2019-03-18 02:19:45 +01:00
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#as: -O0
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X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
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#objdump: -drw
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2018-11-06 11:40:25 +01:00
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#name: pseudo prefixes
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X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c5 f8 29 fa vmovaps %xmm7,%xmm2
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+[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%eax\),%xmm2
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+[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
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+[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
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+[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%eax\),%xmm2
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+[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
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+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
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+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
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+[a-f0-9]+: 89 c8 mov %ecx,%eax
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+[a-f0-9]+: 8b c1 mov %ecx,%eax
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2018-09-13 11:05:27 +02:00
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+[a-f0-9]+: 89 c8 mov %ecx,%eax
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+[a-f0-9]+: 11 c8 adc %ecx,%eax
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+[a-f0-9]+: 13 c1 adc %ecx,%eax
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+[a-f0-9]+: 11 c8 adc %ecx,%eax
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+[a-f0-9]+: 01 c8 add %ecx,%eax
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+[a-f0-9]+: 03 c1 add %ecx,%eax
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+[a-f0-9]+: 01 c8 add %ecx,%eax
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+[a-f0-9]+: 21 c8 and %ecx,%eax
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+[a-f0-9]+: 23 c1 and %ecx,%eax
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+[a-f0-9]+: 21 c8 and %ecx,%eax
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+[a-f0-9]+: 39 c8 cmp %ecx,%eax
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+[a-f0-9]+: 3b c1 cmp %ecx,%eax
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+[a-f0-9]+: 39 c8 cmp %ecx,%eax
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+[a-f0-9]+: 09 c8 or %ecx,%eax
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+[a-f0-9]+: 0b c1 or %ecx,%eax
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+[a-f0-9]+: 09 c8 or %ecx,%eax
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+[a-f0-9]+: 19 c8 sbb %ecx,%eax
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+[a-f0-9]+: 1b c1 sbb %ecx,%eax
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+[a-f0-9]+: 19 c8 sbb %ecx,%eax
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+[a-f0-9]+: 29 c8 sub %ecx,%eax
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+[a-f0-9]+: 2b c1 sub %ecx,%eax
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+[a-f0-9]+: 29 c8 sub %ecx,%eax
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+[a-f0-9]+: 31 c8 xor %ecx,%eax
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+[a-f0-9]+: 33 c1 xor %ecx,%eax
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+[a-f0-9]+: 31 c8 xor %ecx,%eax
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+[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
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+[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
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+[a-f0-9]+: a1 78 56 34 12 mov 0x12345678,%eax
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+[a-f0-9]+: a3 78 56 34 12 mov %eax,0x12345678
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+[a-f0-9]+: 89 07 mov %eax,\(%edi\)
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+[a-f0-9]+: 8b 07 mov \(%edi\),%eax
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+[a-f0-9]+: 89 07 mov %eax,\(%edi\)
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+[a-f0-9]+: 8b 07 mov \(%edi\),%eax
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+[a-f0-9]+: 8c c7 mov %es,%edi
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+[a-f0-9]+: 8e e8 mov %eax,%gs
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+[a-f0-9]+: 8c c7 mov %es,%edi
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+[a-f0-9]+: 8e e8 mov %eax,%gs
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+[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
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+[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
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+[a-f0-9]+: 0f 20 c7 mov %cr0,%edi
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+[a-f0-9]+: 0f 22 f8 mov %eax,%cr7
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+[a-f0-9]+: 0f 21 c7 mov %db0,%edi
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+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
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+[a-f0-9]+: 0f 21 c7 mov %db0,%edi
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+[a-f0-9]+: 0f 23 f8 mov %eax,%db7
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2018-09-13 11:07:07 +02:00
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+[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
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+[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
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+[a-f0-9]+: c5 f9 93 f8 kmovb %k0,%edi
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+[a-f0-9]+: c5 f9 92 f8 kmovb %eax,%k7
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+[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
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+[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
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+[a-f0-9]+: c5 fb 93 f8 kmovd %k0,%edi
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+[a-f0-9]+: c5 fb 92 f8 kmovd %eax,%k7
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+[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
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+[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
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+[a-f0-9]+: c5 f8 93 f8 kmovw %k0,%edi
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+[a-f0-9]+: c5 f8 92 f8 kmovw %eax,%k7
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+[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
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+[a-f0-9]+: c5 f9 90 f8 kmovb %k0,%k7
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+[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
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+[a-f0-9]+: c4 e1 f9 90 f8 kmovd %k0,%k7
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+[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
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+[a-f0-9]+: c4 e1 f8 90 f8 kmovq %k0,%k7
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+[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
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+[a-f0-9]+: c5 f8 90 f8 kmovw %k0,%k7
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2018-09-13 11:05:27 +02:00
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+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
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+[a-f0-9]+: 13 07 adc \(%edi\),%eax
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+[a-f0-9]+: 11 07 adc %eax,\(%edi\)
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+[a-f0-9]+: 13 07 adc \(%edi\),%eax
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+[a-f0-9]+: 01 07 add %eax,\(%edi\)
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+[a-f0-9]+: 03 07 add \(%edi\),%eax
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+[a-f0-9]+: 01 07 add %eax,\(%edi\)
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+[a-f0-9]+: 03 07 add \(%edi\),%eax
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+[a-f0-9]+: 21 07 and %eax,\(%edi\)
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+[a-f0-9]+: 23 07 and \(%edi\),%eax
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+[a-f0-9]+: 21 07 and %eax,\(%edi\)
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+[a-f0-9]+: 23 07 and \(%edi\),%eax
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+[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
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+[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
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+[a-f0-9]+: 39 07 cmp %eax,\(%edi\)
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+[a-f0-9]+: 3b 07 cmp \(%edi\),%eax
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+[a-f0-9]+: 09 07 or %eax,\(%edi\)
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+[a-f0-9]+: 0b 07 or \(%edi\),%eax
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+[a-f0-9]+: 09 07 or %eax,\(%edi\)
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+[a-f0-9]+: 0b 07 or \(%edi\),%eax
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+[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
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+[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
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+[a-f0-9]+: 19 07 sbb %eax,\(%edi\)
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+[a-f0-9]+: 1b 07 sbb \(%edi\),%eax
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+[a-f0-9]+: 29 07 sub %eax,\(%edi\)
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+[a-f0-9]+: 2b 07 sub \(%edi\),%eax
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+[a-f0-9]+: 29 07 sub %eax,\(%edi\)
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+[a-f0-9]+: 2b 07 sub \(%edi\),%eax
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+[a-f0-9]+: 31 07 xor %eax,\(%edi\)
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+[a-f0-9]+: 33 07 xor \(%edi\),%eax
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+[a-f0-9]+: 31 07 xor %eax,\(%edi\)
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+[a-f0-9]+: 33 07 xor \(%edi\),%eax
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+[a-f0-9]+: d8 c0 fadd %st\(0\),%st
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+[a-f0-9]+: d8 c0 fadd %st\(0\),%st
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+[a-f0-9]+: dc c0 fadd %st,%st\(0\)
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+[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
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+[a-f0-9]+: d8 f0 fdiv %st\(0\),%st
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+[a-f0-9]+: dc f0 fdiv %st,%st\(0\)
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+[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
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+[a-f0-9]+: d8 f8 fdivr %st\(0\),%st
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+[a-f0-9]+: dc f8 fdivr %st,%st\(0\)
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+[a-f0-9]+: d8 c8 fmul %st\(0\),%st
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+[a-f0-9]+: d8 c8 fmul %st\(0\),%st
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+[a-f0-9]+: dc c8 fmul %st,%st\(0\)
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+[a-f0-9]+: d8 e0 fsub %st\(0\),%st
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+[a-f0-9]+: d8 e0 fsub %st\(0\),%st
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+[a-f0-9]+: dc e0 fsub %st,%st\(0\)
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+[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
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+[a-f0-9]+: d8 e8 fsubr %st\(0\),%st
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+[a-f0-9]+: dc e8 fsubr %st,%st\(0\)
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+[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
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+[a-f0-9]+: 0f 6f f8 movq %mm0,%mm7
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+[a-f0-9]+: 0f 7f c7 movq %mm0,%mm7
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+[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
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+[a-f0-9]+: 0f 28 f8 movaps %xmm0,%xmm7
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+[a-f0-9]+: 0f 29 c7 movaps %xmm0,%xmm7
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+[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
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+[a-f0-9]+: 0f 10 f8 movups %xmm0,%xmm7
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+[a-f0-9]+: 0f 11 c7 movups %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 10 f8 movss %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 11 c7 movss %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 28 f8 movapd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 29 c7 movapd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 10 f8 movupd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 11 c7 movupd %xmm0,%xmm7
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+[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
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+[a-f0-9]+: f2 0f 10 f8 movsd %xmm0,%xmm7
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+[a-f0-9]+: f2 0f 11 c7 movsd %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 6f f8 movdqa %xmm0,%xmm7
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+[a-f0-9]+: 66 0f 7f c7 movdqa %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 6f f8 movdqu %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 7f c7 movdqu %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
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+[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
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+[a-f0-9]+: 66 0f d6 c7 movq %xmm0,%xmm7
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+[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
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+[a-f0-9]+: c5 f8 28 f8 vmovaps %xmm0,%xmm7
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+[a-f0-9]+: c5 f8 29 c7 vmovaps %xmm0,%xmm7
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+[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
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|
+[a-f0-9]+: 62 f1 7c 48 28 f8 vmovaps %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 48 29 c7 vmovaps %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 28 f8 vmovaps %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 29 c7 vmovaps %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 48 10 f8 vmovups %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 48 11 c7 vmovups %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f8 10 f8 vmovups %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f8 11 c7 vmovups %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 10 f8 vmovups %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 0f 11 c7 vmovups %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f2 10 f8 vmovss %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f2 11 c7 vmovss %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 76 0f 10 f8 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 76 0f 11 c7 vmovss %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 28 f8 vmovapd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 29 c7 vmovapd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 28 f8 vmovapd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 29 c7 vmovapd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 28 f8 vmovapd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 29 c7 vmovapd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 10 f8 vmovupd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 11 c7 vmovupd %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 10 f8 vmovupd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 11 c7 vmovupd %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 10 f8 vmovupd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 0f 11 c7 vmovupd %xmm0,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f3 10 f8 vmovsd %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f3 11 c7 vmovsd %xmm0,%xmm1,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 f7 0f 10 f8 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: 62 f1 f7 0f 11 c7 vmovsd %xmm0,%xmm1,%xmm7\{%k7\}
|
|
|
|
|
+[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 6f f8 vmovdqa %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 7f c7 vmovdqa %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 48 6f f8 vmovdqa32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 48 7f c7 vmovdqa32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 08 6f f8 vmovdqa32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 08 7f c7 vmovdqa32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 6f f8 vmovdqa64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 48 7f c7 vmovdqa64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 08 6f f8 vmovdqa64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 08 7f c7 vmovdqa64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 fa 6f f8 vmovdqu %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 fa 7f c7 vmovdqu %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 48 6f f8 vmovdqu8 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 08 6f f8 vmovdqu8 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7f 48 7f c7 vmovdqu8 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 48 6f f8 vmovdqu16 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 48 7f c7 vmovdqu16 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 08 6f f8 vmovdqu16 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 ff 08 7f c7 vmovdqu16 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 48 6f f8 vmovdqu32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 48 7f c7 vmovdqu32 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 08 6f f8 vmovdqu32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 7e 08 7f c7 vmovdqu32 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 48 6f f8 vmovdqu64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 48 7f c7 vmovdqu64 %zmm0,%zmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 08 6f f8 vmovdqu64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 08 7f c7 vmovdqu64 %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
|
|
|
|
|
+[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
|
2018-11-06 11:40:25 +01:00
|
|
|
+[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: 66 0f 3a 15 c7 00 pextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: c4 e3 79 15 c7 00 vpextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
|
|
|
|
|
+[a-f0-9]+: 62 f3 7d 08 15 c7 00 vpextrw \$0x0,%xmm0,%edi
|
2018-09-13 11:05:27 +02:00
|
|
|
+[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
|
|
|
|
|
+[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
|
|
|
|
|
+[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
|
|
|
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 50 00 movaps 0x0\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 90 00 00 00 00 movaps 0x0\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 50 ff movaps -0x1\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 50 ff movaps -0x1\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 90 ff ff ff ff movaps -0x1\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
|
2020-07-28 12:41:16 +02:00
|
|
|
+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
|
|
|
|
|
+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
|
|
|
|
|
+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
|
|
|
|
|
+[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
|
|
|
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c4 e1 78 28 d7 vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c4 e1 78 29 fa vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 d7 vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 29 fa vmovaps %xmm7,%xmm2
|
|
|
|
|
+[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
|
|
|
|
|
+[a-f0-9]+: 89 c8 mov %ecx,%eax
|
|
|
|
|
+[a-f0-9]+: 8b c1 mov %ecx,%eax
|
2018-09-13 11:05:27 +02:00
|
|
|
+[a-f0-9]+: 89 c8 mov %ecx,%eax
|
X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
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+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 10 movaps \(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 50 00 movaps 0x0\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 00 00 00 00 movaps 0x0\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 50 ff movaps -0x1\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 50 ff movaps -0x1\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 ff ff ff ff movaps -0x1\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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+[a-f0-9]+: 0f 28 90 80 00 00 00 movaps 0x80\(%eax\),%xmm2
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2020-07-28 12:41:16 +02:00
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 45 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 8a 85 00 00 00 00 mov 0x0\(%ebp\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 07 mov \(%bx\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 46 00 mov 0x0\(%bp\),%al
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+[a-f0-9]+: 67 8a 86 00 00 mov 0x0\(%bp\),%al
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X86: Add pseudo prefixes to control encoding
Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
2017-03-09 18:58:46 +01:00
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#pass
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