2018-08-09 18:46:01 +02:00
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/* Target-dependent header for the RISC-V architecture, for GDB, the
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GNU Debugger.
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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2020-01-01 07:20:01 +01:00
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Copyright (C) 2018-2020 Free Software Foundation, Inc.
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef RISCV_TDEP_H
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#define RISCV_TDEP_H
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gdb/riscv: Add target description support
This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
2018-10-29 16:10:52 +01:00
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#include "arch/riscv.h"
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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/* RiscV register numbers. */
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enum
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{
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RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
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RISCV_RA_REGNUM = 1, /* Return Address. */
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RISCV_SP_REGNUM = 2, /* Stack Pointer. */
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RISCV_GP_REGNUM = 3, /* Global Pointer. */
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RISCV_TP_REGNUM = 4, /* Thread Pointer. */
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RISCV_FP_REGNUM = 8, /* Frame Pointer. */
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RISCV_A0_REGNUM = 10, /* First argument. */
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RISCV_A1_REGNUM = 11, /* Second argument. */
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RISCV_PC_REGNUM = 32, /* Program Counter. */
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2018-07-17 16:22:39 +02:00
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RISCV_NUM_INTEGER_REGS = 32,
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
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RISCV_FA0_REGNUM = 43,
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RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
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RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
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RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
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[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR
1. Remove the -mriscv-isa-version and --with-riscv-isa-version options.
We can still use -march to choose the version for each extensions, so there is
no need to add these.
2. Change the arguments of options from [1p9|1p9p1|...] to [1.9|1.9.1|...].
Unlike the architecture string has specified by spec, ther is no need to do
the same thing for options.
3. Spilt the patches to reduce the burdens of review.
[PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions
to
[PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions
[PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default.
[PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version.
to
[PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version.
[PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version.
4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c.
The behavior is same as comparing the choosen privilege spec.
include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean.
(enum riscv_isa_spec_class): New enum class. All supported ISA spec
belong to one of the class
(struct riscv_ext_version): New structure holds version information
for the specific ISA.
* opcode/riscv-opc.h (DECLARE_CSR): There are two version information,
define_version and abort_version. The define_version means which
privilege spec is started to define the CSR, and the abort_version
means which privilege spec is started to abort the CSR. If the CSR is
valid for the newest spec, then the abort_version should be
PRIV_SPEC_CLASS_DRAFT.
(DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR.
* opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define
the current supported privilege spec versions.
(struct riscv_csr_extra): Add new fields to store more information
about the CSR. We use these information to find the suitable CSR
address when user choosing a specific privilege spec.
binutils * dwarf.c: Updated since DECLARE_CSR is changed.
opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store
all information about the supported spec and the corresponding ISA
versions. Currently, only Zicsr is supported to verify the
correctness of Z sub extension settings. Others will be supported
in the future patches.
(struct isa_spec_t, isa_specs): List for all supported ISA spec
classes and the corresponding strings.
(riscv_get_isa_spec_class): New function. Get the corresponding ISA
spec class by giving a ISA spec string.
* riscv-opc.c (struct priv_spec_t): New structure.
(struct priv_spec_t priv_specs): List for all supported privilege spec
classes and the corresponding strings.
(riscv_get_priv_spec_class): New function. Get the corresponding
privilege spec class by giving a spec string.
(riscv_get_priv_spec_name): New function. Get the corresponding
privilege spec string by giving a CSR version class.
* riscv-dis.c: Updated since DECLARE_CSR is changed.
* riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
according to the chosen version. Build a hash table riscv_csr_hash to
store the valid CSR for the chosen pirv verison. Dump the direct
CSR address rather than it's name if it is invalid.
(parse_riscv_dis_option_without_args): New function. Parse the options
without arguments.
(parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
parse the options without arguments first, and then handle the options
with arguments. Add the new option -Mpriv-spec, which has argument.
* riscv-dis.c (print_riscv_disassembler_options): Add description
about the new OBJDUMP option.
ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated
priv attributes according to the -mpriv-spec option.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function
get_default_version. It is used to find the default version for
the specific extension.
* elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters
default_major_version and default_minor_version. Add new bfd_boolean
parameter *use_default_version. Set it to TRUE if we need to call
the callback rps->get_default_version to find the default version.
(riscv_parse_std_ext): Call rps->get_default_version if we fail to find
the default version in riscv_parsing_subset_version, and then call
riscv_add_subset to add the subset into subset list.
(riscv_parse_prefixed_ext): Likewise.
(riscv_std_z_ext_strtab): Support Zicsr extensions.
* elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the
strings rather than characters.
riscv_merge_arch_attr_info): The callback function get_default_version
is only needed for assembler, so set it to NULL int the linker.
* elfxx-riscv.c (riscv_estimate_digit): Remove the static.
* elfxx-riscv.h: Updated.
gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated.
* config/tc-riscv.c (default_arch_with_ext, default_isa_spec):
Static variables which are used to set the ISA extensions. You can
use -march (or ELF build attributes) and -misa-spec to set them,
respectively.
(ext_version_hash): The hash table used to handle the extensions
with versions.
(init_ext_version_hash): Initialize the ext_version_hash according
to riscv_ext_version_table.
(riscv_get_default_ext_version): The callback function of
riscv_parse_subset_t. According to the choosed ISA spec,
get the default version for the specific extension.
(riscv_set_arch): Set the callback function.
(enum options, struct option md_longopts): Add new option -misa-spec.
(md_parse_option): Do not call riscv_set_arch for -march. We will
call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class
to set default_isa_spec class.
(riscv_after_parse_args): Call init_ext_version_hash to initialize the
ext_version_hash, and then call riscv_set_arch to set the architecture
with versions according to default_arch_with_ext.
* testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for
x extensions.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we
already set it's version to 2p1 by march, so no need to use the default
2p2 version. For m-ext, we do not set the version by -march and ELF arch
attribute, so set the default 2p0 to it. For zicsr, it is not defined in
ISA spec 2p2, so set 0p0 to it.
* testsuite/gas/riscv/attribute-10.d: New testcase. The version of
zicsr is 2p0 according to ISA spec 20191213.
* config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT)
(DEFAULT_RISCV_ISA_SPEC): Default configure option settings.
You can set them by configure options --with-arch and
--with-isa-spec, respectively.
(riscv_set_default_isa_spec): New function used to set the
default ISA spec.
(md_parse_option): Call riscv_set_default_isa_spec rather than
call riscv_get_isa_spec_class directly.
(riscv_after_parse_args): If the -isa-spec is not set, then we
set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by
calling riscv_set_default_isa_spec.
* testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since
the --with-isa-spec may be set to different ISA spec.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* configure.ac: Add configure options, --with-arch and
--with-isa-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (default_priv_spec): Static variable which is
used to check if the CSR is valid for the chosen privilege spec. You
can use -mpriv-spec to set it.
(enum reg_class): We now get the CSR address from csr_extra_hash rather
than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX.
(riscv_init_csr_hashes): Only need to initialize one hash table
csr_extra_hash.
(riscv_csr_class_check): Change the return type to void. Don't check
the ISA dependency if -mcsr-check isn't set.
(riscv_csr_version_check): New function. Check and find the CSR address
from csr_extra_hash, according to default_priv_spec. Report warning
for the invalid CSR if -mcsr-check is set.
(reg_csr_lookup_internal): Updated.
(reg_lookup_internal): Likewise.
(md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed.
(enum options, struct option md_longopts): Add new GAS option -mpriv-spec.
(md_parse_option): Call riscv_set_default_priv_version to set
default_priv_spec.
(riscv_after_parse_args): If -mpriv-spec isn't set, then set the default
privilege spec to the newest one.
(enum riscv_csr_class, struct riscv_csr_extra): Move them to
include/opcode/riscv.h.
* testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want
to check the ISA dependency for CSR, so fix the spec version by adding
-mpriv-spec=1.11.
* testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some
version warnings for the test case.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case.
Check whether the CSR is valid when privilege version 1.9 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case.
Check whether the CSR is valid when privilege version 1.9.1 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case.
Check whether the CSR is valid when privilege version 1.10 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case.
Check whether the CSR is valid when privilege version 1.11 is choosed.
* gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise.
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option
setting. You can set it by configure option --with-priv-spec.
(riscv_set_default_priv_spec): New function used to set the default
privilege spec.
(md_parse_option): Call riscv_set_default_priv_spec rather than
call riscv_get_priv_spec_class directly.
(riscv_after_parse_args): If -mpriv-spec isn't set, then we set the
default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by
calling riscv_set_default_priv_spec.
* testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since
the --with-priv-spec may be set to different privilege spec.
* testsuite/gas/riscv/priv-reg.d: Likewise.
* configure.ac: Add configure option --with-priv-spec.
* configure: Regenerated.
* config.in: Regenerated.
* config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to
explicit_attr. Set it to TRUE if any ELF attribute is found.
(riscv_set_default_priv_spec): Try to set the default_priv_spec if
the priv attributes are set.
(md_assemble): Set the default_priv_spec according to the priv
attributes when we start to assemble instruction.
(riscv_write_out_attrs): Rename riscv_write_out_arch_attr to
riscv_write_out_attrs. Update the arch and priv attributes. If we
don't set the corresponding ELF attributes, then try to output the
default ones.
(riscv_set_public_attributes): If any ELF attribute or -march-attr
options is set (explicit_attr is TRUE), then call riscv_write_out_attrs
to update the arch and priv attributes.
(s_riscv_attribute): Make sure all arch and priv attributes are set
before any instruction.
* testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any
ELF attribute or -march-attr is set. If the priv attributes are not
set, then try to update them by the default setting (-mpriv-spec or
--with-priv-spec).
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec
set by priv attributes must be supported.
* testsuite/gas/riscv/attribute-05.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated
priv attributes according to the -mpriv-spec option.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg.d: Removed.
* testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the
CSR according to the priv spec 1.9.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the
CSR according to the priv spec 1.9.1.
* testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the
CSR according to the priv spec 1.10.
* testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the
CSR according to the priv spec 1.11.
* config/tc-riscv.c (md_show_usage): Add descriptions about
the new GAS options.
* doc/c-riscv.texi: Likewise.
2020-05-20 18:22:48 +02:00
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#define DECLARE_CSR(name, num, class, define_version, abort_version) \
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2018-08-09 18:46:01 +02:00
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RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
|
gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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#include "opcode/riscv-opc.h"
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#undef DECLARE_CSR
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RISCV_LAST_CSR_REGNUM = 4160,
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2018-07-17 18:42:23 +02:00
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RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
|
gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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RISCV_PRIV_REGNUM = 4161,
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RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
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};
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2018-12-13 18:57:14 +01:00
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/* RiscV DWARF register numbers. */
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enum
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{
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RISCV_DWARF_REGNUM_X0 = 0,
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RISCV_DWARF_REGNUM_X31 = 31,
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RISCV_DWARF_REGNUM_F0 = 32,
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RISCV_DWARF_REGNUM_F31 = 63,
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};
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gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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/* RISC-V specific per-architecture information. */
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struct gdbarch_tdep
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{
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gdb/riscv: Split ISA and ABI features
The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.
The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.
To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.
The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.
A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.
In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense. The asserts were both like this:
gdb_assert (TYPE_LENGTH (ainfo->type)
<= (cinfo->flen + cinfo->xlen));
And were made in two cases, when passing structures like these:
struct {
integer field1;
float field2;
};
or,
struct {
float field1;
integer field2;
};
When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding). In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.
This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC. The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.
Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.
gdb/ChangeLog:
* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
Delete.
<operator==>: Update with for removed field.
<hash>: Likewise.
* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
<isa_features>: ...this.
<abi_features>: New field.
(riscv_isa_flen): Update comment.
(riscv_abi_xlen): New declaration.
(riscv_abi_flen): New declaration.
* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
isa_features.
(riscv_abi_xlen): New function.
(riscv_isa_flen): Update to get answer from isa_features.
(riscv_abi_flen): New function.
(riscv_has_fp_abi): Update to get answer from abi_features.
(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
xlen and flen.
(riscv_call_info) <xlen, flen>: Update comment.
(riscv_call_arg_struct): Remove invalid assertions
(riscv_features_from_gdbarch_info): Update now hw_float_abi field
is removed.
(riscv_gdbarch_init): Gather isa features and abi features
separately, ensure both match on the gdbarch when reusing an old
gdbarch. Relax an error check to allow 32-bit abi float to run on
a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
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/* Features about the target hardware that impact how the gdbarch is
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configured. Two gdbarch instances are compatible only if this field
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matches. */
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struct riscv_gdbarch_features isa_features;
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/* Features about the abi that impact how the gdbarch is configured. Two
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gdbarch instances are compatible only if this field matches. */
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struct riscv_gdbarch_features abi_features;
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2018-10-22 23:10:13 +02:00
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/* ISA-specific data types. */
|
gdb/riscv: Add target description support
This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
2018-10-29 16:10:52 +01:00
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struct type *riscv_fpreg_d_type = nullptr;
|
gdb/riscv: Record information about unknown tdesc registers
Making use of the previous commit, record information about unknown
registers in the target description, and use this to resolve two
issues.
1. Some targets (QEMU) are reporting three register fflags, frm, and
fcsr, twice, once in the FPU feature, and once in the CSR feature.
GDB does create two registers with identical names, but this
is (sort of) fine, we only ever use the first one, and as both
registers access the same target state things basically work OK.
The only real problem is that the register names show up twice in
'info registers all' output.
In this commit we spot the duplicates of these registers and then
return NULL when asked for the name of these registers. This
causes GDB to hide these registers from the user, fixing this
problem.
2. Some targets (QEMU) advertise CSRs that GDB then can't read. The
problem is these targets also say these CSRs are part of the
save/restore register groups.
This means that before an inferior call GDB tries to save all of
these CSRs, and a failure to read one causes the inferior call to
be abandoned.
We already work around this issue to some degree, known CSRs are
removed from the save/restore groups, despite what the target might
say. However, any unknown CSRs are (currently) not removed in this
way.
After this commit we keep a log of the register numbers for all
unknown CSRs, then when asked about the register groups, we
override the group information for unknown CSRs, removing them from
the save and restore groups.
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_name): Return NULL for duplicate
fflags, frm, and fcsr registers.
(riscv_register_reggroup_p): Remove unknown CSRs from save and
restore groups.
(riscv_tdesc_unknown_reg): New function.
(riscv_gdbarch_init): Pass riscv_tdesc_unknown_reg to
tdesc_use_registers.
* riscv-tdep.h (struct gdbarch_tdep): Add
unknown_csrs_first_regnum, unknown_csrs_count,
duplicate_fflags_regnum, duplicate_frm_regnum, and
duplicate_fcsr_regnum fields.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-tdesc-regs.exp: Extend test case.
2020-06-16 15:53:12 +02:00
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/* Use for tracking unknown CSRs in the target description.
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UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
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CSR. All other unknown CSRs will be assigned sequential numbers after
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this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs. */
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int unknown_csrs_first_regnum = -1;
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int unknown_csrs_count = 0;
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/* Some targets (QEMU) are reporting three registers twice in the target
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description they send. These three register numbers, when not set to
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-1, are for the duplicate copies of these registers. */
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int duplicate_fflags_regnum = -1;
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int duplicate_frm_regnum = -1;
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int duplicate_fcsr_regnum = -1;
|
|
|
|
|
|
gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
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};
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2018-10-26 19:29:46 +02:00
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/* Return the width in bytes of the general purpose registers for GDBARCH.
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Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
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RV128. */
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2018-08-08 19:48:09 +02:00
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extern int riscv_isa_xlen (struct gdbarch *gdbarch);
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gdb/riscv: Split ISA and ABI features
The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.
The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.
To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.
The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.
A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.
In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense. The asserts were both like this:
gdb_assert (TYPE_LENGTH (ainfo->type)
<= (cinfo->flen + cinfo->xlen));
And were made in two cases, when passing structures like these:
struct {
integer field1;
float field2;
};
or,
struct {
float field1;
integer field2;
};
When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding). In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.
This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC. The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.
Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.
gdb/ChangeLog:
* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
Delete.
<operator==>: Update with for removed field.
<hash>: Likewise.
* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
<isa_features>: ...this.
<abi_features>: New field.
(riscv_isa_flen): Update comment.
(riscv_abi_xlen): New declaration.
(riscv_abi_flen): New declaration.
* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
isa_features.
(riscv_abi_xlen): New function.
(riscv_isa_flen): Update to get answer from isa_features.
(riscv_abi_flen): New function.
(riscv_has_fp_abi): Update to get answer from abi_features.
(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
xlen and flen.
(riscv_call_info) <xlen, flen>: Update comment.
(riscv_call_arg_struct): Remove invalid assertions
(riscv_features_from_gdbarch_info): Update now hw_float_abi field
is removed.
(riscv_gdbarch_init): Gather isa features and abi features
separately, ensure both match on the gdbarch when reusing an old
gdbarch. Relax an error check to allow 32-bit abi float to run on
a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
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/* Return the width in bytes of the hardware floating point registers for
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GDBARCH. If this architecture has no floating point registers, then
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return 0. Possible values are 4, 8, or 16 for depending on which of
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single, double or quad floating point support is available. */
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2018-10-26 19:29:46 +02:00
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extern int riscv_isa_flen (struct gdbarch *gdbarch);
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gdb/riscv: Split ISA and ABI features
The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.
The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.
To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.
The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.
A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.
In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense. The asserts were both like this:
gdb_assert (TYPE_LENGTH (ainfo->type)
<= (cinfo->flen + cinfo->xlen));
And were made in two cases, when passing structures like these:
struct {
integer field1;
float field2;
};
or,
struct {
float field1;
integer field2;
};
When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding). In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.
This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC. The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.
Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.
gdb/ChangeLog:
* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
Delete.
<operator==>: Update with for removed field.
<hash>: Likewise.
* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
<isa_features>: ...this.
<abi_features>: New field.
(riscv_isa_flen): Update comment.
(riscv_abi_xlen): New declaration.
(riscv_abi_flen): New declaration.
* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
isa_features.
(riscv_abi_xlen): New function.
(riscv_isa_flen): Update to get answer from isa_features.
(riscv_abi_flen): New function.
(riscv_has_fp_abi): Update to get answer from abi_features.
(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
xlen and flen.
(riscv_call_info) <xlen, flen>: Update comment.
(riscv_call_arg_struct): Remove invalid assertions
(riscv_features_from_gdbarch_info): Update now hw_float_abi field
is removed.
(riscv_gdbarch_init): Gather isa features and abi features
separately, ensure both match on the gdbarch when reusing an old
gdbarch. Relax an error check to allow 32-bit abi float to run on
a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
|
|
|
/* Return the width in bytes of the general purpose register abi for
|
|
|
|
|
GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
|
|
|
|
|
how the binary was compiled rather than the hardware that is available.
|
|
|
|
|
It is possible that a binary compiled for RV32 is being run on an RV64
|
|
|
|
|
target, in which case the isa xlen is 8-bytes, and the abi xlen is
|
|
|
|
|
4-bytes. This will impact how inferior functions are called. */
|
|
|
|
|
extern int riscv_abi_xlen (struct gdbarch *gdbarch);
|
|
|
|
|
|
|
|
|
|
/* Return the width in bytes of the floating point register abi for
|
|
|
|
|
GDBARCH. This reflects how the binary was compiled rather than the
|
|
|
|
|
hardware that is available. It is possible that a binary is compiled
|
|
|
|
|
for single precision floating point, and then run on a target with
|
|
|
|
|
double precision floating point. A return value of 0 indicates that no
|
|
|
|
|
floating point abi is in use (floating point arguments will be passed
|
|
|
|
|
in integer registers) other possible return value are 4, 8, or 16 as
|
|
|
|
|
with RISCV_ISA_FLEN. */
|
|
|
|
|
extern int riscv_abi_flen (struct gdbarch *gdbarch);
|
|
|
|
|
|
RISC-V: Add software single step support.
This adds software single step support that is needed by the linux native port.
This is modeled after equivalent code in the MIPS port.
This also fixes a few bugs in the compressed instruction decode support. Some
instructions are RV32/RV64 specific, and this wasn't being checked. Also, a
few instructions were accidentally using the non-compressed is_* function.
This has been tested on a HiFive Unleashed running Fedora, by putting a
breakpoint on start, typing stepi, and then holding down the return key until
it finishes, and observing that I see everything I expect to see along the way.
There is a problem in _dl_addr where I get into an infinite loop, but it seems
to be some synchronization code that doesn't agree with single step, so I have
to find the end of the loop, put a breakpoint there, continue, and then single
step again until the end.
gdb/
* riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
(decode_register_index_short): New.
(decode_j_type_insn, decode_cj_type_insn): New.
(decode_b_type_insn, decode_cb_type_insn): New.
(riscv_insn::decode): Add support for jumps, branches, lr, and sc. New
local xlen. Check xlen when decoding ambiguous compressed insns. In
compressed decode, use is_c_lui_insn instead of is_lui_insn, and
is_c_sw_insn instead of is_sw_insn.
(riscv_next_pc, riscv_next_pc_atomic_sequence): New.
(riscv_software_single_step): New.
* riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-08 19:53:12 +02:00
|
|
|
/* Single step based on where the current instruction will take us. */
|
2018-08-09 18:46:01 +02:00
|
|
|
extern std::vector<CORE_ADDR> riscv_software_single_step
|
|
|
|
|
(struct regcache *regcache);
|
RISC-V: Add software single step support.
This adds software single step support that is needed by the linux native port.
This is modeled after equivalent code in the MIPS port.
This also fixes a few bugs in the compressed instruction decode support. Some
instructions are RV32/RV64 specific, and this wasn't being checked. Also, a
few instructions were accidentally using the non-compressed is_* function.
This has been tested on a HiFive Unleashed running Fedora, by putting a
breakpoint on start, typing stepi, and then holding down the return key until
it finishes, and observing that I see everything I expect to see along the way.
There is a problem in _dl_addr where I get into an infinite loop, but it seems
to be some synchronization code that doesn't agree with single step, so I have
to find the end of the loop, put a breakpoint there, continue, and then single
step again until the end.
gdb/
* riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
(decode_register_index_short): New.
(decode_j_type_insn, decode_cj_type_insn): New.
(decode_b_type_insn, decode_cb_type_insn): New.
(riscv_insn::decode): Add support for jumps, branches, lr, and sc. New
local xlen. Check xlen when decoding ambiguous compressed insns. In
compressed decode, use is_c_lui_insn instead of is_lui_insn, and
is_c_sw_insn instead of is_sw_insn.
(riscv_next_pc, riscv_next_pc_atomic_sequence): New.
(riscv_software_single_step): New.
* riscv-tdep.h (riscv_software_single_step): Declare.
2018-08-08 19:53:12 +02:00
|
|
|
|
gdb: Initial baremetal riscv support
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
2017-11-09 21:59:13 +01:00
|
|
|
#endif /* RISCV_TDEP_H */
|
