1999-05-03 09:29:11 +02:00
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/* Table of opcodes for the sparc.
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2001-03-13 23:58:38 +01:00
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2012-05-17 17:13:28 +02:00
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2000, 2002, 2004, 2005, 2006, 2007, 2008, 2011, 2012
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1999-05-03 09:29:11 +02:00
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Free Software Foundation, Inc.
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2007-07-05 11:49:03 +02:00
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This file is part of the GNU opcodes library.
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1999-05-03 09:29:11 +02:00
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2007-07-05 11:49:03 +02:00
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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1999-05-03 09:29:11 +02:00
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2007-07-05 11:49:03 +02:00
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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1999-05-03 09:29:11 +02:00
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2005-07-01 13:16:33 +02:00
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You should have received a copy of the GNU General Public License
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2007-07-05 11:49:03 +02:00
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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1999-05-03 09:29:11 +02:00
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/* FIXME-someday: perhaps the ,a's and such should be embedded in the
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instruction's name rather than the args. This would make gas faster, pinsn
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slower, but would mess up some macros a bit. xoxorich. */
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2000-04-14 06:16:58 +02:00
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#include "sysdep.h"
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2012-05-17 17:13:28 +02:00
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#include <stdio.h>
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1999-05-03 09:29:11 +02:00
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#include "opcode/sparc.h"
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/* Some defines to make life easy. */
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#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
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#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
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#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
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2013-08-05 18:11:07 +02:00
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#define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON)
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1999-05-03 09:29:11 +02:00
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#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
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#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
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#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
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#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
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2000-10-20 12:38:47 +02:00
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#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
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1999-05-03 09:29:11 +02:00
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/* Bit masks of architectures supporting the insn. */
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2013-08-05 18:11:07 +02:00
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#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
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| MASK_SPARCLET | MASK_SPARCLITE \
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| MASK_V9 | MASK_V9A | MASK_V9B)
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2005-07-01 13:16:33 +02:00
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/* v6 insns not supported on the sparclet. */
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2013-08-05 18:11:07 +02:00
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#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
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2000-10-20 12:38:47 +02:00
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
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2013-08-05 18:11:07 +02:00
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#define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
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2000-10-20 12:38:47 +02:00
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| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
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1999-05-03 09:29:11 +02:00
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/* Although not all insns are implemented in hardware, sparclite is defined
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to be a superset of v8. Unimplemented insns trap and are then theoretically
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implemented in software.
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It's not clear that the same is true for sparclet, although the docs
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suggest it is. Rather than complicating things, the sparclet assembler
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recognizes all v8 insns. */
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2013-08-05 18:11:07 +02:00
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#define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
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2000-10-20 12:38:47 +02:00
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| MASK_V9 | MASK_V9A | MASK_V9B)
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1999-05-03 09:29:11 +02:00
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#define sparclet (MASK_SPARCLET)
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2013-08-05 18:11:07 +02:00
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/* sparclet insns supported by leon. */
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#define letandleon (MASK_SPARCLET | MASK_LEON)
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1999-05-03 09:29:11 +02:00
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#define sparclite (MASK_SPARCLITE)
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2000-10-20 12:38:47 +02:00
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#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
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2013-08-05 19:04:08 +02:00
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/* v9 insns supported by leon. */
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#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B | MASK_LEON)
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2000-10-20 12:38:47 +02:00
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#define v9a (MASK_V9A | MASK_V9B)
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#define v9b (MASK_V9B)
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2005-07-01 13:16:33 +02:00
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/* v6 insns not supported by v9. */
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2013-08-05 18:11:07 +02:00
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#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
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1999-05-03 09:29:11 +02:00
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| MASK_SPARCLET | MASK_SPARCLITE)
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/* v9a instructions which would appear to be aliases to v9's impdep's
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2005-07-01 13:16:33 +02:00
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otherwise. */
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1999-05-03 09:29:11 +02:00
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#define v9notv9a (MASK_V9)
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/* Table of opcode architectures.
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The order is defined in opcode/sparc.h. */
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2005-07-01 13:16:33 +02:00
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const struct sparc_opcode_arch sparc_opcode_archs[] =
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{
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1999-05-03 09:29:11 +02:00
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{ "v6", MASK_V6 },
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{ "v7", MASK_V6 | MASK_V7 },
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{ "v8", MASK_V6 | MASK_V7 | MASK_V8 },
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2013-08-05 18:11:07 +02:00
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{ "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON },
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1999-05-03 09:29:11 +02:00
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{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
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{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
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/* ??? Don't some v8 priviledged insns conflict with v9? */
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{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
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/* v9 with ultrasparc additions */
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{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
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2000-10-20 12:38:47 +02:00
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/* v9 with cheetah additions */
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{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
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1999-05-03 09:29:11 +02:00
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{ NULL, 0 }
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};
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/* Given NAME, return it's architecture entry. */
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enum sparc_opcode_arch_val
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2005-07-01 13:16:33 +02:00
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sparc_opcode_lookup_arch (const char *name)
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1999-05-03 09:29:11 +02:00
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{
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const struct sparc_opcode_arch *p;
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for (p = &sparc_opcode_archs[0]; p->name; ++p)
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2005-07-01 13:16:33 +02:00
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if (strcmp (name, p->name) == 0)
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return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
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1999-05-03 09:29:11 +02:00
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return SPARC_OPCODE_ARCH_BAD;
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}
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/* Branch condition field. */
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2005-07-01 13:16:33 +02:00
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#define COND(x) (((x) & 0xf) << 25)
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1999-05-03 09:29:11 +02:00
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2012-04-27 20:03:13 +02:00
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/* Compare And Branch condition field. */
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#define CBCOND(x) (((x) & 0x1f) << 25)
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1999-05-03 09:29:11 +02:00
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/* v9: Move (MOVcc and FMOVcc) condition field. */
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2005-07-01 13:16:33 +02:00
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#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
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1999-05-03 09:29:11 +02:00
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/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
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2005-07-01 13:16:33 +02:00
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#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
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#define CONDA (COND (0x8))
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#define CONDCC (COND (0xd))
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#define CONDCS (COND (0x5))
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#define CONDE (COND (0x1))
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#define CONDG (COND (0xa))
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#define CONDGE (COND (0xb))
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#define CONDGU (COND (0xc))
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#define CONDL (COND (0x3))
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#define CONDLE (COND (0x2))
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#define CONDLEU (COND (0x4))
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#define CONDN (COND (0x0))
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#define CONDNE (COND (0x9))
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#define CONDNEG (COND (0x6))
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#define CONDPOS (COND (0xe))
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#define CONDVC (COND (0xf))
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#define CONDVS (COND (0x7))
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1999-05-03 09:29:11 +02:00
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#define CONDNZ CONDNE
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#define CONDZ CONDE
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#define CONDGEU CONDCC
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#define CONDLU CONDCS
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2005-07-01 13:16:33 +02:00
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#define FCONDA (COND (0x8))
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#define FCONDE (COND (0x9))
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#define FCONDG (COND (0x6))
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#define FCONDGE (COND (0xb))
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#define FCONDL (COND (0x4))
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#define FCONDLE (COND (0xd))
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#define FCONDLG (COND (0x2))
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#define FCONDN (COND (0x0))
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#define FCONDNE (COND (0x1))
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#define FCONDO (COND (0xf))
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#define FCONDU (COND (0x7))
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#define FCONDUE (COND (0xa))
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#define FCONDUG (COND (0x5))
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#define FCONDUGE (COND (0xc))
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#define FCONDUL (COND (0x3))
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#define FCONDULE (COND (0xe))
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1999-05-03 09:29:11 +02:00
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#define FCONDNZ FCONDNE
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#define FCONDZ FCONDE
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2005-07-01 13:16:33 +02:00
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#define ICC (0) /* v9 */
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#define XCC (1 << 12) /* v9 */
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2012-04-27 20:03:13 +02:00
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#define CBCOND_XCC (1 << 21)
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2005-07-01 13:16:33 +02:00
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#define FCC(x) (((x) & 0x3) << 11) /* v9 */
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#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
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1999-05-03 09:29:11 +02:00
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/* The order of the opcodes in the table is significant:
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2005-07-01 13:16:33 +02:00
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1999-05-03 09:29:11 +02:00
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* The assembler requires that all instances of the same mnemonic must
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be consecutive. If they aren't, the assembler will bomb at runtime.
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2005-07-01 13:16:33 +02:00
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* The disassembler should not care about the order of the opcodes. */
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1999-05-03 09:29:11 +02:00
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/* Entries for commutative arithmetic operations. */
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/* ??? More entries can make use of this. */
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#define COMMUTEOP(opcode, op3, arch_mask) \
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, arch_mask }, \
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{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, arch_mask }, \
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{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, arch_mask }
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1999-05-03 09:29:11 +02:00
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const struct sparc_opcode sparc_opcodes[] = {
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, v6 },
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{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, v6 }, /* ld [rs1+%g0],d */
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{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, v6 },
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{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, v6 },
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{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ld [rs1+0],d */
|
|
|
|
|
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, v6 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, v6 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, v6 },
|
|
|
|
|
{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, v6notv9 }, /* ld [rs1+0],d */
|
|
|
|
|
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, v6notv9 },
|
|
|
|
|
{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, v6notv9 }, /* ld [rs1+0],d */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
|
|
|
|
|
'ld' pseudo-op in v9. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+%g0],d */
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, v9 },
|
|
|
|
|
{ "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS, 0, v6 }, /* ldd [rs1+0],d */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
|
|
|
|
|
{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, v6notv9 },
|
|
|
|
|
{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, v6notv9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, v9 },
|
|
|
|
|
{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldsb [rs1+%g0],d */
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldsb [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldsh [rs1+%g0],d */
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldsh [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldstub [rs1+%g0],d */
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
|
|
|
|
{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldstub [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v9 }, /* ldsw [rs1+%g0],d */
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, v9 },
|
|
|
|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, v9 },
|
|
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|
|
{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, v9 }, /* ldsw [rs1+0],d */
|
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{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 },
|
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|
{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* ldub [rs1+%g0],d */
|
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|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, v6 },
|
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|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, v6 },
|
|
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|
|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
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|
{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* ldub [rs1+0],d */
|
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|
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|
{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, v6 },
|
|
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|
|
{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v6 }, /* lduh [rs1+%g0],d */
|
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|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, v6 },
|
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|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, v6 },
|
|
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|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, v6 },
|
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|
|
{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, v6 }, /* lduh [rs1+0],d */
|
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|
{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v9 }, /* ldx [rs1+%g0],d */
|
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|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, v9 },
|
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|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, v9 },
|
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|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, v9 },
|
|
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|
|
{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, v9 }, /* ldx [rs1+0],d */
|
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|
{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, 0, v9 }, /* ld [rs1+%g0],d */
|
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|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, v9 },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, v9 }, /* ld [rs1+0],d */
|
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|
|
|
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|
|
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, v9b },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, v9b },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, v9b },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, v9b },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, v9b },
|
|
|
|
|
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, v9b },
|
|
|
|
|
|
|
|
|
|
{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, v6 },
|
|
|
|
|
{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, v9 },
|
|
|
|
|
{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, v9 }, /* ldda [rs1+%g0],d */
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, v6 }, /* ldda [rs1+%g0],d */
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
|
|
|
|
|
{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, v9 }, /* ldda [rs1+%g0],d */
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, v9 },
|
|
|
|
|
{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, v9 },
|
|
|
|
|
{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, v9 }, /* ldd [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, v6 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldsba [rs1+%g0],d */
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, v6 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldsha [rs1+%g0],d */
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, v6 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* ldstuba [rs1+%g0],d */
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, v6 },
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|
|
|
|
{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lduba [rs1+%g0],d */
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, v9 },
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|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, v6 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, v6 }, /* lduha [rs1+%g0],d */
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|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, v9 },
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|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
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|
|
|
|
|
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|
|
{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, 0, v9 }, /* lduwa === lda */
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, v6 }, /* st d[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, 0, v6 },
|
|
|
|
|
{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+%g0] */
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, v6 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, v6 },
|
|
|
|
|
{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, v6 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, v9 },
|
|
|
|
|
{ "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_PREF_ALIAS, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS, 0, v6 }, /* std d,[rs1+0] */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, v6 },
|
|
|
|
|
{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, v6 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, v6notv9 },
|
|
|
|
|
{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+0] */
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* std d,[rs1+0] */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, v6 },
|
|
|
|
|
{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, v6 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, 0, v9 },
|
|
|
|
|
{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, v9 }, /* stxa d,[rs1+%g0] */
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, v9 }, /* stx d,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, v9 }, /* stq [rs1+%g0] */
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, v9 },
|
|
|
|
|
{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, v9 }, /* stq [rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, v9 }, /* stqa [rs1+%g0] */
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, v9 },
|
|
|
|
|
{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, v9 }, /* stqa [rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, v7 }, /* swap [rs1+%g0],d */
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, v7 },
|
|
|
|
|
{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, v7 }, /* swap [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, v7 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, v7 }, /* swapa [rs1+%g0],d */
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, v9 },
|
|
|
|
|
{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, v9 }, /* swap [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, v6 }, /* restore %g0,%g0,%g0 */
|
|
|
|
|
{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, v6 }, /* restore %g0,0,%g0 */
|
|
|
|
|
|
|
|
|
|
{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+rs2 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1,%g0 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+X */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X */
|
|
|
|
|
{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+0 */
|
|
|
|
|
|
|
|
|
|
{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, v6 }, /* Sun assembler compatibility */
|
|
|
|
|
{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %i7+8,%g0 */
|
|
|
|
|
{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %o7+8,%g0 */
|
|
|
|
|
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,d */
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, v9 },
|
|
|
|
|
{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, 0, v9 },
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, v9 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, v9 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, v9 }, /* flush rs1+0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "[i]", 0, 0, v9 }, /* flush %g0+i */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, v9 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, v8 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, v8 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, v8 }, /* flush rs1+0 */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, v8 }, /* flush %g0+i */
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, v8 },
|
|
|
|
|
{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, v8 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* IFLUSH was renamed to FLUSH in v8. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, v6 }, /* flush rs1+%g0 */
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, v6 }, /* flush rs1+0 */
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, v9 },
|
|
|
|
|
{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, v9 }, /* return rs1+%g0 */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, v9 }, /* return rs1+0 */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, v9 }, /* return %g0+i */
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, v9 },
|
|
|
|
|
{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, v9 },
|
|
|
|
|
{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, v9 },
|
|
|
|
|
{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, v9 },
|
|
|
|
|
{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, v9 }, /* prefetcha [rs1+0],d */
|
|
|
|
|
|
|
|
|
|
{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 },
|
|
|
|
|
{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 },
|
|
|
|
|
{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 },
|
|
|
|
|
{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 },
|
|
|
|
|
{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 },
|
|
|
|
|
{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 },
|
|
|
|
|
{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, v9 },
|
|
|
|
|
{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, v9 },
|
|
|
|
|
|
|
|
|
|
{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, sparclite },
|
|
|
|
|
{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, sparclite },
|
|
|
|
|
|
|
|
|
|
{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, sparclet|sparclite },
|
|
|
|
|
{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, sparclet|sparclite },
|
|
|
|
|
|
|
|
|
|
{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, v9 },
|
|
|
|
|
{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, v9 },
|
|
|
|
|
|
|
|
|
|
{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, v6 }, /* or %g0,%g0,d */
|
|
|
|
|
{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, 0, v6 }, /* or %g0,0,d */
|
|
|
|
|
{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+%g0] */
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+%g0] */
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+0] */
|
|
|
|
|
|
|
|
|
|
{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* This is not a commutative instruction. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* This is not a commutative instruction. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, 0, v6 }, /* orcc rs1, %g0, %g0 */
|
|
|
|
|
{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
|
|
|
|
|
{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, v6 }, /* orcc rs1, 0, %g0 */
|
|
|
|
|
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, v8 }, /* wr r,r,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, v8 }, /* wr r,i,%asrX */
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_PREF_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%asrX */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, 0, v6 }, /* wr r,r,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, 0, v6 }, /* wr r,i,%y */
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_PREF_ALIAS, 0, v6 }, /* wr %g0,i,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,0,%y */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_PREF_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, 0, v6notv9 }, /* wr r,r,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, 0, v6notv9 }, /* wr r,i,%psr */
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */
|
|
|
|
|
{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, 0, v6notv9 }, /* wr r,r,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, 0, v6notv9 }, /* wr r,i,%wim */
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */
|
|
|
|
|
{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, 0, v6notv9 }, /* wr r,r,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, 0, v6notv9 }, /* wr r,i,%tbr */
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */
|
|
|
|
|
{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_PREF_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, v9 }, /* wr r,r,%ccr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, v9 }, /* wr r,i,%ccr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, v9 }, /* wr r,r,%asi */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, v9 }, /* wr r,i,%asi */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, v9 }, /* wr r,r,%fprs */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, v9 }, /* wr r,i,%fprs */
|
|
|
|
|
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pcr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pcr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pic */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pic */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%dcr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%dcr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%gsr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%gsr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%set_softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%set_softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%clear_softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%clear_softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%softint */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%tick_cmpr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%tick_cmpr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */
|
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */
|
2012-04-27 22:43:35 +02:00
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(26), F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0), "1,2,_", 0, HWCAP_CBCOND, v9b }, /* wr r,r,%cfr */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(26), F3(~2, ~0x30, ~1)|RD(~26), "1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */
|
2012-04-27 20:04:00 +02:00
|
|
|
|
{ "wr", F3(2, 0x30, 0)|RD(27), F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0), "1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */
|
|
|
|
|
{ "wr", F3(2, 0x30, 1)|RD(27), F3(~2, ~0x30, ~1)|RD(~27), "1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */
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{ "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */
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2012-04-27 20:04:00 +02:00
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{ "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, v9b }, /* wr %g0,i,%pause */
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, v8 }, /* rd %asrX,r */
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{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, v6 }, /* rd %y,r */
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{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, v6notv9 }, /* rd %psr,r */
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{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, 0, v6notv9 }, /* rd %wim,r */
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{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, 0, v6notv9 }, /* rd %tbr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, v9 }, /* rd %ccr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, v9 }, /* rd %asi,r */
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{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, v9 }, /* rd %tick,r */
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{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, v9 }, /* rd %pc,r */
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{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, v9 }, /* rd %fprs,r */
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{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %pcr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %pic,r */
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{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %dcr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %gsr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %softint,r */
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{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */
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Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
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{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick,r */
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{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, HWCAP_VIS2, v9b }, /* rd %sys_tick_cmpr,r */
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{ "rd", F3(2, 0x28, 0)|RS1(26), F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0), "/,d", 0, HWCAP_CBCOND, v9b }, /* rd %cfr,r */
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
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{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, 0, v9 }, /* rdpr %priv,r */
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{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, 0, v9 }, /* wrpr r1,r2,%priv */
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{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, 0, v9 }, /* wrpr r1,%priv */
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{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, 0, v9 }, /* wrpr r1,i,%priv */
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{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, 0, v9 }, /* wrpr i,r1,%priv */
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{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, 0, v9 }, /* wrpr i,%priv */
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{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, 0, v9 }, /* rdhpr %hpriv,r */
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{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */
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{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, 0, v9 }, /* wrhpr r1,%hpriv */
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{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, 0, v9 }, /* wrhpr r1,i,%hpriv */
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{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, 0, v9 }, /* wrhpr i,r1,%hpriv */
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{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, 0, v9 }, /* wrhpr i,%hpriv */
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2006-02-25 02:33:24 +01:00
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, 0, v8 }, /* rd %asr1,r */
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{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, 0, v6 }, /* rd %y,r */
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{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, 0, v6notv9 }, /* rd %psr,r */
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{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, 0, v6notv9 }, /* rd %wim,r */
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{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, 0, v6notv9 }, /* rd %tbr,r */
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{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
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{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
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{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
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{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
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{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
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{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
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{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
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{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
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{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
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{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
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{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, 0, v6 }, /* or %g0,rs2,d */
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{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, 0, v6 }, /* or %g0,i,d */
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{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, v6 }, /* or rs1,%g0,d */
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{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, v6 }, /* or rs1,0,d */
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{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, v6 },
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{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, v6 },
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{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* or rd,rs2,rd */
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{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, 0, v6 }, /* or rd,i,rd */
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1999-05-03 09:29:11 +02:00
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/* This is not a commutative instruction. */
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, v6 },
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1999-05-03 09:29:11 +02:00
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/* This is not a commutative instruction. */
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, v6 },
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{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* andn rd,rs2,rd */
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{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, 0, v6 }, /* andn rd,i,rd */
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{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, 0, v6 }, /* subcc rs1,rs2,%g0 */
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{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, 0, v6 }, /* subcc rs1,i,%g0 */
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{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, v6 },
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{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, v6 },
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{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 },
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{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, v6notv9 },
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{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, v9 },
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{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 },
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{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, v6notv9 },
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{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, v9 },
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{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, v6 },
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{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, v6 },
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{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, v6 },
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{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, v6 },
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{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* sub rd,1,rd */
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{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, 0, v8 }, /* sub rd,imm,rd */
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{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* subcc rd,1,rd */
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{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, 0, v8 }, /* subcc rd,imm,rd */
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{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* add rd,1,rd */
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{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, 0, v8 }, /* add rd,imm,rd */
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{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 }, /* addcc rd,1,rd */
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{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, 0, v8 }, /* addcc rd,imm,rd */
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{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, v6 }, /* andcc rs1,rs2,%g0 */
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{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, v6 }, /* andcc rs1,i,%g0 */
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{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, v6 }, /* sub %g0,rs2,rd */
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{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, v6 }, /* sub %g0,rd,rd */
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{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, v6 },
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{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, v6 },
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{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
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{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, v6 },
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{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, v6 },
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{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 },
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{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, v6notv9 },
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{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, v6notv9 },
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{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, v9 },
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{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, v9 },
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{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, v6notv9 },
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{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, v6notv9 },
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{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, v6notv9 },
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{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, v9 },
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{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, v9 },
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{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 },
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{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32, v8 },
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{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32, v8 },
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{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 },
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{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32, v8 },
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{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32, v8 },
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{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 },
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{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32, v8 },
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{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32, v8 },
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{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, v8 },
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{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32, v8 },
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{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32, v8 },
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{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 },
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{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32, v8 },
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{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32, v8 },
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{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 },
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{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32, v8 },
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{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32, v8 },
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{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 },
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{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32, v8 },
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{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32, v8 },
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{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, v8 },
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{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32, v8 },
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{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32, v8 },
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{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, v9 },
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{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, v9 },
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{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, v9 },
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{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, v9 },
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{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, v6 },
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{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, v6 },
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{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%o7 */
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{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, 0, v6 },
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{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%o7 */
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{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, v6 },
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{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%o7 */
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{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, 0, v6 },
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{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%o7 */
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{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%o7 */
|
|
|
|
|
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "chkpt", F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, HWCAP_TRANS, v9b },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Conditional instructions.
|
|
|
|
|
|
|
|
|
|
Because this part of the table was such a mess earlier, I have
|
|
|
|
|
macrofied it so that all the branches and traps are generated from
|
|
|
|
|
a single-line description of each condition value. John Gilmore. */
|
|
|
|
|
|
|
|
|
|
/* Define branches -- one annulled, one without, etc. */
|
|
|
|
|
#define br(opcode, mask, lose, flags) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, v6 }, \
|
|
|
|
|
{ opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, v6 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define brx(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
|
|
|
|
|
#define tr(opcode, mask, lose, flags) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, v9 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, v9 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, v9 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, v9 }, /* rs1 + %g0 */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, v9 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, v9 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, v9 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, v9 }, /* rs1 + %g0 */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, v6 }, /* %g0 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, v6 }, /* rs1 + imm */ \
|
|
|
|
|
{ opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, v6 }, /* imm + rs1 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose), "1+2", (flags), 0, v6 }, /* rs1 + rs2 */ \
|
|
|
|
|
{ opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, v6 } /* rs1 + %g0 */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* v9: We must put `brx' before `br', to ensure that we never match something
|
|
|
|
|
v9: against an expression unless it is an expression. Otherwise, we end
|
|
|
|
|
v9: up with undefined symbol tables entries, because they get added, but
|
|
|
|
|
v9: are not deleted if the pattern fails to match. */
|
|
|
|
|
|
|
|
|
|
/* Define both branches and traps based on condition mask */
|
|
|
|
|
#define cond(bop, top, mask, flags) \
|
|
|
|
|
brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
|
|
|
|
|
br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
|
|
|
|
|
tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
|
|
|
|
|
|
|
|
|
|
/* Define all the conditions, all the branches, all the traps. */
|
|
|
|
|
|
|
|
|
|
/* Standard branch, trap mnemonics */
|
|
|
|
|
cond ("b", "ta", CONDA, F_UNBR),
|
|
|
|
|
/* Alternative form (just for assembly, not for disassembly) */
|
|
|
|
|
cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
|
|
|
|
|
|
|
|
|
|
cond ("bcc", "tcc", CONDCC, F_CONDBR),
|
|
|
|
|
cond ("bcs", "tcs", CONDCS, F_CONDBR),
|
|
|
|
|
cond ("be", "te", CONDE, F_CONDBR),
|
|
|
|
|
cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("bg", "tg", CONDG, F_CONDBR),
|
|
|
|
|
cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("bge", "tge", CONDGE, F_CONDBR),
|
|
|
|
|
cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
|
|
|
|
|
cond ("bgu", "tgu", CONDGU, F_CONDBR),
|
|
|
|
|
cond ("bl", "tl", CONDL, F_CONDBR),
|
|
|
|
|
cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
|
|
|
|
|
cond ("ble", "tle", CONDLE, F_CONDBR),
|
|
|
|
|
cond ("bleu", "tleu", CONDLEU, F_CONDBR),
|
|
|
|
|
cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
|
|
|
|
|
cond ("bn", "tn", CONDN, F_CONDBR),
|
|
|
|
|
cond ("bne", "tne", CONDNE, F_CONDBR),
|
|
|
|
|
cond ("bneg", "tneg", CONDNEG, F_CONDBR),
|
|
|
|
|
cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
|
|
|
|
|
cond ("bpos", "tpos", CONDPOS, F_CONDBR),
|
|
|
|
|
cond ("bvc", "tvc", CONDVC, F_CONDBR),
|
|
|
|
|
cond ("bvs", "tvs", CONDVS, F_CONDBR),
|
|
|
|
|
cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
|
|
|
|
|
|
|
|
|
|
#undef cond
|
|
|
|
|
#undef br
|
|
|
|
|
#undef brr /* v9 */
|
|
|
|
|
#undef tr
|
|
|
|
|
|
|
|
|
|
#define brr(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, v9 }, \
|
|
|
|
|
{ opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define condr(bop, mask, flags) /* v9 */ \
|
|
|
|
|
brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ condr("brnz", 0x5, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brz", 0x1, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brgez", 0x7, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brlz", 0x3, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brlez", 0x2, F_CONDBR),
|
|
|
|
|
/* v9 */ condr("brgz", 0x6, F_CONDBR),
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
#define cbcond(cop, cmask, flgs) \
|
2012-04-27 20:03:13 +02:00
|
|
|
|
{ "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
"1,2,=", flgs, HWCAP_CBCOND, v9}, \
|
2012-04-27 20:03:13 +02:00
|
|
|
|
{ "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
"1,X,=", flgs, HWCAP_CBCOND, v9}, \
|
2012-04-27 20:03:13 +02:00
|
|
|
|
{ "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
"1,2,=", flgs, HWCAP_CBCOND, v9}, \
|
2012-04-27 20:03:13 +02:00
|
|
|
|
{ "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
"1,X,=", flgs, HWCAP_CBCOND, v9},
|
|
|
|
|
|
|
|
|
|
cbcond("be", 0x09, F_CONDBR)
|
|
|
|
|
cbcond("bz", 0x09, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("ble", 0x0a, F_CONDBR)
|
|
|
|
|
cbcond("bl", 0x0b, F_CONDBR)
|
|
|
|
|
cbcond("bleu", 0x0c, F_CONDBR)
|
|
|
|
|
cbcond("bcs", 0x0d, F_CONDBR)
|
|
|
|
|
cbcond("blu", 0x0d, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bneg", 0x0e, F_CONDBR)
|
|
|
|
|
cbcond("bvs", 0x0f, F_CONDBR)
|
|
|
|
|
cbcond("bne", 0x19, F_CONDBR)
|
|
|
|
|
cbcond("bnz", 0x19, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bg", 0x1a, F_CONDBR)
|
|
|
|
|
cbcond("bge", 0x1b, F_CONDBR)
|
|
|
|
|
cbcond("bgu", 0x1c, F_CONDBR)
|
|
|
|
|
cbcond("bcc", 0x1d, F_CONDBR)
|
|
|
|
|
cbcond("bgeu", 0x1d, F_CONDBR|F_ALIAS)
|
|
|
|
|
cbcond("bpos", 0x1e, F_CONDBR)
|
|
|
|
|
cbcond("bvc", 0x1f, F_CONDBR)
|
2012-04-27 20:03:13 +02:00
|
|
|
|
|
|
|
|
|
#undef cbcond
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#undef condr /* v9 */
|
|
|
|
|
#undef brr /* v9 */
|
|
|
|
|
|
|
|
|
|
#define movr(opcode, mask, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define fmovrs(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
#define fmovrd(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
#define fmovrq(mop, mask, flags) /* v9 */ \
|
|
|
|
|
fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ movr("movrne", 0x5, 0),
|
|
|
|
|
/* v9 */ movr("movre", 0x1, 0),
|
|
|
|
|
/* v9 */ movr("movrgez", 0x7, 0),
|
|
|
|
|
/* v9 */ movr("movrlz", 0x3, 0),
|
|
|
|
|
/* v9 */ movr("movrlez", 0x2, 0),
|
|
|
|
|
/* v9 */ movr("movrgz", 0x6, 0),
|
|
|
|
|
/* v9 */ movr("movrnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ movr("movrz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrs("fmovrsne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrse", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrslz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrslez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrd("fmovrdne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrde", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovrq("fmovrqne", 0x5, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqe", 0x1, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef movr /* v9 */
|
|
|
|
|
#undef fmovr /* v9 */
|
|
|
|
|
#undef fmrr /* v9 */
|
|
|
|
|
|
|
|
|
|
#define movicc(opcode, cond, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define movfcc(opcode, fcond, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#define movcc(opcode, cond, fcond, flags) /* v9 */ \
|
|
|
|
|
movfcc (opcode, fcond, flags), /* v9 */ \
|
|
|
|
|
movicc (opcode, cond, flags) /* v9 */
|
|
|
|
|
|
|
|
|
|
/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
|
|
|
|
|
/* v9 */ movicc ("movcc", CONDCC, 0),
|
|
|
|
|
/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
|
|
|
|
|
/* v9 */ movicc ("movcs", CONDCS, 0),
|
|
|
|
|
/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
|
|
|
|
|
/* v9 */ movcc ("move", CONDE, FCONDE, 0),
|
|
|
|
|
/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
|
|
|
|
|
/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
|
|
|
|
|
/* v9 */ movicc ("movgu", CONDGU, 0),
|
|
|
|
|
/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
|
|
|
|
|
/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
|
|
|
|
|
/* v9 */ movicc ("movleu", CONDLEU, 0),
|
|
|
|
|
/* v9 */ movfcc ("movlg", FCONDLG, 0),
|
|
|
|
|
/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
|
|
|
|
|
/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
|
|
|
|
|
/* v9 */ movicc ("movneg", CONDNEG, 0),
|
|
|
|
|
/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
|
|
|
|
|
/* v9 */ movfcc ("movo", FCONDO, 0),
|
|
|
|
|
/* v9 */ movicc ("movpos", CONDPOS, 0),
|
|
|
|
|
/* v9 */ movfcc ("movu", FCONDU, 0),
|
|
|
|
|
/* v9 */ movfcc ("movue", FCONDUE, 0),
|
|
|
|
|
/* v9 */ movfcc ("movug", FCONDUG, 0),
|
|
|
|
|
/* v9 */ movfcc ("movuge", FCONDUGE, 0),
|
|
|
|
|
/* v9 */ movfcc ("movul", FCONDUL, 0),
|
|
|
|
|
/* v9 */ movfcc ("movule", FCONDULE, 0),
|
|
|
|
|
/* v9 */ movicc ("movvc", CONDVC, 0),
|
|
|
|
|
/* v9 */ movicc ("movvs", CONDVS, 0),
|
|
|
|
|
/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef movicc /* v9 */
|
|
|
|
|
#undef movfcc /* v9 */
|
|
|
|
|
#undef movcc /* v9 */
|
|
|
|
|
|
|
|
|
|
#define FM_SF 1 /* v9 - values for fpsize */
|
|
|
|
|
#define FM_DF 2 /* v9 */
|
|
|
|
|
#define FM_QF 3 /* v9 */
|
|
|
|
|
|
2004-04-20 12:23:51 +02:00
|
|
|
|
#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2004-04-20 12:23:51 +02:00
|
|
|
|
#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
|
2004-04-20 12:23:51 +02:00
|
|
|
|
#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, v9 }, \
|
|
|
|
|
{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, v9 }
|
2004-04-20 12:23:51 +02:00
|
|
|
|
|
|
|
|
|
#define fmovicc(suffix, cond, flags) /* v9 */ \
|
|
|
|
|
fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
|
|
|
|
|
fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
|
|
|
|
|
fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
|
|
|
|
|
|
|
|
|
|
#define fmovfcc(suffix, fcond, flags) /* v9 */ \
|
|
|
|
|
fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
|
|
|
|
|
fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
|
|
|
|
|
fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
|
|
|
|
|
|
|
|
|
|
#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
|
|
|
|
|
fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
|
|
|
|
|
fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
|
|
|
|
|
fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
|
|
|
|
|
|
|
|
|
|
/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
|
|
|
|
|
/* v9 */ fmovicc ("cc", CONDCC, 0),
|
|
|
|
|
/* v9 */ fmovicc ("cs", CONDCS, 0),
|
|
|
|
|
/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
|
|
|
|
|
/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
|
|
|
|
|
/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovicc ("gu", CONDGU, 0),
|
|
|
|
|
/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
|
|
|
|
|
/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("leu", CONDLEU, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("lg", FCONDLG, 0),
|
|
|
|
|
/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
|
|
|
|
|
/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("neg", CONDNEG, 0),
|
|
|
|
|
/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
|
|
|
|
|
/* v9 */ fmovfcc ("o", FCONDO, 0),
|
|
|
|
|
/* v9 */ fmovicc ("pos", CONDPOS, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("u", FCONDU, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ue", FCONDUE, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ug", FCONDUG, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ul", FCONDUL, 0),
|
|
|
|
|
/* v9 */ fmovfcc ("ule", FCONDULE, 0),
|
|
|
|
|
/* v9 */ fmovicc ("vc", CONDVC, 0),
|
|
|
|
|
/* v9 */ fmovicc ("vs", CONDVS, 0),
|
|
|
|
|
/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
|
|
|
|
|
|
|
|
|
|
#undef fmoviccx /* v9 */
|
|
|
|
|
#undef fmovfccx /* v9 */
|
|
|
|
|
#undef fmovccx /* v9 */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#undef fmovicc /* v9 */
|
|
|
|
|
#undef fmovfcc /* v9 */
|
|
|
|
|
#undef fmovcc /* v9 */
|
|
|
|
|
#undef FM_DF /* v9 */
|
|
|
|
|
#undef FM_QF /* v9 */
|
|
|
|
|
#undef FM_SF /* v9 */
|
|
|
|
|
|
|
|
|
|
/* Coprocessor branches. */
|
|
|
|
|
#define CBR(opcode, mask, lose, flags, arch) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, arch }, \
|
|
|
|
|
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, arch }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Floating point branches. */
|
|
|
|
|
#define FBR(opcode, mask, lose, flags) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, v6 }, \
|
|
|
|
|
{ opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, v6 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* V9 extended floating point branches. */
|
|
|
|
|
#define FBRX(opcode, mask, lose, flags) /* v9 */ \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
|
|
|
|
|
{ opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, v9 }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* v9: We must put `FBRX' before `FBR', to ensure that we never match
|
|
|
|
|
v9: something against an expression unless it is an expression. Otherwise,
|
|
|
|
|
v9: we end up with undefined symbol tables entries, because they get added,
|
|
|
|
|
v9: but are not deleted if the pattern fails to match. */
|
|
|
|
|
|
|
|
|
|
#define CONDFC(fop, cop, mask, flags) \
|
|
|
|
|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
|
|
|
|
|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
|
|
|
|
|
CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
|
|
|
|
|
|
|
|
|
|
#define CONDFCL(fop, cop, mask, flags) \
|
|
|
|
|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
|
|
|
|
|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
|
|
|
|
|
CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
|
|
|
|
|
|
|
|
|
|
#define CONDF(fop, mask, flags) \
|
|
|
|
|
FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
|
|
|
|
|
FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
|
|
|
|
|
|
2002-10-23 17:45:49 +02:00
|
|
|
|
CONDFC ("fb", "cb", 0x8, F_UNBR),
|
|
|
|
|
CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
|
|
|
|
|
CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
|
|
|
|
|
CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
|
|
|
|
|
CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
|
|
|
|
|
CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
|
|
|
|
|
CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
|
|
|
|
|
CONDFC ("fble", "cb01", 0xd, F_CONDBR),
|
|
|
|
|
CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
|
|
|
|
|
CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
|
|
|
|
|
CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
|
|
|
|
|
CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
|
|
|
|
|
CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
|
|
|
|
|
CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
|
|
|
|
|
CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
|
|
|
|
|
CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
|
|
|
|
|
CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
|
|
|
|
|
CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
|
|
|
|
|
CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
#undef CONDFC
|
|
|
|
|
#undef CONDFCL
|
|
|
|
|
#undef CONDF
|
|
|
|
|
#undef CBR
|
|
|
|
|
#undef FBR
|
|
|
|
|
#undef FBRX /* v9 */
|
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%g0 */
|
|
|
|
|
{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%g0 */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "nop", F2(0, 4), 0xfeffffff, "", 0, 0, v6 }, /* sethi 0, %g0 */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v6 },
|
|
|
|
|
{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
|
|
|
|
|
{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, v9 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, v6notv9 },
|
|
|
|
|
{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, v9 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* This *is* a commutative instruction. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, v6 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* This *is* a commutative instruction. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, v6 },
|
|
|
|
|
{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, v6 },
|
|
|
|
|
|
|
|
|
|
{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, v6 }, /* xnor rs1,%0,rd */
|
|
|
|
|
{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, v6 }, /* xnor rd,%0,rd */
|
|
|
|
|
|
|
|
|
|
{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, 0, v6 }, /* xor rd,rs2,rd */
|
|
|
|
|
{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, 0, v6 }, /* xor rd,i,rd */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* FPop1 and FPop2 are not instructions. Don't accept them. */
|
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
|
|
|
|
|
{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
|
|
|
|
|
{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
|
|
|
|
|
|
|
|
|
|
{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, v9 },
|
|
|
|
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{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, v9 },
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{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
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|
{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
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|
{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
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{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
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{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, v9 },
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{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, v9 },
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{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, v8 },
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{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
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{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, v8 },
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{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
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{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
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{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
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{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, v6 },
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{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, v8 },
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{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
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{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, v6 },
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{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, v6 },
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{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, v8 },
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{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
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{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, v6 },
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{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, v8 },
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{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, v8 },
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{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, v8 },
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{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, v7 },
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{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, v8 },
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{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v8 },
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{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, v7 },
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{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
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{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
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{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
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{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
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{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
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{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
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{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
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{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
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{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
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|
{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
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|
{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
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{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
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{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, v6 },
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|
{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, v8 },
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|
{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
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|
{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, v6 },
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|
{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, v6 },
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|
{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, v8 },
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|
{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
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|
{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, v6 },
|
1999-05-03 09:29:11 +02:00
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#define CMPFCC(x) (((x)&0x3)<<25)
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|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
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|
{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, 0, v6 },
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|
|
{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, 0, v6 },
|
|
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|
|
{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, 0, v9 },
|
|
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|
|
{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, 0, v8 },
|
|
|
|
|
{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, 0, v8 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, v8 },
|
|
|
|
|
{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, v8 },
|
|
|
|
|
{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
|
|
|
|
|
{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, 0, v6 },
|
|
|
|
|
{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, 0, v6 },
|
|
|
|
|
{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, 0, v9 },
|
|
|
|
|
{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, 0, v9 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* These Extended FPop (FIFO) instructions are new in the Fujitsu
|
|
|
|
|
MB86934, replacing the CPop instructions from v6 and later
|
|
|
|
|
processors. */
|
|
|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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|
#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, sparclite }
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#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, sparclite }
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#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, sparclite }
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1999-05-03 09:29:11 +02:00
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EFPOP1_2 ("efitod", 0x0c8, "f,H"),
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EFPOP1_2 ("efitos", 0x0c4, "f,g"),
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EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
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EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
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EFPOP1_2 ("efstod", 0x0c9, "f,H"),
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EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
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EFPOP1_2 ("efmovs", 0x001, "f,g"),
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EFPOP1_2 ("efnegs", 0x005, "f,g"),
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EFPOP1_2 ("efabss", 0x009, "f,g"),
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EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
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EFPOP1_2 ("efsqrts", 0x029, "f,g"),
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EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
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EFPOP1_3 ("efadds", 0x041, "e,f,g"),
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EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
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EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
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EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
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EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
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EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
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EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
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EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
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EFPOP2_2 ("efcmpd", 0x052, "v,B"),
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EFPOP2_2 ("efcmped", 0x056, "v,B"),
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EFPOP2_2 ("efcmps", 0x051, "e,f"),
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EFPOP2_2 ("efcmpes", 0x055, "e,f"),
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#undef EFPOP1_2
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#undef EFPOP1_3
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#undef EFPOP2_2
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/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
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present. Otherwise, the F_ALIAS flag is ignored. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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|
{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
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{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
|
1999-05-03 09:29:11 +02:00
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|
/* sparclet specific insns */
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|
2013-08-05 18:11:07 +02:00
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COMMUTEOP ("umac", 0x3e, letandleon),
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COMMUTEOP ("smac", 0x3f, letandleon),
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|
1999-05-03 09:29:11 +02:00
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COMMUTEOP ("umacd", 0x2e, sparclet),
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COMMUTEOP ("smacd", 0x2f, sparclet),
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COMMUTEOP ("umuld", 0x09, sparclet),
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COMMUTEOP ("smuld", 0x0d, sparclet),
|
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|
|
|
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, sparclet },
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{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, sparclet },
|
1999-05-03 09:29:11 +02:00
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|
/* The manual isn't completely accurate on these insns. The `rs2' field is
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|
treated as being 6 bits to account for 6 bit immediates to cpush. It is
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assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
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#define BIT5 (1<<5)
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, sparclet },
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{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, sparclet },
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{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, sparclet },
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{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, sparclet },
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{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, sparclet },
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{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, sparclet },
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{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, sparclet },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#undef BIT5
|
|
|
|
|
|
|
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|
|
/* sparclet coprocessor branch insns */
|
|
|
|
|
#define SLCBCC2(opcode, mask, lose) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, sparclet }, \
|
|
|
|
|
{ opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, sparclet }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
#define SLCBCC(opcode, mask) \
|
|
|
|
|
SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
|
|
|
|
|
|
|
|
|
|
/* cbn,cba can't be defined here because they're defined elsewhere and GAS
|
|
|
|
|
requires all mnemonics of the same name to be consecutive. */
|
|
|
|
|
/*SLCBCC("cbn", 0), - already defined */
|
|
|
|
|
SLCBCC("cbe", 1),
|
|
|
|
|
SLCBCC("cbf", 2),
|
|
|
|
|
SLCBCC("cbef", 3),
|
|
|
|
|
SLCBCC("cbr", 4),
|
|
|
|
|
SLCBCC("cber", 5),
|
|
|
|
|
SLCBCC("cbfr", 6),
|
|
|
|
|
SLCBCC("cbefr", 7),
|
|
|
|
|
/*SLCBCC("cba", 8), - already defined */
|
|
|
|
|
SLCBCC("cbne", 9),
|
|
|
|
|
SLCBCC("cbnf", 10),
|
|
|
|
|
SLCBCC("cbnef", 11),
|
|
|
|
|
SLCBCC("cbnr", 12),
|
|
|
|
|
SLCBCC("cbner", 13),
|
|
|
|
|
SLCBCC("cbnfr", 14),
|
|
|
|
|
SLCBCC("cbnefr", 15),
|
|
|
|
|
|
|
|
|
|
#undef SLCBCC2
|
|
|
|
|
#undef SLCBCC
|
|
|
|
|
|
2013-08-05 18:11:07 +02:00
|
|
|
|
{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9andleon },
|
|
|
|
|
{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9andleon },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 },
|
|
|
|
|
{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* v9 synthetic insns */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, v9 }, /* bn,a,pt %xcc,label */
|
|
|
|
|
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* sra rs1,%g0,rd */
|
|
|
|
|
{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */
|
|
|
|
|
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */
|
|
|
|
|
{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */
|
2013-08-05 18:11:07 +02:00
|
|
|
|
{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P,rs2,rd */
|
|
|
|
|
{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P_L,rs2,rd */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
|
|
|
|
|
{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Ultrasparc extensions */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, v9a },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
|
|
|
|
|
{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, v9a },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
/* Note that the mixing of 32/64 bit regs is intentional. */
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
|
|
|
|
|
{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, v9a },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a },
|
|
|
|
|
{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, v9a },
|
|
|
|
|
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
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{ "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a },
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{ "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
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{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, v9a },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, v9a },
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{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, v9a },
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{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, v9a },
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1999-05-03 09:29:11 +02:00
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2000-10-20 12:38:47 +02:00
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/* Cheetah instructions */
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Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
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{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", HWCAP_VIS2, 0, v9b },
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{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", HWCAP_VIS2, 0, v9b },
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{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, v9b },
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{ "commit", F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, HWCAP_TRANS, v9b },
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{ "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
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{ "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
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{ "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, v9b },
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{ "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
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{ "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
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{ "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
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{ "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
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{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, v9b },
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{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b },
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{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b },
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{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, v9b },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, v9b },
|
Increase the accuracy of sparc instruction aliases.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
2013-04-07 00:22:03 +02:00
|
|
|
|
{ "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, v9b },
|
|
|
|
|
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, v9b },
|
2012-04-27 20:02:35 +02:00
|
|
|
|
{"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{ "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },
|
|
|
|
|
{ "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b },
|
|
|
|
|
{ "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b },
|
|
|
|
|
{"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
|
|
|
|
{ "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
|
|
|
|
{"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
|
|
|
|
{ "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b },
|
|
|
|
|
{ "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b },
|
|
|
|
|
{ "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b },
|
|
|
|
|
{ "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b },
|
|
|
|
|
{ "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b },
|
|
|
|
|
{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
|
|
|
|
|
{ "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
|
|
|
|
|
{ "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
|
2012-08-22 01:00:36 +02:00
|
|
|
|
{"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
|
|
|
|
|
{"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
|
|
|
|
|
{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
|
|
|
|
{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
|
|
|
|
|
{"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, v9b },
|
|
|
|
|
{ "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, v9b },
|
2011-08-05 18:52:50 +02:00
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
/* More v9 specific insns, these need to come last so they do not clash
|
|
|
|
|
with v9a instructions such as "edge8" which looks like impdep1. */
|
|
|
|
|
|
|
|
|
|
#define IMPDEP(name, code) \
|
Move sparc opcode hwcaps out of sparc_opcode flags field.
include/opcode/
* sparc.h (struct sparc_opcode): New field 'hwcaps'.
F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
(HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
HWCAP_CBCOND, HWCAP_CRC32): New defines.
opcodes/
* sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
gas/
* config/tc-sparc.c (sparc_arch_table): Rework to use HWCAP_*
masks.
(sparc_md_end): No longer need to translate hwcap_seen values into
ELF hwcap bits, they now match exactly.
(get_hwcap_name): Use HWCAP_* and handle new values.
(sparc_ip): Fetch hwcaps from insn->hwcaps instead of insn->flags.
2012-04-27 20:01:35 +02:00
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, v9notv9a }, \
|
|
|
|
|
{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, v9notv9a }
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
|
|
|
|
IMPDEP ("impdep1", 0x36),
|
|
|
|
|
IMPDEP ("impdep2", 0x37),
|
|
|
|
|
|
|
|
|
|
#undef IMPDEP
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
|
|
|
|
|
|
|
|
|
|
/* Utilities for argument parsing. */
|
|
|
|
|
|
|
|
|
|
typedef struct
|
|
|
|
|
{
|
|
|
|
|
int value;
|
|
|
|
|
const char *name;
|
|
|
|
|
} arg;
|
|
|
|
|
|
|
|
|
|
/* Look up NAME in TABLE. */
|
|
|
|
|
|
|
|
|
|
static int
|
2005-07-01 13:16:33 +02:00
|
|
|
|
lookup_name (const arg *table, const char *name)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
const arg *p;
|
|
|
|
|
|
|
|
|
|
for (p = table; p->name; ++p)
|
|
|
|
|
if (strcmp (name, p->name) == 0)
|
|
|
|
|
return p->value;
|
|
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Look up VALUE in TABLE. */
|
|
|
|
|
|
|
|
|
|
static const char *
|
2005-07-01 13:16:33 +02:00
|
|
|
|
lookup_value (const arg *table, int value)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
const arg *p;
|
|
|
|
|
|
|
|
|
|
for (p = table; p->name; ++p)
|
|
|
|
|
if (value == p->value)
|
|
|
|
|
return p->name;
|
|
|
|
|
|
2005-07-01 13:16:33 +02:00
|
|
|
|
return NULL;
|
1999-05-03 09:29:11 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle ASI's. */
|
|
|
|
|
|
|
|
|
|
static arg asi_table[] =
|
|
|
|
|
{
|
|
|
|
|
/* These are in the v9 architecture manual. */
|
|
|
|
|
/* The shorter versions appear first, they're here because Sun's as has them.
|
|
|
|
|
Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
|
|
|
|
|
UltraSPARC architecture manual). */
|
|
|
|
|
{ 0x04, "#ASI_N" },
|
|
|
|
|
{ 0x0c, "#ASI_N_L" },
|
|
|
|
|
{ 0x10, "#ASI_AIUP" },
|
|
|
|
|
{ 0x11, "#ASI_AIUS" },
|
|
|
|
|
{ 0x18, "#ASI_AIUP_L" },
|
|
|
|
|
{ 0x19, "#ASI_AIUS_L" },
|
|
|
|
|
{ 0x80, "#ASI_P" },
|
|
|
|
|
{ 0x81, "#ASI_S" },
|
|
|
|
|
{ 0x82, "#ASI_PNF" },
|
|
|
|
|
{ 0x83, "#ASI_SNF" },
|
|
|
|
|
{ 0x88, "#ASI_P_L" },
|
|
|
|
|
{ 0x89, "#ASI_S_L" },
|
|
|
|
|
{ 0x8a, "#ASI_PNF_L" },
|
|
|
|
|
{ 0x8b, "#ASI_SNF_L" },
|
|
|
|
|
{ 0x04, "#ASI_NUCLEUS" },
|
|
|
|
|
{ 0x0c, "#ASI_NUCLEUS_LITTLE" },
|
|
|
|
|
{ 0x10, "#ASI_AS_IF_USER_PRIMARY" },
|
|
|
|
|
{ 0x11, "#ASI_AS_IF_USER_SECONDARY" },
|
|
|
|
|
{ 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
|
|
|
|
|
{ 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
|
|
|
|
|
{ 0x80, "#ASI_PRIMARY" },
|
|
|
|
|
{ 0x81, "#ASI_SECONDARY" },
|
|
|
|
|
{ 0x82, "#ASI_PRIMARY_NOFAULT" },
|
|
|
|
|
{ 0x83, "#ASI_SECONDARY_NOFAULT" },
|
|
|
|
|
{ 0x88, "#ASI_PRIMARY_LITTLE" },
|
|
|
|
|
{ 0x89, "#ASI_SECONDARY_LITTLE" },
|
|
|
|
|
{ 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
|
|
|
|
|
{ 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
|
2008-04-23 09:49:33 +02:00
|
|
|
|
/* These are UltraSPARC and Niagara extensions. */
|
|
|
|
|
{ 0x14, "#ASI_PHYS_USE_EC" },
|
|
|
|
|
{ 0x15, "#ASI_PHYS_BYPASS_EC_E" },
|
|
|
|
|
{ 0x16, "#ASI_BLK_AIUP_4V" },
|
|
|
|
|
{ 0x17, "#ASI_BLK_AIUS_4V" },
|
|
|
|
|
{ 0x1c, "#ASI_PHYS_USE_EC_L" },
|
|
|
|
|
{ 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
|
|
|
|
|
{ 0x1e, "#ASI_BLK_AIUP_L_4V" },
|
|
|
|
|
{ 0x1f, "#ASI_BLK_AIUS_L_4V" },
|
|
|
|
|
{ 0x20, "#ASI_SCRATCHPAD" },
|
|
|
|
|
{ 0x21, "#ASI_MMU" },
|
|
|
|
|
{ 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
|
|
|
|
|
{ 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
|
|
|
|
|
{ 0x25, "#ASI_QUEUE" },
|
|
|
|
|
{ 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
|
|
|
|
|
{ 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
|
|
|
|
|
{ 0x30, "#ASI_PCACHE_DATA_STATUS" },
|
|
|
|
|
{ 0x31, "#ASI_PCACHE_DATA" },
|
|
|
|
|
{ 0x32, "#ASI_PCACHE_TAG" },
|
|
|
|
|
{ 0x33, "#ASI_PCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x34, "#ASI_QUAD_LDD_PHYS" },
|
|
|
|
|
{ 0x38, "#ASI_WCACHE_VALID_BITS" },
|
|
|
|
|
{ 0x39, "#ASI_WCACHE_DATA" },
|
|
|
|
|
{ 0x3a, "#ASI_WCACHE_TAG" },
|
|
|
|
|
{ 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
|
|
|
|
|
{ 0x40, "#ASI_SRAM_FAST_INIT" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_AVAILABLE" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_ENABLE_STAT" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_ENABLE" },
|
|
|
|
|
{ 0x41, "#ASI_XIR_STEERING" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_RW" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_W1S" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_W1C" },
|
|
|
|
|
{ 0x41, "#ASI_CORE_RUNNING_STAT" },
|
|
|
|
|
{ 0x41, "#ASI_CMT_ERROR_STEERING" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_INVALIDATE" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_UTAG" },
|
|
|
|
|
{ 0x41, "#ASI_DCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x42, "#ASI_DCACHE_INVALIDATE" },
|
|
|
|
|
{ 0x43, "#ASI_DCACHE_UTAG" },
|
|
|
|
|
{ 0x44, "#ASI_DCACHE_SNOOP_TAG" },
|
|
|
|
|
{ 0x45, "#ASI_LSU_CONTROL_REG" },
|
|
|
|
|
{ 0x45, "#ASI_DCU_CONTROL_REG" },
|
|
|
|
|
{ 0x46, "#ASI_DCACHE_DATA" },
|
|
|
|
|
{ 0x47, "#ASI_DCACHE_TAG" },
|
|
|
|
|
{ 0x48, "#ASI_INTR_DISPATCH_STAT" },
|
|
|
|
|
{ 0x49, "#ASI_INTR_RECEIVE" },
|
|
|
|
|
{ 0x4a, "#ASI_UPA_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_JBUS_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_SAFARI_CONFIG" },
|
|
|
|
|
{ 0x4a, "#ASI_SAFARI_ADDRESS" },
|
|
|
|
|
{ 0x4b, "#ASI_ESTATE_ERROR_EN" },
|
|
|
|
|
{ 0x4c, "#ASI_AFSR" },
|
|
|
|
|
{ 0x4d, "#ASI_AFAR" },
|
|
|
|
|
{ 0x4e, "#ASI_EC_TAG_DATA" },
|
|
|
|
|
{ 0x50, "#ASI_IMMU" },
|
|
|
|
|
{ 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
|
|
|
|
|
{ 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
|
|
|
|
|
{ 0x54, "#ASI_ITLB_DATA_IN" },
|
|
|
|
|
{ 0x55, "#ASI_ITLB_DATA_ACCESS" },
|
|
|
|
|
{ 0x56, "#ASI_ITLB_TAG_READ" },
|
|
|
|
|
{ 0x57, "#ASI_IMMU_DEMAP" },
|
|
|
|
|
{ 0x58, "#ASI_DMMU" },
|
|
|
|
|
{ 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
|
|
|
|
|
{ 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
|
|
|
|
|
{ 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
|
|
|
|
|
{ 0x5c, "#ASI_DTLB_DATA_IN" },
|
|
|
|
|
{ 0x5d, "#ASI_DTLB_DATA_ACCESS" },
|
|
|
|
|
{ 0x5e, "#ASI_DTLB_TAG_READ" },
|
|
|
|
|
{ 0x5f, "#ASI_DMMU_DEMAP" },
|
|
|
|
|
{ 0x60, "#ASI_IIU_INST_TRAP" },
|
|
|
|
|
{ 0x63, "#ASI_INTR_ID" },
|
|
|
|
|
{ 0x63, "#ASI_CORE_ID" },
|
|
|
|
|
{ 0x63, "#ASI_CESR_ID" },
|
|
|
|
|
{ 0x66, "#ASI_IC_INSTR" },
|
|
|
|
|
{ 0x67, "#ASI_IC_TAG" },
|
|
|
|
|
{ 0x68, "#ASI_IC_STAG" },
|
|
|
|
|
{ 0x6e, "#ASI_IC_PRE_DECODE" },
|
|
|
|
|
{ 0x6f, "#ASI_IC_NEXT_FIELD" },
|
|
|
|
|
{ 0x6f, "#ASI_BRPRED_ARRAY" },
|
|
|
|
|
{ 0x70, "#ASI_BLK_AIUP" },
|
|
|
|
|
{ 0x71, "#ASI_BLK_AIUS" },
|
|
|
|
|
{ 0x72, "#ASI_MCU_CTRL_REG" },
|
|
|
|
|
{ 0x74, "#ASI_EC_DATA" },
|
|
|
|
|
{ 0x75, "#ASI_EC_CTRL" },
|
|
|
|
|
{ 0x76, "#ASI_EC_W" },
|
|
|
|
|
{ 0x77, "#ASI_UDB_ERROR_W" },
|
|
|
|
|
{ 0x77, "#ASI_UDB_CONTROL_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_DATAN_W" },
|
|
|
|
|
{ 0x77, "#ASI_INTR_DISPATCH_W" },
|
|
|
|
|
{ 0x78, "#ASI_BLK_AIUPL" },
|
|
|
|
|
{ 0x79, "#ASI_BLK_AIUSL" },
|
|
|
|
|
{ 0x7e, "#ASI_EC_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBH_ERROR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBL_ERROR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBH_CONTROL_R" },
|
|
|
|
|
{ 0x7f, "#ASI_UDBL_CONTROL_R" },
|
|
|
|
|
{ 0x7f, "#ASI_INTR_R" },
|
|
|
|
|
{ 0x7f, "#ASI_INTR_DATAN_R" },
|
|
|
|
|
{ 0xc0, "#ASI_PST8_P" },
|
|
|
|
|
{ 0xc1, "#ASI_PST8_S" },
|
|
|
|
|
{ 0xc2, "#ASI_PST16_P" },
|
|
|
|
|
{ 0xc3, "#ASI_PST16_S" },
|
|
|
|
|
{ 0xc4, "#ASI_PST32_P" },
|
|
|
|
|
{ 0xc5, "#ASI_PST32_S" },
|
|
|
|
|
{ 0xc8, "#ASI_PST8_PL" },
|
|
|
|
|
{ 0xc9, "#ASI_PST8_SL" },
|
|
|
|
|
{ 0xca, "#ASI_PST16_PL" },
|
|
|
|
|
{ 0xcb, "#ASI_PST16_SL" },
|
|
|
|
|
{ 0xcc, "#ASI_PST32_PL" },
|
|
|
|
|
{ 0xcd, "#ASI_PST32_SL" },
|
|
|
|
|
{ 0xd0, "#ASI_FL8_P" },
|
|
|
|
|
{ 0xd1, "#ASI_FL8_S" },
|
|
|
|
|
{ 0xd2, "#ASI_FL16_P" },
|
|
|
|
|
{ 0xd3, "#ASI_FL16_S" },
|
|
|
|
|
{ 0xd8, "#ASI_FL8_PL" },
|
|
|
|
|
{ 0xd9, "#ASI_FL8_SL" },
|
|
|
|
|
{ 0xda, "#ASI_FL16_PL" },
|
|
|
|
|
{ 0xdb, "#ASI_FL16_SL" },
|
|
|
|
|
{ 0xe0, "#ASI_BLK_COMMIT_P", },
|
|
|
|
|
{ 0xe1, "#ASI_BLK_COMMIT_S", },
|
|
|
|
|
{ 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
|
|
|
|
|
{ 0xf0, "#ASI_BLK_P", },
|
|
|
|
|
{ 0xf1, "#ASI_BLK_S", },
|
|
|
|
|
{ 0xf8, "#ASI_BLK_PL", },
|
|
|
|
|
{ 0xf9, "#ASI_BLK_SL", },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for ASI NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_encode_asi (const char *name)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (asi_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for ASI value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_decode_asi (int value)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (asi_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle membar masks. */
|
|
|
|
|
|
|
|
|
|
static arg membar_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0x40, "#Sync" },
|
|
|
|
|
{ 0x20, "#MemIssue" },
|
|
|
|
|
{ 0x10, "#Lookaside" },
|
|
|
|
|
{ 0x08, "#StoreStore" },
|
|
|
|
|
{ 0x04, "#LoadStore" },
|
|
|
|
|
{ 0x02, "#StoreLoad" },
|
|
|
|
|
{ 0x01, "#LoadLoad" },
|
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for membar arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_encode_membar (const char *name)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (membar_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for membar value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_decode_membar (int value)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (membar_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle prefetch args. */
|
|
|
|
|
|
|
|
|
|
static arg prefetch_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0, "#n_reads" },
|
|
|
|
|
{ 1, "#one_read" },
|
|
|
|
|
{ 2, "#n_writes" },
|
|
|
|
|
{ 3, "#one_write" },
|
|
|
|
|
{ 4, "#page" },
|
2000-10-20 12:38:47 +02:00
|
|
|
|
{ 16, "#invalidate" },
|
2008-04-23 09:49:33 +02:00
|
|
|
|
{ 17, "#unified", },
|
|
|
|
|
{ 20, "#n_reads_strong", },
|
|
|
|
|
{ 21, "#one_read_strong", },
|
|
|
|
|
{ 22, "#n_writes_strong", },
|
|
|
|
|
{ 23, "#one_write_strong", },
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for prefetch arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_encode_prefetch (const char *name)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (prefetch_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for prefetch value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_decode_prefetch (int value)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (prefetch_table, value);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle sparclet coprocessor registers. */
|
|
|
|
|
|
|
|
|
|
static arg sparclet_cpreg_table[] =
|
|
|
|
|
{
|
|
|
|
|
{ 0, "%ccsr" },
|
|
|
|
|
{ 1, "%ccfr" },
|
|
|
|
|
{ 2, "%cccrcr" },
|
|
|
|
|
{ 3, "%ccpr" },
|
|
|
|
|
{ 4, "%ccsr2" },
|
|
|
|
|
{ 5, "%cccrr" },
|
|
|
|
|
{ 6, "%ccrstr" },
|
|
|
|
|
{ 0, 0 }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Return the value for sparclet cpreg arg NAME, or -1 if not found. */
|
|
|
|
|
|
|
|
|
|
int
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_encode_sparclet_cpreg (const char *name)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_name (sparclet_cpreg_table, name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
|
|
|
|
|
|
|
|
|
|
const char *
|
2005-07-01 13:16:33 +02:00
|
|
|
|
sparc_decode_sparclet_cpreg (int value)
|
1999-05-03 09:29:11 +02:00
|
|
|
|
{
|
|
|
|
|
return lookup_value (sparclet_cpreg_table, value);
|
|
|
|
|
}
|