2007-06-28 16:29:56 +02:00
|
|
|
// i386 register table.
|
2009-09-02 09:25:43 +02:00
|
|
|
// Copyright 2007, 2008
|
2007-07-05 11:49:03 +02:00
|
|
|
// Free Software Foundation, Inc.
|
|
|
|
|
//
|
|
|
|
|
// This file is part of the GNU opcodes library.
|
|
|
|
|
//
|
|
|
|
|
// This library is free software; you can redistribute it and/or modify
|
|
|
|
|
// it under the terms of the GNU General Public License as published by
|
|
|
|
|
// the Free Software Foundation; either version 3, or (at your option)
|
|
|
|
|
// any later version.
|
|
|
|
|
//
|
|
|
|
|
// It is distributed in the hope that it will be useful, but WITHOUT
|
|
|
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
|
|
|
|
// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
|
|
|
|
// License for more details.
|
|
|
|
|
//
|
|
|
|
|
// You should have received a copy of the GNU General Public License
|
|
|
|
|
// along with GAS; see the file COPYING. If not, write to the Free
|
|
|
|
|
// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
|
|
|
|
|
// 02110-1301, USA.
|
2007-06-28 16:29:56 +02:00
|
|
|
|
|
|
|
|
// Make %st first as we test for it.
|
2008-02-13 11:14:40 +01:00
|
|
|
st, FloatReg|FloatAcc, 0, 0, 11, 33
|
2007-06-28 16:29:56 +02:00
|
|
|
// 8 bit regs
|
2008-02-13 11:14:40 +01:00
|
|
|
al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
axl, Reg8|Acc|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// 16 bit regs
|
2008-02-13 11:14:40 +01:00
|
|
|
ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// 32 bit regs
|
2008-02-13 11:14:40 +01:00
|
|
|
eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
|
|
|
|
|
ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
|
|
|
|
|
edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
|
|
|
|
|
ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
|
|
|
|
|
esp, Reg32, 0, 4, 4, Dw2Inval
|
|
|
|
|
ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
|
|
|
|
|
esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
|
|
|
|
|
edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
|
|
|
|
|
r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
|
|
|
|
|
rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
|
|
|
|
|
rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
|
|
|
|
|
rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
|
|
|
|
|
rsp, Reg64, 0, 4, Dw2Inval, 7
|
|
|
|
|
rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
|
|
|
|
|
rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
|
|
|
|
|
rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
|
|
|
|
|
r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
|
|
|
|
|
r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
|
|
|
|
|
r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
|
|
|
|
|
r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
|
|
|
|
|
r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
|
|
|
|
|
r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
|
|
|
|
|
r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
|
|
|
|
|
r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
|
2007-06-29 22:07:53 +02:00
|
|
|
// Segment registers.
|
2008-02-13 11:14:40 +01:00
|
|
|
es, SReg2, 0, 0, 40, 50
|
|
|
|
|
cs, SReg2, 0, 1, 41, 51
|
|
|
|
|
ss, SReg2, 0, 2, 42, 52
|
|
|
|
|
ds, SReg2, 0, 3, 43, 53
|
|
|
|
|
fs, SReg3, 0, 4, 44, 54
|
|
|
|
|
gs, SReg3, 0, 5, 45, 55
|
2008-02-13 14:41:26 +01:00
|
|
|
flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// Control registers.
|
2008-02-13 11:14:40 +01:00
|
|
|
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
cr1, Control, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
cr2, Control, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
cr3, Control, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
cr4, Control, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
cr5, Control, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
cr6, Control, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
cr7, Control, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// Debug registers.
|
2008-02-13 11:14:40 +01:00
|
|
|
db0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
db1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
db2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
db3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
db4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
db5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
db6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
db7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// Test registers.
|
2008-02-13 11:14:40 +01:00
|
|
|
tr0, Test, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
tr1, Test, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
tr2, Test, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
tr3, Test, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
tr4, Test, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
tr5, Test, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
tr6, Test, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
tr7, Test, 0, 7, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// MMX and simd registers.
|
2008-02-13 11:14:40 +01:00
|
|
|
mm0, RegMMX, 0, 0, 29, 41
|
|
|
|
|
mm1, RegMMX, 0, 1, 30, 42
|
|
|
|
|
mm2, RegMMX, 0, 2, 31, 43
|
|
|
|
|
mm3, RegMMX, 0, 3, 32, 44
|
|
|
|
|
mm4, RegMMX, 0, 4, 33, 45
|
|
|
|
|
mm5, RegMMX, 0, 5, 34, 46
|
|
|
|
|
mm6, RegMMX, 0, 6, 35, 47
|
|
|
|
|
mm7, RegMMX, 0, 7, 36, 48
|
|
|
|
|
xmm0, RegXMM, 0, 0, 21, 17
|
|
|
|
|
xmm1, RegXMM, 0, 1, 22, 18
|
|
|
|
|
xmm2, RegXMM, 0, 2, 23, 19
|
|
|
|
|
xmm3, RegXMM, 0, 3, 24, 20
|
|
|
|
|
xmm4, RegXMM, 0, 4, 25, 21
|
|
|
|
|
xmm5, RegXMM, 0, 5, 26, 22
|
|
|
|
|
xmm6, RegXMM, 0, 6, 27, 23
|
|
|
|
|
xmm7, RegXMM, 0, 7, 28, 24
|
|
|
|
|
xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
|
|
|
|
|
xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
|
|
|
|
|
xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
|
|
|
|
|
xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
|
|
|
|
|
xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
|
|
|
|
|
xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
|
|
|
|
|
xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
|
|
|
|
|
xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
|
binutils/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* dwarf.c (dwarf_regnames_i386): Add AVX registers.
(dwarf_regnames_x86_64): Likewise.
gas/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.
* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
Document -msse2avx, .avx, .aes, .clmul and .fma.
* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
(vex_prefix): Likewise.
(sse2avx): Likewise.
(CPU_FLAGS_ARCH_MATCH): Likewise.
(CPU_FLAGS_64BIT_MATCH): Likewise.
(CPU_FLAGS_32BIT_MATCH): Likewise.
(CPU_FLAGS_PERFECT_MATCH): Likewise.
(regymm): Likewise.
(vex_imm4): Likewise.
(fits_in_imm4): Likewise.
(build_vex_prefix): Likewise.
(VEX_check_operands): Likewise.
(bad_implicit_operand): Likewise.
(OPTION_MSSE2AVX): Likewise.
(T_YMMWORD): Likewise.
(_i386_insn): Add vex.
(cpu_arch): Add .avx, .aes, .clmul and .fma.
(cpu_flags_match): Changed to take a pointer to const template.
Enable encoding SSE instructions with VEX prefix for -msse2avx.
(match_mem_size): Also check ymmword.
(operand_type_match): Clear ymmword.
(md_begin): Allow '_' in mnemonic.
(type_names): Add OPERAND_TYPE_VEX_IMM4.
(process_immext): Update assert.
(md_assemble): Don't call process_immext if sse2avx and immext
are true. Call build_vex_prefix if vex is true.
(parse_insn): Updated for cpu_flags_match.
(swap_operands): Handle 5 operands.
(match_template): Handle 5 operands. Updated for cpu_flags_match.
Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
(check_byte_reg): Check regymm.
(process_operands): Duplicate the destination register for
-msse2avx if needed.
(build_modrm_byte): Updated for instructions with VEX encoding.
(output_insn): Output VEX prefix if needed.
(md_longopts): Add msse2avx.
(md_parse_option): Handle OPTION_MSSE2AVX.
(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
(intel_e09): Support YMMWORD.
(intel_e11): Likewise.
(intel_get_token): Likewise.
gas/testsuite/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
x86-64-avx-intel and x86-64-inval-avx.
* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
* gas/cfi/cfi-x86_64.s: Likewise.
* gas/i386/aes.d: New.
* gas/i386/aes.s: Likewise.
* gas/i386/aes-intel.d: Likewise.
* gas/i386/avx.d: Likewise.
* gas/i386/avx.s: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/clmul.d: Likewise.
* gas/i386/clmul-intel.d: Likewise.
* gas/i386/clmul.s: Likewise.
* gas/i386/i386.exp: Likewise.
* gas/i386/inval-avx.l: Likewise.
* gas/i386/inval-avx.s: Likewise.
* gas/i386/sse2avx.d: Likewise.
* gas/i386/sse2avx.s: Likewise.
* gas/i386/x86-64-aes.d: Likewise.
* gas/i386/x86-64-aes.s: Likewise.
* gas/i386/x86-64-aes-intel.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx.s: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
* gas/i386/x86-64-clmul.d: Likewise.
* gas/i386/x86-64-clmul-intel.d: Likewise.
* gas/i386/x86-64-clmul.s: Likewise.
* gas/i386/x86-64-inval-avx.l: Likewise.
* gas/i386/x86-64-inval-avx.s: Likewise.
* gas/i386/x86-64-sse2avx.d: Likewise.
* gas/i386/x86-64-sse2avx.s: Likewise.
* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
* gas/i386/x86-64-arch-2.s: Likewise.
* gas/i386/rexw.s: Add AVX tests.
* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.
* gas/cfi/cfi-i386.d: Updated.
* gas/cfi/cfi-x86_64.d: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-1.l: Likewise.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/rexw.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-opcode-inval.d: Likewise.
* gas/i386/x86-64-opcode-inval-intel.d: Likewise.
include/opcode/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (MAX_OPERANDS): Set to 5.
(MAX_MNEM_SIZE): Changed to 20.
opcodes/
2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_E_register): New.
(OP_E_memory): Likewise.
(OP_VEX): Likewise.
(OP_EX_Vex): Likewise.
(OP_EX_VexW): Likewise.
(OP_XMM_Vex): Likewise.
(OP_XMM_VexW): Likewise.
(OP_REG_VexI4): Likewise.
(PCLMUL_Fixup): Likewise.
(VEXI4_Fixup): Likewise.
(VZERO_Fixup): Likewise.
(VCMP_Fixup): Likewise.
(VPERMIL2_Fixup): Likewise.
(rex_original): Likewise.
(rex_ignored): Likewise.
(Mxmm): Likewise.
(XMM): Likewise.
(EXxmm): Likewise.
(EXxmmq): Likewise.
(EXymmq): Likewise.
(Vex): Likewise.
(Vex128): Likewise.
(Vex256): Likewise.
(VexI4): Likewise.
(EXdVex): Likewise.
(EXqVex): Likewise.
(EXVexW): Likewise.
(EXdVexW): Likewise.
(EXqVexW): Likewise.
(XMVex): Likewise.
(XMVexW): Likewise.
(XMVexI4): Likewise.
(PCLMUL): Likewise.
(VZERO): Likewise.
(VCMP): Likewise.
(VPERMIL2): Likewise.
(xmm_mode): Likewise.
(xmmq_mode): Likewise.
(ymmq_mode): Likewise.
(vex_mode): Likewise.
(vex128_mode): Likewise.
(vex256_mode): Likewise.
(USE_VEX_C4_TABLE): Likewise.
(USE_VEX_C5_TABLE): Likewise.
(USE_VEX_LEN_TABLE): Likewise.
(VEX_C4_TABLE): Likewise.
(VEX_C5_TABLE): Likewise.
(VEX_LEN_TABLE): Likewise.
(REG_VEX_XX): Likewise.
(MOD_VEX_XXX): Likewise.
(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
(PREFIX_0F3A44): Likewise.
(PREFIX_0F3ADF): Likewise.
(PREFIX_VEX_XXX): Likewise.
(VEX_OF): Likewise.
(VEX_OF38): Likewise.
(VEX_OF3A): Likewise.
(VEX_LEN_XXX): Likewise.
(vex): Likewise.
(need_vex): Likewise.
(need_vex_reg): Likewise.
(vex_i4_done): Likewise.
(vex_table): Likewise.
(vex_len_table): Likewise.
(OP_REG_VexI4): Likewise.
(vex_cmp_op): Likewise.
(pclmul_op): Likewise.
(vpermil2_op): Likewise.
(m_mode): Updated.
(es_reg): Likewise.
(PREFIX_0F38F0): Likewise.
(PREFIX_0F3A60): Likewise.
(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
and PREFIX_VEX_XXX entries.
(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
PREFIX_0F3ADF.
(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
Add MOD_VEX_XXX entries.
(ckprefix): Initialize rex_original and rex_ignored. Store the
REX byte in rex_original.
(get_valid_dis386): Handle the implicit prefix in VEX prefix
bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
calling get_valid_dis386. Use rex_original and rex_ignored when
printing out REX.
(putop): Handle "XY".
(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
ymmq_mode.
(OP_E_extended): Updated to use OP_E_register and
OP_E_memory.
(OP_XMM): Handle VEX.
(OP_EX): Likewise.
(XMM_Fixup): Likewise.
(CMP_Fixup): Use ARRAY_SIZE.
* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
CPU_FMA_FLAGS and CPU_AVX_FLAGS.
(operand_type_init): Add OPERAND_TYPE_REGYMM and
OPERAND_TYPE_VEX_IMM4.
(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
VexImmExt and SSE2AVX.
(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
* i386-opc.h (CpuAVX): New.
(CpuAES): Likewise.
(CpuCLMUL): Likewise.
(CpuFMA): Likewise.
(Vex): Likewise.
(Vex256): Likewise.
(VexNDS): Likewise.
(VexNDD): Likewise.
(VexW0): Likewise.
(VexW1): Likewise.
(Vex0F): Likewise.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(Vex3Sources): Likewise.
(VexImmExt): Likewise.
(SSE2AVX): Likewise.
(RegYMM): Likewise.
(Ymmword): Likewise.
(Vex_Imm4): Likewise.
(Implicit1stXmm0): Likewise.
(CpuXsave): Updated.
(CpuLM): Likewise.
(ByteOkIntel): Likewise.
(OldGcc): Likewise.
(Control): Likewise.
(Unspecified): Likewise.
(OTMax): Likewise.
(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
vex3sources, veximmext and sse2avx.
(i386_operand_type): Add regymm, ymmword and vex_imm4.
* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2008-04-03 16:03:21 +02:00
|
|
|
// AVX registers.
|
2008-08-01 16:21:30 +02:00
|
|
|
ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
|
|
|
|
|
ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
|
2007-09-26 15:40:59 +02:00
|
|
|
// No type will make these registers rejected for all purposes except
|
|
|
|
|
// for addressing. This saves creating one extra type for RIP/EIP.
|
2008-02-13 11:14:40 +01:00
|
|
|
rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
|
|
|
|
|
eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
|
2007-09-20 19:38:38 +02:00
|
|
|
// No type will make these registers rejected for all purposes except
|
|
|
|
|
// for addressing.
|
2008-02-13 11:14:40 +01:00
|
|
|
eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
|
|
|
|
|
riz, BaseIndex, 0, RegRiz, Dw2Inval, Dw2Inval
|
2007-06-28 16:29:56 +02:00
|
|
|
// fp regs.
|
2008-02-13 11:14:40 +01:00
|
|
|
st(0), FloatReg|FloatAcc, 0, 0, 11, 33
|
|
|
|
|
st(1), FloatReg, 0, 1, 12, 34
|
|
|
|
|
st(2), FloatReg, 0, 2, 13, 35
|
|
|
|
|
st(3), FloatReg, 0, 3, 14, 36
|
|
|
|
|
st(4), FloatReg, 0, 4, 15, 37
|
|
|
|
|
st(5), FloatReg, 0, 5, 16, 38
|
|
|
|
|
st(6), FloatReg, 0, 6, 17, 39
|
|
|
|
|
st(7), FloatReg, 0, 7, 18, 40
|
|
|
|
|
// Pseudo-register names only used in .cfi_* directives
|
|
|
|
|
eflags, 0, 0, 0, 9, 49
|
|
|
|
|
rflags, 0, 0, 0, Dw2Inval, 49
|
|
|
|
|
fs.base, 0, 0, 0, Dw2Inval, 58
|
|
|
|
|
gs.base, 0, 0, 0, Dw2Inval, 59
|
|
|
|
|
tr, 0, 0, 0, 48, 62
|
|
|
|
|
ldtr, 0, 0, 0, 49, 63
|
|
|
|
|
// st0...7 for backward compatibility
|
|
|
|
|
st0, 0, 0, 0, 11, 33
|
|
|
|
|
st1, 0, 0, 1, 12, 34
|
|
|
|
|
st2, 0, 0, 2, 13, 35
|
|
|
|
|
st3, 0, 0, 3, 14, 36
|
|
|
|
|
st4, 0, 0, 4, 15, 37
|
|
|
|
|
st5, 0, 0, 5, 16, 38
|
|
|
|
|
st6, 0, 0, 6, 17, 39
|
|
|
|
|
st7, 0, 0, 7, 18, 40
|
|
|
|
|
fcw, 0, 0, 0, 37, 65
|
|
|
|
|
fsw, 0, 0, 0, 38, 66
|
|
|
|
|
mxcsr, 0, 0, 0, 39, 64
|