2013-04-03 16:42:10 +02:00
|
|
|
|
2013-04-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
|
|
|
|
|
|
destination address by subtracting the operand from the current
|
|
|
|
|
|
address.
|
|
|
|
|
|
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
|
|
|
|
|
|
a positive value in the insn.
|
|
|
|
|
|
(extract_u16_loop): Do not negate the returned value.
|
|
|
|
|
|
(D16_LOOP): Add V850_INVERSE_PCREL flag.
|
|
|
|
|
|
|
|
|
|
|
|
(ceilf.sw): Remove duplicate entry.
|
|
|
|
|
|
(cvtf.hs): New entry.
|
|
|
|
|
|
(cvtf.sh): Likewise.
|
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|
|
|
|
(fmaf.s): Likewise.
|
|
|
|
|
|
(fmsf.s): Likewise.
|
|
|
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|
|
(fnmaf.s): Likewise.
|
|
|
|
|
|
(fnmsf.s): Likewise.
|
|
|
|
|
|
(maddf.s): Restrict to E3V5 architectures.
|
|
|
|
|
|
(msubf.s): Likewise.
|
|
|
|
|
|
(nmaddf.s): Likewise.
|
|
|
|
|
|
(nmsubf.s): Likewise.
|
|
|
|
|
|
|
2013-03-27 19:49:10 +01:00
|
|
|
|
2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-dis.c (get_sib): Add the sizeflag argument. Properly
|
|
|
|
|
|
check address mode.
|
|
|
|
|
|
(print_insn): Pass sizeflag to get_sib.
|
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|
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|
|
2013-03-27 12:43:37 +01:00
|
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|
|
2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
|
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|
|
|
|
|
|
|
|
|
|
PR binutils/15068
|
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|
|
|
|
* tic6x-dis.c: Add support for displaying 16-bit insns.
|
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|
|
|
|
2013-03-20 17:36:34 +01:00
|
|
|
|
2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15095
|
|
|
|
|
|
* tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
|
|
|
|
|
|
individual msb and lsb halves in src1 & src2 fields. Discard the
|
|
|
|
|
|
src1 (lsb) value and only use src2 (msb), discarding bit 0, to
|
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|
|
|
|
follow what Ti SDK does in that case as any value in the src1
|
|
|
|
|
|
field yields the same output with SDK disassembler.
|
|
|
|
|
|
|
2013-03-12 16:19:23 +01:00
|
|
|
|
2013-03-12 Michael Eager <eager@eagercon.com>
|
|
|
|
|
|
|
2013-03-20 17:36:34 +01:00
|
|
|
|
* opcodes/mips-dis.c (print_insn_args): Modify def of reg.
|
2013-03-12 16:19:23 +01:00
|
|
|
|
|
2013-03-12 03:41:26 +01:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
|
|
|
|
|
|
|
2013-03-12 03:20:08 +01:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
|
|
|
|
|
|
|
2013-03-12 02:41:41 +01:00
|
|
|
|
2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
|
|
|
|
|
|
|
|
|
|
|
|
* nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
|
|
|
|
|
|
|
2013-03-11 12:09:33 +01:00
|
|
|
|
2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_opcodes): Add entries for CRC instructions.
|
|
|
|
|
|
(thumb32_opcodes): Likewise.
|
|
|
|
|
|
(print_insn_thumb32): Handle 'S' control char.
|
|
|
|
|
|
|
2013-03-08 18:25:12 +01:00
|
|
|
|
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* lm32-desc.c: Regenerate.
|
|
|
|
|
|
|
2013-03-02 02:57:48 +01:00
|
|
|
|
2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-reg.tbl (riz): Add RegRex64.
|
|
|
|
|
|
* i386-tbl.h: Regenerated.
|
|
|
|
|
|
|
2013-02-28 20:18:40 +01:00
|
|
|
|
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
|
|
|
|
|
|
(aarch64_feature_crc): New static.
|
|
|
|
|
|
(CRC): New macro.
|
|
|
|
|
|
(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
|
|
|
|
|
|
crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
|
|
|
|
|
|
* aarch64-asm-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-dis-2.c: Ditto.
|
|
|
|
|
|
* aarch64-opc-2.c: Ditto.
|
|
|
|
|
|
|
2013-02-27 04:00:44 +01:00
|
|
|
|
2013-02-27 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc (rl78_decode_opcode): Fix typo.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-25 19:41:06 +01:00
|
|
|
|
2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc: Fix encoding of DIVWU insn.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2013-02-19 20:10:31 +01:00
|
|
|
|
2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/15159
|
|
|
|
|
|
* i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
|
|
|
|
|
|
(cpu_flags): Add CpuSMAP.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.h (CpuSMAP): New.
|
|
|
|
|
|
(i386_cpu_flags): Add cpusmap.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-opc.tbl: Add clac and stac.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-02-15 15:54:28 +01:00
|
|
|
|
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
|
|
|
|
|
|
which also makes the disassembler output be in little
|
|
|
|
|
|
endian like it should be.
|
|
|
|
|
|
|
2013-02-14 19:12:51 +01:00
|
|
|
|
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
|
|
|
|
|
|
fields to NULL.
|
|
|
|
|
|
(aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
|
|
|
|
|
|
|
2013-02-13 20:36:10 +01:00
|
|
|
|
2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
|
2013-02-13 18:09:09 +01:00
|
|
|
|
|
|
|
|
|
|
* mips-dis.c (is_compressed_mode_p): Only match symbols from the
|
|
|
|
|
|
section disassembled.
|
|
|
|
|
|
|
2013-02-11 11:15:52 +01:00
|
|
|
|
2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c: Update strht pattern.
|
|
|
|
|
|
|
gas/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
2013-02-09 11:24:20 +01:00
|
|
|
|
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
|
|
|
|
|
|
|
|
|
|
|
|
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
|
|
|
|
|
|
single-float. Disable ll, lld, sc and scd for EE. Disable the
|
|
|
|
|
|
trunc.w.s macro for EE.
|
|
|
|
|
|
|
2013-02-07 00:22:26 +01:00
|
|
|
|
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
|
|
|
|
|
|
Andrew Jenner <andrew@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
Based on patches from Altera Corporation.
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
|
|
|
|
|
|
nios2-opc.c.
|
|
|
|
|
|
* Makefile.in: Regenerated.
|
|
|
|
|
|
* configure.in: Add case for bfd_nios2_arch.
|
|
|
|
|
|
* configure: Regenerated.
|
|
|
|
|
|
* disassemble.c (ARCH_nios2): Define.
|
|
|
|
|
|
(disassembler): Add case for bfd_arch_nios2.
|
|
|
|
|
|
* nios2-dis.c: New file.
|
|
|
|
|
|
* nios2-opc.c: New file.
|
|
|
|
|
|
|
2013-02-04 07:04:33 +01:00
|
|
|
|
2013-02-04 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
* rx-decode.c: Regenerate.
|
|
|
|
|
|
|
include/opcode/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
opcodes/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
* aarch64-asm.c (convert_xtl_to_shll): New function.
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_xtl_to_shll.
* aarch64-dis.c (convert_shll_to_xtl): New function.
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
calling convert_shll_to_xtl.
* aarch64-gen.c: Update copyright year.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Re-generate.
* aarch64-opc-2.c: Re-generate.
gas/testsuite/
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/alias.s: Add new tests.
* gas/aarch64/alias.d: Update.
* gas/aarch64/no-aliases.d: Update.
2013-01-30 16:43:32 +01:00
|
|
|
|
2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
|
|
|
|
|
|
ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
|
|
|
|
|
|
* aarch64-asm.c (convert_xtl_to_shll): New function.
|
|
|
|
|
|
(convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_xtl_to_shll.
|
|
|
|
|
|
* aarch64-dis.c (convert_shll_to_xtl): New function.
|
|
|
|
|
|
(convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
|
|
|
|
|
|
calling convert_shll_to_xtl.
|
|
|
|
|
|
* aarch64-gen.c: Update copyright year.
|
|
|
|
|
|
* aarch64-asm-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-dis-2.c: Re-generate.
|
|
|
|
|
|
* aarch64-opc-2.c: Re-generate.
|
|
|
|
|
|
|
2013-01-24 12:14:05 +01:00
|
|
|
|
2013-01-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c: Add support for e3v5 architecture.
|
|
|
|
|
|
* v850-opc.c: Likewise.
|
|
|
|
|
|
|
2013-01-17 17:09:44 +01:00
|
|
|
|
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
|
|
|
|
|
|
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
|
|
|
|
|
|
* aarch64-opc.c (operand_general_constraint_met_p): For
|
2013-01-24 12:14:05 +01:00
|
|
|
|
AARCH64_MOD_LSL, move the range check on the shift amount before the
|
2013-01-17 17:09:44 +01:00
|
|
|
|
alignment check; change to call set_sft_amount_out_of_range_error
|
|
|
|
|
|
instead of set_imm_out_of_range_error.
|
|
|
|
|
|
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
|
|
|
|
|
|
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
|
|
|
|
|
|
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
|
|
|
|
|
|
SIMD_IMM_SFT.
|
|
|
|
|
|
|
2013-01-16 23:11:05 +01:00
|
|
|
|
2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
|
|
|
|
|
|
|
|
|
|
|
|
* i386-init.h: Regenerated.
|
|
|
|
|
|
* i386-tbl.h: Likewise.
|
|
|
|
|
|
|
2013-01-15 09:45:45 +01:00
|
|
|
|
2013-01-15 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
|
|
|
|
|
|
values.
|
|
|
|
|
|
* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
|
|
|
|
|
|
|
2013-01-14 12:22:06 +01:00
|
|
|
|
2013-01-14 Will Newton <will.newton@imgtec.com>
|
|
|
|
|
|
|
|
|
|
|
|
* metag-dis.c (REG_WIDTH): Increase to 64.
|
|
|
|
|
|
|
include/opcode/
* ppc.h (PPC_OPCODE_POWER8): New define.
(PPC_OPCODE_HTM): Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
(SH6): Update.
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
gas/
* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* config/tc-ppc.c (md_show_usage): Likewise.
(ppc_handle_align): Handle power8's group ending nop.
gas/testsuite/
* gas/ppc/htm.d: New test.
* gas/ppc/htm.s: Likewise.
* gas/ppc/power8.d: Likewise.
* gas/ppc/power8.s: Likewise.
* gas/ppc/ppc.exp: Run them.
2013-01-11 03:25:36 +01:00
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2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
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* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
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XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
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(SH6): Update.
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<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
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"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
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"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
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<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
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2013-01-10 10:49:22 +01:00
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2013-01-10 Will Newton <will.newton@imgtec.com>
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* Makefile.am: Add Meta.
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* configure.in: Add Meta.
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* disassemble.c: Add Meta support.
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* metag-dis.c: New file.
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* Makefile.in: Regenerate.
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* configure: Regenerate.
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2013-01-07 16:09:07 +01:00
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2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
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(match_opcode): Rename to cr16_match_opcode.
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2013-01-04 18:22:53 +01:00
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2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
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* mips-dis.c: Add names for CP0 registers of r5900.
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* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
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instructions sq and lq.
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Add support for MIPS r5900 CPU.
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Add support for 128 bit MMI (Multimedia Instructions).
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Add support for EE instructions (Emotion Engine).
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Disable unsupported floating point instructions (64 bit and
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undefined compare operations).
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Enable instructions of MIPS ISA IV which are supported by r5900.
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Disable 64 bit co processor instructions.
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Disable 64 bit multiplication and division instructions.
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Disable instructions for co-processor 2 and 3, because these are
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not supported (preparation for later VU0 support (Vector Unit)).
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Disable cvt.w.s because this behaves like trunc.w.s and the
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correct execution can't be ensured on r5900.
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Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
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will confuse less developers and compilers.
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2013-01-04 14:32:06 +01:00
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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2013-01-04 15:59:33 +01:00
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* aarch64-opc.c (aarch64_print_operand): Change to print
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AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
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in comment.
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* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
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from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
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OP_MOV_IMM_WIDE.
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2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
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* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
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PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
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2013-01-04 14:32:06 +01:00
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2013-01-02 18:15:38 +01:00
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2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (process_copyright): Update copyright year to 2013.
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2013-01-02 14:13:36 +01:00
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2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
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2012-12-17 17:56:12 +01:00
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2013-01-02 14:13:36 +01:00
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* cr16-dis.c (match_opcode,make_instruction): Remove static
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declaration.
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(dwordU,wordU): Moved typedefs to opcode/cr16.h
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(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
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2012-12-17 17:56:12 +01:00
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2013-01-02 14:13:36 +01:00
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For older changes see ChangeLog-2012
|
1999-05-03 09:29:11 +02:00
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2013-01-02 14:13:36 +01:00
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Copyright (C) 2013 Free Software Foundation, Inc.
|
2012-12-10 13:48:03 +01:00
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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1999-05-03 09:29:11 +02:00
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Local Variables:
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2001-01-11 20:01:42 +01:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 09:29:11 +02:00
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version-control: never
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End:
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