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opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct register use annotation of "alnv.ps". gas/testsuite/ * gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction branch swapping. * gas/mips/alnv_ps-swap.s: Source for the new test. * gas/mips/mips.exp: Run the new test.
2011-02-28 17:34:39 +01:00
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (mips_builtin_opcodes): Correct register use
annotation of "alnv.ps".
gas/ * config/tc-mips.c (macro): Handle M_PREF_AB. include/opcode/ * mips.h (M_PREF_AB): New enum value. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
2011-02-28 17:06:51 +01:00
2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
opcodes: blackfin: drop null/nul checks in OUTS Parts of the disassembler rely on the disasm info never being NULL (such as being able to read memory to disassemble in the first place). So drop useless null checks in the OUTS helper. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-22 21:52:31 +01:00
2011-02-22 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
opcodes: blackfin: use OUTS helper We have an OUTS helper to handle outf fprintf_func logic, so conver the few places not using it over. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-22 21:51:42 +01:00
2011-02-22 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
opcodes: blackfin: clean up saved_state Mark the state static, punt unused members, unify indexable register lookups, and abort when there is a register lookup failure. Otherwise we return NULL and the calling code assumes a valid pointer is returned. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-20 02:26:14 +01:00
2011-02-19 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
exception, end_of_registers, msize, memory, bfd_mach.
(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
LB0REG, LC1REG, LT1REG, LB1REG): Delete
(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
(get_allreg): Change to new defines. Fallback to abort().
opcodes: blackfin: fix style Non-functional thrashing to the GNU style. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 18:12:05 +01:00
2011-02-14 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c: Add whitespace/parenthesis where needed.
opcodes: blackfin: catch invalid loopsetup insns The LoopSetup insn is only valid when the reg field is 0-7, so don't go decoding it incorrectly when reg is 8-15. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-14 06:21:04 +01:00
2011-02-14 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
than 7.
Remove freebsd1 from libtool.m4 macros and config.rpath. /: Import from Libtool and gnulib: 2011-01-27 Gerald Pfeifer <gerald@pfeifer.com> Prepare for supporting FreeBSD 10. * config.rpath: Remove handling of freebsd1* which soon would match FreeBSD 10.0. 2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change) Remove support for FreeBSD 1.x. * libtool.m4 (_LT_LINKER_SHLIBS) (_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which soon would incorrectly match FreeBSD 10.0. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.
2011-02-13 22:00:14 +01:00
2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* configure: Regenerate.
opcodes: blackfin: fix decoding of ABS The single cycle dual mac ABS insn was incorrectly decoding the mac1 part of the insn. Once we fix the decode, update the gas tests to have the correct output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 19:55:22 +01:00
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
opcodes: blackfin: fix decoding of dsp mult insns When assigning to a register half, the mac0 part of the mult insn was not decoding properly. It would always show a full dreg instead of the dreg low half. Once we fix the disassembler, we have to update a few of the gas tests as their previous expected output was incorrect. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 19:54:49 +01:00
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
dregs only when P is set, and dregs_lo otherwise.
gas/opcodes: blackfin: punt BYTEOP2M insn support The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-13 19:53:16 +01:00
2011-02-13 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
opcodes: blackfin: add missing space after PRNT insn Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 20:38:11 +01:00
2011-02-12 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
opcodes: blackfin: drop "GP" register There never was a "GP" register, so punt it from the decode map. It's a hold over from a very old processor definition and never made it into actual silicon. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 20:37:32 +01:00
2011-02-12 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (machine_registers): Delete REG_GP.
(reg_names): Delete "GP".
(decode_allregs): Change REG_GP to REG_LASTREG.
gas/opcodes: blackfin: move dsp mac func defines to common header The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 20:36:31 +01:00
2011-02-12 Mike Frysinger <vapier@gentoo.org>
Swap ChangeLog entries.
2011-02-28 17:03:38 +01:00
* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
M_IH, M_IU): Delete.
gas/opcodes: blackfin: move dsp mac func defines to common header The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-12 20:36:31 +01:00
opcodes: blackfin: constify register names Constify the array itself since it need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-02-11 20:03:27 +01:00
2011-02-11 Mike Frysinger <vapier@gentoo.org>
* bfin-dis.c (reg_names): Add const.
(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
decode_counters, decode_allregs): Likewise.
2011-02-09 Michael Snyder <msnyder@vmware.com> * i386-dis.c (OP_J): Parenthesize expression to prevent truncated addresses. (print_insn): Fix indentation off-by-one.
2011-02-09 19:43:41 +01:00
2011-02-09 Michael Snyder <msnyder@vmware.com>
* i386-dis.c (OP_J): Parenthesize expression to prevent
truncated addresses.
(print_insn): Fix indentation off-by-one.
Updated Danish translation.
2011-02-01 14:14:40 +01:00
2011-02-01 Nick Clifton <nickc@redhat.com>
* po/da.po: Updated Danish translation.
* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
2011-01-21 01:53:11 +01:00
2011-01-21 Dave Murphy <davem@devkitpro.org>
* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
Properly sign-extend byte. gas/testsuite/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.d: Updated. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (sIbT): New. (b_T_mode): Likewise. (dis386): Replace sIb with sIbT on "pushT". (x86_64_table): Replace sIb with Ib on "aam" and "aad". (OP_sI): Handle b_T_mode. Properly sign-extend byte.
2011-01-18 18:08:13 +01:00
2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (sIbT): New.
(b_T_mode): Likewise.
(dis386): Replace sIb with sIbT on "pushT".
(x86_64_table): Replace sIb with Ib on "aam" and "aad".
(OP_sI): Handle b_T_mode. Properly sign-extend byte.
opcodes/ * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.
2011-01-18 15:14:46 +01:00
2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated
Add support for TBM instructions. gas/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. * doc/c-i386.texi (i386-TBM): New section. opcodes/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * i386-dis.c (REG_XOP_TBM_01): New. (REG_XOP_TBM_02): New. (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 entries, and add bextr instruction. * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. (cpu_flags): Add CpuTBM. * i386-opc.h (CpuTBM) New. (i386_cpu_flags): Add bit cputbm. * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, blcs, blsfill, blsic, t1mskc, and tzmsk. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated gas/testsuite 2011-01-17 Quentin Neill <quentin.neill@amd.com> * gas/i386/tbm.s: New. * gas/i386/tbm.d: New. * gas/i386/tbm-intel.d: New. * gas/i386/x86-64-tbm.s: New. * gas/i386/x86-64-tbm.d: New. * gas/i386/x86-64-tbm-intel.d: New. * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. * gas/i386/arch-10.s: Add a TBM instruction. * gas/i386/arch-10-1.l: Add TBM instruction pattern. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-arch-2.d: Likewise.
2011-01-17 19:40:36 +01:00
2011-01-17 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (REG_XOP_TBM_01): New.
(REG_XOP_TBM_02): New.
(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
entries, and add bextr instruction.
* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
(cpu_flags): Add CpuTBM.
* i386-opc.h (CpuTBM) New.
(i386_cpu_flags): Add bit cputbm.
* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
blcs, blsfill, blsic, t1mskc, and tzmsk.
* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
2011-01-12 08:06:29 +01:00
2011-01-12 DJ Delorie <dj@redhat.com>
* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
Take unadjusted offset for loongson3a specific instructions.
2011-01-11 08:22:09 +01:00
2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
* mips-dis.c (print_insn_args): Adjust the value to print the real
offset for "+c" argument.
* po/da.po: Updated Danish translation.
2011-01-10 14:51:10 +01:00
2011-01-10 Nick Clifton <nickc@redhat.com>
* po/da.po: Updated Danish translation.
gas/testsuite/ * gas/arm/blx-bad.s: New. * gas/arm/blx-bad.d: New. opcodes/ * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
2011-01-06 15:30:43 +01:00
2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
Implement BMI instructions.
2011-01-05 01:16:57 +01:00
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (REG_VEX_38F3): New.
(PREFIX_0FBC): Likewise.
(PREFIX_VEX_38F2): Likewise.
(PREFIX_VEX_38F3_REG_1): Likewise.
(PREFIX_VEX_38F3_REG_2): Likewise.
(PREFIX_VEX_38F3_REG_3): Likewise.
(PREFIX_VEX_38F7): Likewise.
(VEX_LEN_38F2_P_0): Likewise.
(VEX_LEN_38F3_R_1_P_0): Likewise.
(VEX_LEN_38F3_R_2_P_0): Likewise.
(VEX_LEN_38F3_R_3_P_0): Likewise.
(VEX_LEN_38F7_P_0): Likewise.
(dis386_twobyte): Use PREFIX_0FBC.
(reg_table): Add REG_VEX_38F3.
(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
PREFIX_VEX_38F7.
(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
VEX_LEN_38F7_P_0.
* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
(cpu_flags): Add CpuBMI.
* i386-opc.h (CpuBMI): New.
(i386_cpu_flags): Add cpubmi.
* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Add VexGdq. 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VexGdq): New. (OP_VEX): Handle dq_mode.
2011-01-04 21:53:32 +01:00
2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (VexGdq): New.
(OP_VEX): Handle dq_mode.
Update copyright to 2011. binutils/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.c (print_version): Update copyright to 2011. gas/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * gas.c (parse_args): Update copyright to 2011. gold/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.cc (print_version): Update copyright to 2011. ld/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * ldver.c (ldversion): Update copyright to 2011. opcodes/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update copyright to 2011.
2011-01-01 21:55:48 +01:00
2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (process_copyright): Update copyright to 2011.
Rotate binutils ChangeLogs.
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For older changes see ChangeLog-2010
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