binutils-gdb/opcodes/cgen-opc.c

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/* CGEN generic opcode support.
Copyright (C) 1996-2020 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
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You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#include "sysdep.h"
PR 14072 * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * alpha-opc.c: Include sysdep.h before any other header file. * alpha-dis.c: Likewise. * avr-dis.c: Likewise. * cgen-opc.c: Likewise. * cr16-dis.c: Likewise. * cris-dis.c: Likewise. * crx-dis.c: Likewise. * d10v-dis.c: Likewise. * d10v-opc.c: Likewise. * d30v-dis.c: Likewise. * d30v-opc.c: Likewise. * h8500-dis.c: Likewise. * i370-dis.c: Likewise. * i370-opc.c: Likewise. * m10200-dis.c: Likewise. * m10300-dis.c: Likewise. * micromips-opc.c: Likewise. * mips-opc.c: Likewise. * mips61-opc.c: Likewise. * moxie-dis.c: Likewise. * or32-opc.c: Likewise. * pj-dis.c: Likewise. * ppc-dis.c: Likewise. * ppc-opc.c: Likewise. * s390-dis.c: Likewise. * sh-dis.c: Likewise. * sh64-dis.c: Likewise. * sparc-dis.c: Likewise. * sparc-opc.c: Likewise. * spu-dis.c: Likewise. * tic30-dis.c: Likewise. * tic54x-dis.c: Likewise. * tic80-dis.c: Likewise. * tic80-opc.c: Likewise. * tilegx-dis.c: Likewise. * tilepro-dis.c: Likewise. * v850-dis.c: Likewise. * v850-opc.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * xgate-dis.c: Likewise. * xtensa-dis.c: Likewise. * rl78-decode.opc: Likewise. * rl78-decode.c: Regenerate. * rx-decode.opc: Likewise. * rx-decode.c: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * sysdep.h: Generate an error if included before config.h. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in.h: Generate an error if included before config.h. * sysdep.h: Likewise. * bfd-in2.h: Regenerate. * compress.c: Remove #include "config.h". * plugin.c: Likewise. * elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h. * elf64-hppa.c: Likewise. * som.c: Likewise. * xsymc.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * aclocal.m4: Regenerate. * Makefile.am: Use wrappers around C files generated by flex. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * itbl-lex-wrapper.c: New file. * config/bfin-lex-wrapper.c: New file. * cgen.c: Include as.h before setjmp.h. * config/tc-dlx.c: Include as.h before any other header. * config/tc-h8300.c: Likewise. * config/tc-lm32.c: Likewise. * config/tc-mep.c: Likewise. * config/tc-microblaze.c: Likewise. * config/tc-mmix.c: Likewise. * config/tc-msp430.c: Likewise. * config/tc-or32.c: Likewise. * config/tc-tic4x.c: Likewise. * config/tc-tic54x.c: Likewise. * config/tc-xtensa.c: Likewise. * configure.in: Add check that sysdep.h has been included before any system header files. * configure: Regenerate. * config.in: Regenerate. * unwind-ia64.h: Include config.h.
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#include "alloca-conf.h"
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#include <stdio.h>
#include "ansidecl.h"
#include "libiberty.h"
#include "safe-ctype.h"
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#include "bfd.h"
#include "symcat.h"
#include "opcode/cgen.h"
static unsigned int hash_keyword_name
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(const CGEN_KEYWORD *, const char *, int);
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static unsigned int hash_keyword_value
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(const CGEN_KEYWORD *, unsigned int);
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static void build_keyword_hash_tables
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(CGEN_KEYWORD *);
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/* Return number of hash table entries to use for N elements. */
#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31)
/* Look up *NAMEP in the keyword table KT.
The result is the keyword entry or NULL if not found. */
const CGEN_KEYWORD_ENTRY *
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cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name)
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{
const CGEN_KEYWORD_ENTRY *ke;
const char *p,*n;
if (kt->name_hash_table == NULL)
build_keyword_hash_tables (kt);
ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)];
/* We do case insensitive comparisons.
If that ever becomes a problem, add an attribute that denotes
"do case sensitive comparisons". */
while (ke != NULL)
{
n = name;
p = ke->name;
while (*p
&& (*p == *n
|| (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n)))))
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++n, ++p;
if (!*p && !*n)
return ke;
ke = ke->next_name;
}
if (kt->null_entry)
return kt->null_entry;
return NULL;
}
/* Look up VALUE in the keyword table KT.
The result is the keyword entry or NULL if not found. */
const CGEN_KEYWORD_ENTRY *
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cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value)
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{
const CGEN_KEYWORD_ENTRY *ke;
if (kt->name_hash_table == NULL)
build_keyword_hash_tables (kt);
ke = kt->value_hash_table[hash_keyword_value (kt, value)];
while (ke != NULL)
{
if (value == ke->value)
return ke;
ke = ke->next_value;
}
return NULL;
}
/* Add an entry to a keyword table. */
void
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cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke)
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{
unsigned int hash;
size_t i;
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if (kt->name_hash_table == NULL)
build_keyword_hash_tables (kt);
hash = hash_keyword_name (kt, ke->name, 0);
ke->next_name = kt->name_hash_table[hash];
kt->name_hash_table[hash] = ke;
hash = hash_keyword_value (kt, ke->value);
ke->next_value = kt->value_hash_table[hash];
kt->value_hash_table[hash] = ke;
if (ke->name[0] == 0)
kt->null_entry = ke;
for (i = 1; i < strlen (ke->name); i++)
if (! ISALNUM (ke->name[i])
&& ! strchr (kt->nonalpha_chars, ke->name[i]))
{
size_t idx = strlen (kt->nonalpha_chars);
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/* If you hit this limit, please don't just
increase the size of the field, instead
look for a better algorithm. */
if (idx >= sizeof (kt->nonalpha_chars) - 1)
abort ();
kt->nonalpha_chars[idx] = ke->name[i];
kt->nonalpha_chars[idx+1] = 0;
}
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}
/* FIXME: Need function to return count of keywords. */
/* Initialize a keyword table search.
SPEC is a specification of what to search for.
A value of NULL means to find every keyword.
Currently NULL is the only acceptable value [further specification
deferred].
The result is an opaque data item used to record the search status.
It is passed to each call to cgen_keyword_search_next. */
CGEN_KEYWORD_SEARCH
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cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec)
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{
CGEN_KEYWORD_SEARCH search;
/* FIXME: Need to specify format of params. */
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if (spec != NULL)
abort ();
if (kt->name_hash_table == NULL)
build_keyword_hash_tables (kt);
search.table = kt;
search.spec = spec;
search.current_hash = 0;
search.current_entry = NULL;
return search;
}
/* Return the next keyword specified by SEARCH.
The result is the next entry or NULL if there are no more. */
const CGEN_KEYWORD_ENTRY *
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cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search)
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{
/* Has search finished? */
if (search->current_hash == search->table->hash_table_size)
return NULL;
/* Search in progress? */
if (search->current_entry != NULL
/* Anything left on this hash chain? */
&& search->current_entry->next_name != NULL)
{
search->current_entry = search->current_entry->next_name;
return search->current_entry;
}
/* Move to next hash chain [unless we haven't started yet]. */
if (search->current_entry != NULL)
++search->current_hash;
while (search->current_hash < search->table->hash_table_size)
{
search->current_entry = search->table->name_hash_table[search->current_hash];
if (search->current_entry != NULL)
return search->current_entry;
++search->current_hash;
}
return NULL;
}
/* Return first entry in hash chain for NAME.
If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */
static unsigned int
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hash_keyword_name (const CGEN_KEYWORD *kt,
const char *name,
int case_sensitive_p)
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{
unsigned int hash;
if (case_sensitive_p)
for (hash = 0; *name; ++name)
hash = (hash * 97) + (unsigned char) *name;
else
for (hash = 0; *name; ++name)
hash = (hash * 97) + (unsigned char) TOLOWER (*name);
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return hash % kt->hash_table_size;
}
/* Return first entry in hash chain for VALUE. */
static unsigned int
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hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value)
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{
return value % kt->hash_table_size;
}
/* Build a keyword table's hash tables.
We probably needn't build the value hash table for the assembler when
we're using the disassembler, but we keep things simple. */
static void
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build_keyword_hash_tables (CGEN_KEYWORD *kt)
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{
int i;
/* Use the number of compiled in entries as an estimate for the
typical sized table [not too many added at runtime]. */
unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries);
kt->hash_table_size = size;
kt->name_hash_table = (CGEN_KEYWORD_ENTRY **)
xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *));
memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *));
kt->value_hash_table = (CGEN_KEYWORD_ENTRY **)
xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *));
memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *));
/* The table is scanned backwards as we want keywords appearing earlier to
be prefered over later ones. */
for (i = kt->num_init_entries - 1; i >= 0; --i)
cgen_keyword_add (kt, &kt->init_entries[i]);
}
/* Hardware support. */
/* Lookup a hardware element by its name.
Returns NULL if NAME is not supported by the currently selected
mach/isa. */
const CGEN_HW_ENTRY *
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cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name)
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{
unsigned int i;
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const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
for (i = 0; i < cd->hw_table.num_entries; ++i)
if (hw[i] && strcmp (name, hw[i]->name) == 0)
return hw[i];
return NULL;
}
/* Lookup a hardware element by its number.
Hardware elements are enumerated, however it may be possible to add some
at runtime, thus HWNUM is not an enum type but rather an int.
Returns NULL if HWNUM is not supported by the currently selected mach. */
const CGEN_HW_ENTRY *
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cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum)
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{
unsigned int i;
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const CGEN_HW_ENTRY **hw = cd->hw_table.entries;
/* ??? This can be speeded up. */
for (i = 0; i < cd->hw_table.num_entries; ++i)
if (hw[i] && hwnum == hw[i]->type)
return hw[i];
return NULL;
}
/* Operand support. */
/* Lookup an operand by its name.
Returns NULL if NAME is not supported by the currently selected
mach/isa. */
const CGEN_OPERAND *
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cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name)
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{
unsigned int i;
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const CGEN_OPERAND **op = cd->operand_table.entries;
for (i = 0; i < cd->operand_table.num_entries; ++i)
if (op[i] && strcmp (name, op[i]->name) == 0)
return op[i];
return NULL;
}
/* Lookup an operand by its number.
Operands are enumerated, however it may be possible to add some
at runtime, thus OPNUM is not an enum type but rather an int.
Returns NULL if OPNUM is not supported by the currently selected
mach/isa. */
const CGEN_OPERAND *
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cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum)
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{
return cd->operand_table.entries[opnum];
}
/* Instruction support. */
/* Return number of instructions. This includes any added at runtime. */
int
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cgen_insn_count (CGEN_CPU_DESC cd)
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{
int count = cd->insn_table.num_init_entries;
CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries;
for ( ; rt_insns != NULL; rt_insns = rt_insns->next)
++count;
return count;
}
/* Return number of macro-instructions.
This includes any added at runtime. */
int
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cgen_macro_insn_count (CGEN_CPU_DESC cd)
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{
int count = cd->macro_insn_table.num_init_entries;
CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries;
for ( ; rt_insns != NULL; rt_insns = rt_insns->next)
++count;
return count;
}
/* Cover function to read and properly byteswap an insn value. */
CGEN_INSN_INT
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
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cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length,
int endian)
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{
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
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int big_p = (endian == CGEN_ENDIAN_BIG);
int insn_chunk_bitsize = cd->insn_chunk_bitsize;
CGEN_INSN_INT value = 0;
if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length)
{
/* We need to divide up the incoming value into insn_chunk_bitsize-length
segments, and endian-convert them, one at a time. */
int i;
2015-08-12 13:45:07 +02:00
/* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();
for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
{
int bit_index;
bfd_vma this_value;
bit_index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */
this_value = bfd_get_bits (& buf[bit_index / 8], insn_chunk_bitsize, big_p);
value = (value << insn_chunk_bitsize) | this_value;
}
}
else
{
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
value = bfd_get_bits (buf, length, endian == CGEN_ENDIAN_BIG);
}
return value;
1999-05-03 09:29:11 +02:00
}
/* Cover function to store an insn value properly byteswapped. */
void
2003-08-08 23:21:24 +02:00
cgen_put_insn_value (CGEN_CPU_DESC cd,
unsigned char *buf,
int length,
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
CGEN_INSN_INT value,
int endian)
1999-05-03 09:29:11 +02:00
{
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
int big_p = (endian == CGEN_ENDIAN_BIG);
int insn_chunk_bitsize = cd->insn_chunk_bitsize;
if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length)
{
/* We need to divide up the incoming value into insn_chunk_bitsize-length
segments, and endian-convert them, one at a time. */
int i;
2015-08-12 13:45:07 +02:00
/* Enforce divisibility. */
if ((length % insn_chunk_bitsize) != 0)
abort ();
for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */
{
int bit_index;
bit_index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */
bfd_put_bits ((bfd_vma) value, & buf[bit_index / 8], insn_chunk_bitsize, big_p);
value >>= insn_chunk_bitsize;
}
}
else
{
bfd_put_bits ((bfd_vma) value, buf, length, big_p);
}
1999-05-03 09:29:11 +02:00
}
/* Look up instruction INSN_*_VALUE and extract its fields.
INSN_INT_VALUE is used if CGEN_INT_INSN_P.
Otherwise INSN_BYTES_VALUE is used.
INSN, if non-null, is the insn table entry.
Otherwise INSN_*_VALUE is examined to compute it.
LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0.
0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
If INSN != NULL, LENGTH must be valid.
ALIAS_P is non-zero if alias insns are to be included in the search.
The result is a pointer to the insn table entry, or NULL if the instruction
wasn't recognized. */
/* ??? Will need to be revisited for VLIW architectures. */
const CGEN_INSN *
2003-08-08 23:21:24 +02:00
cgen_lookup_insn (CGEN_CPU_DESC cd,
const CGEN_INSN *insn,
CGEN_INSN_INT insn_int_value,
/* ??? CGEN_INSN_BYTES would be a nice type name to use here. */
unsigned char *insn_bytes_value,
int length,
CGEN_FIELDS *fields,
int alias_p)
1999-05-03 09:29:11 +02:00
{
CGEN_EXTRACT_INFO ex_info;
CGEN_EXTRACT_INFO *info;
if (cd->int_insn_p)
{
info = NULL;
insn_bytes_value = (unsigned char *) xmalloc (cd->max_insn_bitsize / 8);
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value,
cd->insn_endian);
1999-05-03 09:29:11 +02:00
}
else
{
info = &ex_info;
ex_info.dis_info = NULL;
ex_info.insn_bytes = insn_bytes_value;
ex_info.valid = -1;
opcodes: discriminate endianness and insn-endianness in CGEN ports The CGEN support code in opcodes accesses instruction contents using a couple of functions defined in cgen-opc.c: cgen_get_insn_value and cgen_put_insn_value. These functions use the "instruction endianness" in the CPU description to order the read/written bytes. The process of writing an instruction to the object file is: a) cgen_put_insn_value ;; Writes out the opcodes. b) ARCH_cgen_insert_operand insert_normal insert_1 cgen_put_insn_value ;; Writes out the bytes of the ;; operand. Likewise, the process of reading an instruction from the object file is: a) cgen_get_insn_value ;; Reads the opcodes. b) ARCH_cgen_extract_operand extract_normal extract_1 cgen_get_insn_value ;; Reads in the bytes of the ;; operand. As can be seen above, cgen_{get,put}_insn_value are used to both process the instruction opcodes (the constant fields conforming the base instruction) and also the values of the instruction operands, such as immediates. This is problematic for architectures in which the endianness of instructions is different to the endianness of data. An example is BPF, where instructions are always encoded big-endian but the data may be either big or little. This patch changes the cgen_{get,put}_insn_value functions in order to get an extra argument with the endianness to use, and adapts the existin callers to these functions in order to provide cd->endian or cd->insn_endian, whatever appropriate. Callers like extract_1 and insert_1 pass cd->endian (since they are reading/writing operand values) while callers reading/writing the base instruction pass cd->insn_endian instead. A few little adjustments have been needed in some existing CGEN based ports: * The BPF assembler uses cgen_put_insn_value. It has been adapted to pass the new endian argument. * The mep port has code in mep.opc that uses cgen_{get,put}_insn_value. It has been adapted to pass the new endianargument. Ditto for a call in the assembler. Tested with --enable-targets=all. Regested in all supported targets. No regressions. include/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/cgen.h: Get an `endian' argument in both cgen_get_insn_value and cgen_put_insn_value. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. (cgen_put_insn_value): Likewise. (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. * cgen-dis.in (print_insn): Likewise. * cgen-ibld.in (insert_1): Likewise. (insert_1): Likewise. (insert_insn_normal): Likewise. (extract_1): Likewise. * bpf-dis.c: Regenerate. * bpf-ibld.c: Likewise. * bpf-ibld.c: Likewise. * cgen-dis.in: Likewise. * cgen-ibld.in: Likewise. * cgen-opc.c: Likewise. * epiphany-dis.c: Likewise. * epiphany-ibld.c: Likewise. * fr30-dis.c: Likewise. * fr30-ibld.c: Likewise. * frv-dis.c: Likewise. * frv-ibld.c: Likewise. * ip2k-dis.c: Likewise. * ip2k-ibld.c: Likewise. * iq2000-dis.c: Likewise. * iq2000-ibld.c: Likewise. * lm32-dis.c: Likewise. * lm32-ibld.c: Likewise. * m32c-dis.c: Likewise. * m32c-ibld.c: Likewise. * m32r-dis.c: Likewise. * m32r-ibld.c: Likewise. * mep-dis.c: Likewise. * mep-ibld.c: Likewise. * mt-dis.c: Likewise. * mt-ibld.c: Likewise. * or1k-dis.c: Likewise. * or1k-ibld.c: Likewise. * xc16x-dis.c: Likewise. * xc16x-ibld.c: Likewise. * xstormy16-dis.c: Likewise. * xstormy16-ibld.c: Likewise. gas/ChangeLog: 2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> * cgen.c (gas_cgen_finish_insn): Pass the endianness to cgen_put_insn_value. (gas_cgen_md_apply_fix): Likewise. (gas_cgen_md_apply_fix): Likewise. * config/tc-bpf.c (md_apply_fix): Pass data endianness to cgen_put_insn_value. * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to cgen_put_insn_value. cpu/ChangeLog: 2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> * mep.opc (print_slot_insn): Pass the insn endianness to cgen_get_insn_value.
2020-06-04 16:15:53 +02:00
insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length,
cd->insn_endian);
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}
if (!insn)
{
const CGEN_INSN_LIST *insn_list;
/* The instructions are stored in hash lists.
Pick the first one and keep trying until we find the right one. */
insn_list = cgen_dis_lookup_insn (cd, (char *) insn_bytes_value,
insn_int_value);
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while (insn_list != NULL)
{
insn = insn_list->insn;
if (alias_p
/* FIXME: Ensure ALIAS attribute always has same index. */
|| ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS))
{
/* Basic bit mask must be correct. */
/* ??? May wish to allow target to defer this check until the
extract handler. */
if ((insn_int_value & CGEN_INSN_BASE_MASK (insn))
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== CGEN_INSN_BASE_VALUE (insn))
{
/* ??? 0 is passed for `pc' */
int elength = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, info, insn_int_value, fields, (bfd_vma) 0);
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if (elength > 0)
{
/* sanity check */
if (length != 0 && length != elength)
abort ();
break;
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}
}
}
insn_list = insn_list->next;
}
}
else
{
/* Sanity check: can't pass an alias insn if ! alias_p. */
if (! alias_p
&& CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS))
abort ();
/* Sanity check: length must be correct. */
if (length != CGEN_INSN_BITSIZE (insn))
abort ();
/* ??? 0 is passed for `pc' */
length = CGEN_EXTRACT_FN (cd, insn)
(cd, insn, info, insn_int_value, fields, (bfd_vma) 0);
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/* Sanity check: must succeed.
Could relax this later if it ever proves useful. */
if (length == 0)
abort ();
}
if (cd->int_insn_p)
free (insn_bytes_value);
return insn;
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}
/* Fill in the operand instances used by INSN whose operands are FIELDS.
INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
in. */
void
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cgen_get_insn_operands (CGEN_CPU_DESC cd,
const CGEN_INSN *insn,
const CGEN_FIELDS *fields,
int *indices)
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{
const CGEN_OPINST *opinst;
int i;
if (insn->opinst == NULL)
abort ();
for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst)
{
enum cgen_operand_type op_type = opinst->op_type;
if (op_type == CGEN_OPERAND_NIL)
indices[i] = opinst->index;
else
indices[i] = (*cd->get_int_operand) (cd, op_type, fields);
}
}
/* Cover function to cgen_get_insn_operands when either INSN or FIELDS
isn't known.
The INSN, INSN_*_VALUE, and LENGTH arguments are passed to
cgen_lookup_insn unchanged.
INSN_INT_VALUE is used if CGEN_INT_INSN_P.
Otherwise INSN_BYTES_VALUE is used.
The result is the insn table entry or NULL if the instruction wasn't
recognized. */
const CGEN_INSN *
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cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd,
const CGEN_INSN *insn,
CGEN_INSN_INT insn_int_value,
/* ??? CGEN_INSN_BYTES would be a nice type name to use here. */
unsigned char *insn_bytes_value,
int length,
int *indices,
CGEN_FIELDS *fields)
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{
/* Pass non-zero for ALIAS_P only if INSN != NULL.
If INSN == NULL, we want a real insn. */
insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value,
length, fields, insn != NULL);
if (! insn)
return NULL;
cgen_get_insn_operands (cd, insn, fields, indices);
return insn;
}
/* Allow signed overflow of instruction fields. */
void
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cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd)
{
cd->signed_overflow_ok_p = 1;
}
/* Generate an error message if a signed field in an instruction overflows. */
void
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cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd)
{
cd->signed_overflow_ok_p = 0;
}
/* Will an error message be generated if a signed field in an instruction overflows ? */
unsigned int
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cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd)
{
return cd->signed_overflow_ok_p;
}