Commit Graph

15 Commits

Author SHA1 Message Date
Alan Modra b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra a8bfaadbb4 aarch64 bfd.h tidy
bfd/
	* bfd-in.h: Move aarch64 declarations and defines..
	* cpu-aarch64.h: ..to here, new file..
	* elfxx-aarch64.h: ..and here.
	* cpu-aarch64.c: Include cpu-aarch64.h.
	* elfnn-aarch64.c: Likewise.
	* bfd-in2.h: Regenerate.
ld/
	* emultempl/aarch64elf.em: Include elfxx-aarch64.h.
2019-09-23 10:27:21 +09:30
Nick Clifton aebcfb76fc Enhance the disassembler so that it will reliably determine whether a reloc applies to the middle of the next insn.
PR 24907
binutils* objdump.c (null_print): New function.
	(disassemble_bytes): Delete previous_octets local and replace with
	a test of the max_reloc_offset_into_insn field of the
	bfd_arch_info structure.  If a reloc is a potential match for the
	next insn, then perform a dummy disassembly in order to calculate
	its real length.

bfd	* archures.c (bfd_arch_info_type): Add max_reloc_offset_into_insn
	field.
	(bfd_default_arch_struct): Initialise the new field.
	* bfd-in2.h: Regenerate.
	* cpu-aarch64.c: Initialise the new field.
	* cpu-alpha.c: Likewise.
	* cpu-arc.c: Likewise.
	* cpu-arm.c: Likewise.
	* cpu-avr.c: Likewise.
	* cpu-bfin.c: Likewise.
	* cpu-bpf.c: Likewise.
	* cpu-cr16.c: Likewise.
	* cpu-cr16c.c: Likewise.
	* cpu-cris.c: Likewise.
	* cpu-crx.c: Likewise.
	* cpu-csky.c: Likewise.
	* cpu-d10v.c: Likewise.
	* cpu-d30v.c: Likewise.
	* cpu-dlx.c: Likewise.
	* cpu-epiphany.c: Likewise.
	* cpu-fr30.c: Likewise.
	* cpu-frv.c: Likewise.
	* cpu-ft32.c: Likewise.
	* cpu-h8300.c: Likewise.
	* cpu-hppa.c: Likewise.
	* cpu-i386.c: Likewise.
	* cpu-ia64.c: Likewise.
	* cpu-iamcu.c: Likewise.
	* cpu-ip2k.c: Likewise.
	* cpu-iq2000.c: Likewise.
	* cpu-k1om.c: Likewise.
	* cpu-l1om.c: Likewise.
	* cpu-lm32.c: Likewise.
	* cpu-m10200.c: Likewise.
	* cpu-m10300.c: Likewise.
	* cpu-m32c.c: Likewise.
	* cpu-m32r.c: Likewise.
	* cpu-m68hc11.c: Likewise.
	* cpu-m68hc12.c: Likewise.
	* cpu-m68k.c: Likewise.
	* cpu-m9s12x.c: Likewise.
	* cpu-m9s12xg.c: Likewise.
	* cpu-mcore.c: Likewise.
	* cpu-mep.c: Likewise.
	* cpu-metag.c: Likewise.
	* cpu-microblaze.c: Likewise.
	* cpu-mips.c: Likewise.
	* cpu-mmix.c: Likewise.
	* cpu-moxie.c: Likewise.
	* cpu-msp430.c: Likewise.
	* cpu-mt.c: Likewise.
	* cpu-nds32.c: Likewise.
	* cpu-nfp.c: Likewise.
	* cpu-nios2.c: Likewise.
	* cpu-ns32k.c: Likewise.
	* cpu-or1k.c: Likewise.
	* cpu-pdp11.c: Likewise.
	* cpu-pj.c: Likewise.
	* cpu-plugin.c: Likewise.
	* cpu-powerpc.c: Likewise.
	* cpu-pru.c: Likewise.
	* cpu-riscv.c: Likewise.
	* cpu-rl78.c: Likewise.
	* cpu-rs6000.c: Likewise.
	* cpu-rx.c: Likewise.
	* cpu-s12z.c: Likewise.
	* cpu-s390.c: Likewise.
	* cpu-score.c: Likewise.
	* cpu-sh.c: Likewise.
	* cpu-sparc.c: Likewise.
	* cpu-spu.c: Likewise.
	* cpu-tic30.c: Likewise.
	* cpu-tic4x.c: Likewise.
	* cpu-tic54x.c: Likewise.
	* cpu-tic6x.c: Likewise.
	* cpu-tic80.c: Likewise.
	* cpu-tilegx.c: Likewise.
	* cpu-tilepro.c: Likewise.
	* cpu-v850.c: Likewise.
	* cpu-v850_rh850.c: Likewise.
	* cpu-vax.c: Likewise.
	* cpu-visium.c: Likewise.
	* cpu-wasm32.c: Likewise.
	* cpu-xc16x.c: Likewise.
	* cpu-xgate.c: Likewise.
	* cpu-xstormy16.c: Likewise.
	* cpu-xtensa.c: Likewise.
	* cpu-z80.c: Likewise.
	* cpu-z8k.c: Likewise.

gas	* testsuite/gas/arm/pr24907.s: New test.
	* testsuite/gas/arm/pr24907.d: Expected disassembly.
2019-09-10 15:20:58 +01:00
Dennis Zhang 546053acfa Adds support for following CPUs to the ARM and Aarch64 assemblers: Cortex-A77, Cortex-A76AE, Cortex-A34, Cortex-A65, and Cortex-A65AE.
Related specifications can be found at
https://developer.arm.com/ip-products/processors.

gas	* NEWS: Mention the Arm and AArch64 new processors.
	* config/tc-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	Cortex-A77, cortex-A65AE, and Cortex-A76AE.
	* doc/c-aarch64.texi: Document new CPUs.
	* testsuite/gas/aarch64/cpu-cortex-a34.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a65ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a76ae.d: New test.
	* testsuite/gas/aarch64/cpu-cortex-a77.d: New test.
	* testsuite/gas/aarch64/nop-asm.s: New test.

bfd	* cpu-aarch64.c: New entries for Cortex-A34, Cortex-A65,
	 Cortex-A77, cortex-A65AE, and Cortex-A76AE.
2019-08-20 17:13:29 +01:00
Alan Modra 827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Alan Modra 219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Alan Modra 2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Yury Norov 3145b99715 bfd: aarch64: fix word and arrdess size declaration in ilp32 mode
ILP32 has 32-bit word and address, but currently they declared as 64-bit in
bfd_aarch64_arch_ilp32, which breaks further logic of bfd. This patch fixes it.

Glibc testsuite build with patched binutils shows that next tests stop to fail:
iconvdata/mtrace-tst-loading
iconvdata/tst-loading
iconvdata/tst-tables
localedata/mtrace-tst-leaks
localedata/tst-leaks
posix/tst-getaddrinfo4
posix/tst-getaddrinfo5
posix/tst-regex2
2016-12-21 17:56:03 +05:30
Yury Norov 7acd51d697 Revert "bfd: aarch64: fix word and arrdess size declaration in ilp32 mode"
This reverts commit a02c351265.
2016-12-14 11:57:42 +05:30
Yury Norov a02c351265 bfd: aarch64: fix word and arrdess size declaration in ilp32 mode 2016-12-14 11:07:24 +05:30
Alan Modra 6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Alan Modra 4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Yufeng Zhang cec5225bd8 [AArch64, ILP32] 2/6 Parametrize elfnn-aarch64.c and add basic support in ld
and gas.

bfd/

	* Makefile.am (BFD64_BACKENDS): Add elf32-aarch64.lo.
	(BUILD_CFILES): Add elf32-aarch64.c.
	(elf32-aarch64.c): New rule for generating from elfnn-aarch64.c.
	* Makefile.in: Re-generated.
	* archures.c (bfd_mach_aarch64_ilp32): New define.
	* bfd-in.h (bfd_elf32_aarch64_init_maps): New declaration.
	(bfd_elf32_aarch64_set_options): Ditto.
	(elf32_aarch64_setup_section_lists): Ditto.
	(elf32_aarch64_next_input_section): Ditto.
	(elf32_aarch64_size_stubs): Ditto.
	(elf32_aarch64_build_stubs): Ditto.
	* bfd-in2.h: Re-generated.
	* config.bfd (aarch64-*-elf): Add bfd_elf32_littleaarch64_vec
	and bfd_elf32_bigaarch64_vec.
	(aarch64-*-linux*): Likewise.
	(aarch64_be-*-elf): Likewise.
	(aarch64_be-*-linux*): Likewise.
	* configure.in (bfd_elf32_bigaarch64_vec)
	(bfd_elf32_littleaarch64_vec): New.
	* configure: Re-generated.
	* cpu-aarch64.c (compatible): Don't allow mixing ilp32 objects with
	lp64 ones.
	(bfd_aarch64_arch_ilp32): New.
	(bfd_aarch64_arch): Link to bfd_aarch64_arch_ilp32.
	* elfnn-aarch64.c (ARCH_SIZE): New define.
	(AARCH64_R, AARCH64_R_STR, LOG_FILE_ALIGN): New defines.
	(GOT_ENTRY_SIZE): Re-define as (ARCH_SIZE / 8).
	(elf64_aarch64_*): Rename to elfNN_aarch64_*.
	(ELF64_R_*): Rename to ELFNN_R_*.
	Plus other paramaterization.
	* targets.c (bfd_elf32_bigaarch64_vec, bfd_elf32_littleaarch64_vec):
	New declarations.
	(_bfd_target_vector): Add bfd_elf32_bigaarch64_vec and
	bfd_elf32_littleaarch64_vec.

gas/

	* config/tc-aarch64.c (ilp32_p): New static variable.
	(elf64_aarch64_target_format): Return the target according to the
	value of 'ilp32_p'.
	(md_begin): Determine 'mach' according to the value of 'ilp32_p'.
	(aarch64_opts): Add support for options '-milp32' and '-mlp64'.
	(aarch64_dwarf2_addr_size): New function.
	* config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration.
	(DWARF2_ADDR_SIZE): New define.

ld/

	* Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32.c.
	(eaarch64elf32.c): New dependency and rule.
	* Makefile.in: Re-generated.
	* configure.tgt (aarch64-*-elf): Add aarch64elf32.
	(aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise.
	* emulparams/aarch64elf32.sh: New file.
2013-06-26 10:41:42 +00:00
Nick Clifton a06ea96464 Add support for 64-bit ARM architecture: AArch64 2012-08-13 14:52:54 +00:00