The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode.
Once we've fixed that, it's easy to see that the disassembler also likes
to decode this insn incorrectly. So fix that and then add some tests.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA is very exact with regards to address truncation when
under/over flowing its 32bit range. On a 32bit system, things work the
same and so addresses are decoded properly. On a 64bit system though,
the decoded addresses may include the bits that are supposed to have
been truncated. So force a 32bit truncation after the address has been
calculated.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Many register move insns were not being decoded properly, so rewrite
the whole function to be a bit more manageable in terms of valid
combinations.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin disassembler was originally based on the premise of parsing
valid opcodes all the time, so some of the opcode checking can be a bit
fuzzy. This is exemplified in decoding of parallel insns where many
times things are decoded as invalid when in reality, they may not be
used in parallel combinations. So add parallel checking to most insn
decoding routines so we see ILLEGAL and not just whatever insn happens
to be close to a valid mnemonic, as well as some additional sub-opcode
checks.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The push/pop multiple insn has a 3 bit field for the P register range,
but only values of 0...5 are valid (P0 - P5). There is no such P6 or
P7 register, so mark these insns as illegal.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The saturation bit was missed when decoding a vector shift insn
leading to the output looking the same as the non-saturating insn.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
All ASTAT bits work in the hardware even though they aren't part of the
official Blackfin ISA. So decode every ASTAT field to make the output
a bit nicer when working with hand generated opcodes.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Sometimes the encoding in the opcode is a 4 bit field which defines a
register number. However, register numbers are only 0-7, so make sure
we call illegal for when the opcode register number is greater than 8.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some extended registers when given to the DBG/DBGCMPLX pseudo insns are
not encoded properly. So fix them, fix the display of them when being
disassembled, and add testcases.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it. And now
that the disassembler can handle it, make sure our assembler can output
it too.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
No need for these local structures related to formatting of output to
be writable, so constify the whole shebang.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* config/bfin-parse.y (asm_1): Implement HLT instruction.
Fix comments for DBGA, DBGAH and DBGAL.
* config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according
to the new encoding of DBGA, DBGAH, and DBGAL.
include/
* opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp.
(PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define.
(PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask,
PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask):
Adjust accordingly.
(init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and
PseudoDbg_Assert_grp_mask.
opcodes/
* bfin-dis.c (decode_pseudodbg_assert_0): Change according
to the new encoding of DBGA, DBGAH, and DBGAL.
(_print_insn_bfin): Likewise.
* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
data register in each rule that moves to the data
register.
gas/testsuite/
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
Add check for mismatch of accumulator and data register.
opcodes/
* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
multiply and multiply-accumulate to data register instruction.
Mike Frysinger
Alan Modra
Jie Zhang
Bernd Schmidt
Nick Clifton
Catherine Moore