* riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add
comment for SD field, and correct xlen calculation. For MISA, add
comment for MXL field, add call to register_size, and correct base
calculation.
This commit fixes some test failures in gdb.base/varargs.exp when
running on targets with floating point hardware. Floating point
unnamed (variadic) arguments should be passed in integer registers
according to the abi.
After this commit I see no failures in gdb.base/varargs.exp on 32 or
64 bit targets with floating point hardware.
gdb/ChangeLog:
* riscv-tdep.c (riscv_call_arg_scalar_float): Unnamed (variadic)
arguments are passed in integer registers.
(riscv_call_arg_complex_float): Likewise.
This fixes an ARI warning in riscv-tdep.c that whitespace before a
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_name): Fix ARI warning by removing
leading whitespace before #include line.
Currently, if the target announces that it has floating point
registers in its target description then GDB assumes that the hardware
float ABI should be used. However, there's nothing stopping a user
compiling a program for the soft-float abi, and then trying to run
this on a target with hardware floating point registers.
This commit adjusts the logic that decides if GDB should use the
hardware float abi. The primary decision now is based on what the ELF
currently being executed says in its headers. If the file was
compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w
float is used.
If the current BFD is not an ELF then we don't currently have a
mechanism for figuring out if the file was compiled for float or not.
In this case we disable the h/w float abi. This shouldn't be a
problem as, right now, the RISC-V linker can only produce ELFs.
If there is NO current BFD (can this happen?) then we will enable h/w
float abi if the target has floating point hardware, otherwise, s/w
float abi is used.
This commit also adds some sanity checking that the features requested
in the BFD (xlen and flen) match the target description.
For testing I ran the testsuite on a target that returns a target
description containing both integer and floating point registers, but
used a compiler that didn't have floating point support. Before this
commit I would see failures on may tests that made inferior calls
using floating point arguments, after this commit, all of these issues
are resolved. One example from the testsuite is
gdb.base/infcall-nested-structs.exp.
gdb/ChangeLog:
* riscv-tdep.c (riscv_features_from_gdbarch_info): New function.
(riscv_find_default_target_description): Use new function to
extract feature from gdbarch_info.
(riscv_gdbarch_init): Add error checks for xlen and flen between
target description and bfd headers. Be smarter about when we
think the hardware floating point abi should be used.
Add '==' and '!=' operators for the struct riscv_gdb_features,
allowing a small simplification.
gdb/ChangeLog:
* arch/riscv.h (riscv_gdb_features::operator==): New.
(riscv_gdb_features::operator!=): New.
* riscv-tdep.c (riscv_gdbarch_init): Make use of the inequality
operator.
Makes more of the interface related to fetching target descriptions
constant.
gdb/ChangeLog:
* arch/riscv.h (riscv_create_target_description): Make return type
const.
* arch/riscv.c (riscv_create_target_description): Likewise.
* riscv-tdep.c (riscv_find_default_target_description): Likewise.
This commit adds target description support for riscv.
I've used the split feature approach for specifying the architectural
features, and the CSR feature is auto-generated from the riscv-opc.h
header file.
If the target doesn't provide a suitable target description then GDB
will build one by looking at the bfd headers.
This commit does not implement target description creation for the
Linux or FreeBSD native targets, both of these will need to add
read_description methods into their respective target classes, which
probe the target features, and then call
riscv_create_target_description to build a suitable target
description. Until this is done Linux and FreeBSD will get the same
default target description based on the bfd that bare-metal targets
get.
I've only added feature descriptions for 32 and 64 bit registers, 128
bit registers (for RISC-V) are not supported in the reset of GDB yet.
This commit removes the special reading of the MISA register in order
to establish the target features, this was only used for figuring out
the f-register size, and even that wasn't done consistently. We now
rely on the target to tell us what size of registers it has (or look
in the BFD as a last resort). The result of this is that we should
now support RV64 targets with 32-bit float, though I have not
extensively tested this combination yet.
* Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o.
(HFILES_NO_SRCDIR): Add arch/riscv.h.
* arch/riscv.c: New file.
* arch/riscv.h: New file.
* configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into
this list, and add arch/riscv.o.
* features/Makefile: Add riscv features.
* features/riscv/32bit-cpu.c: New file.
* features/riscv/32bit-cpu.xml: New file.
* features/riscv/32bit-csr.c: New file.
* features/riscv/32bit-csr.xml: New file.
* features/riscv/32bit-fpu.c: New file.
* features/riscv/32bit-fpu.xml: New file.
* features/riscv/64bit-cpu.c: New file.
* features/riscv/64bit-cpu.xml: New file.
* features/riscv/64bit-csr.c: New file.
* features/riscv/64bit-csr.xml: New file.
* features/riscv/64bit-fpu.c: New file.
* features/riscv/64bit-fpu.xml: New file.
* features/riscv/rebuild-csr-xml.sh: New file.
* riscv-tdep.c: Add 'arch/riscv.h' include.
(riscv_gdb_reg_names): Delete.
(csr_reggroup): New global.
(struct riscv_register_alias): Delete.
(struct riscv_register_feature): New structure.
(riscv_register_aliases): Delete.
(riscv_xreg_feature): New global.
(riscv_freg_feature): New global.
(riscv_virtual_feature): New global.
(riscv_csr_feature): New global.
(riscv_create_csr_aliases): New function.
(riscv_read_misa_reg): Delete.
(riscv_has_feature): Delete.
(riscv_isa_xlen): Simplify, just return cached xlen.
(riscv_isa_flen): Simplify, just return cached flen.
(riscv_has_fp_abi): Update for changes in struct gdbarch_tdep.
(riscv_register_name): Update to make use of tdesc_register_name.
Look up xreg and freg names in the new globals riscv_xreg_feature
and riscv_freg_feature. Don't supply csr aliases here.
(riscv_fpreg_q_type): Delete.
(riscv_register_type): Use tdesc_register_type in almost all
cases, override the returned type in a few specific cases only.
(riscv_print_one_register_info): Handle errors reading registers.
(riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for
registers that are otherwise unknown to GDB. Also check the
csr_reggroup.
(riscv_print_registers_info): Remove assert about upper register
number, and use gdbarch_register_reggroup_p instead of
short-cutting.
(riscv_find_default_target_description): New function.
(riscv_check_tdesc_feature): New function.
(riscv_add_reggroups): New function.
(riscv_setup_register_aliases): New function.
(riscv_init_reggroups): New function.
(_initialize_riscv_tdep): Add calls to setup CSR aliases, and
setup register groups. Register new riscv debug variable.
* riscv-tdep.h: Add 'arch/riscv.h' include.
(struct gdbarch_tdep): Remove abi union, and add
riscv_gdbarch_features field. Remove cached quad floating point
type, and provide initialisation for double type field.
* target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to
the list of targets using the feature based target descriptions.
* NEWS: Mention target description support.
gdb/doc/ChangeLog:
* gdb.texinfo (Standard Target Features): Add RISC-V Features
sub-section.
For riscv64-linux target, second half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
Unnamed arguments with 2*XLEN alignment are passed in aligned register pairs.
gdb/
* riscv-tdep.c (struct riscv_arg_info): New field is_unnamed.
(riscv_call_arg_scalar_int): If unnamed arg with twice xlen alignment,
then increment next_regnum if odd.
(riscv_arg_location): New arg is_unnamed. Set ainfo->is_unnamed.
(riscv_push_dummy_call): New local ftype. Call check_typedef to set
function type. Pass new arg to riscv_arg_location based on function
type.
(riscv_return_value): Pass new arg to riscv_arg_location.
For riscv64-linux target, first half of fix for
FAIL: gdb.base/gnu_vector.exp: call add_various_floatvecs
GCC gives vectors natural aligment based on total size, not element size,
bounded by the maximum supported type alignment.
gdb/
* riscv-tdep.c (BIGGEST_ALIGNMENT): New.
(riscv_type_alignment) <TYPE_CODE_ARRAY>: If TYPE_VECTOR, return min
of TYPE_LENGTH and BIGGEST_ALIGNMENT.
For riscv64-linux target, fixes
FAIL: gdb.base/gnu_vector.exp: call add_many_charvecs
Ensure that stack slots are always the same alignment as XLEN by rounding
up arg align to xlen.
gdb/
* riscv-tdep.c (riscv_call_arg_scalar_int): Use std::min when
setting len. New local align, set to max of arg align and xlen,
and pass to first riscv_assign_stack_location call.
When we connect to a remote target one of the first things GDB does is
establish a frame id. If an error is thrown while building this frame
id then GDB will disconnect from the target.
This can mean that, if the user is attempting to connect to a target
that doesn't yet have a program loaded, or the program the user is
going to load onto the target doesn't match what is already loaded, or
the target is just in some undefined state, then the very first
request for a frame id can fail (for example, by trying to load from
an invalid memory address), and GDB will disconnect. It is then
impossible for the user to connect to the target and load a new
program at all.
An example of such a session might look like this:
Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases...
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
Cannot access memory at address 0x0
(gdb) load
You can't do that when your target is `exec'
(gdb) info frame
/path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed.
A problem internal to GDB has been detected,
further debugging may prove unreliable.
Quit this debugging session? (y or n)
The solution is to handle errors in riscv_frame_this_id, and leave the
this_id variable with its default value, which is the predefined
'outermost' frame.
With this fix in place, connecting to the same target now looks like
this:
(gdb) target remote :37191
Remote debugging using :37191
0x0000000000000100 in ?? ()
(gdb) info frame
Stack level 0, frame at 0x0:
pc = 0x100; saved pc = <not saved>
Outermost frame: outermost
Arglist at unknown address.
Locals at unknown address, Previous frame's sp in sp
gdb/ChangeLog:
* riscv-tdep.c (riscv_insn::decode): Update header comment.
(riscv_frame_this_id): Catch errors thrown while building the
frame cache, leave the frame id as the default, which is the outer
frame id.
Some hardware doesn't support unaligned accesses, and a bare metal target
may not have an unaligned access trap handler. So if the PC is 2-byte
aligned, then use a 2-byte breakpoint to avoid unaligned accesses.
Tested on native RV64GC Linux with gdb testsuite and cross on spike
simulator and openocd with riscv-tests/debug.
gdb/
* riscv-tdep.c (riscv_breakpoint_kind_from_pc): New local unaligned_p.
Set if pcptr if unaligned. Return 2 if unaligned_p true. Update
debugging messages.
Make riscv_isa_flen available to the linux native code, and clean up duplicate
comments.
gdb/
* riscv-tdep.c (riscv_isa_xlen): Refer to riscv-tdep.h comment.
(riscv_isa_flen): Likewise. Drop static.
* riscv-tdep.h (riscv_isa_xlen): Move riscv-tdep.c comment to here.
(riscv_isa_flen): Likewise.
When reading the MISA register, the RISC-V specification says that, if
MISA can't be found then a default value of 0 should be assumed.
As such, this patch ensures that GDB ignores errors when accessing
both the new and old locations for the MISA register.
Additionally, this patch removes an unneeded flag parameter which
didn't provide any additional functionality beyond checking the MISA
for the default value of 0.
gdb/ChangeLog:
* riscv-tdep.c (riscv_read_misa_reg): Update comment, remove
READ_P parameter, catch and ignore register access errors from
either the old or new MISA location.
(riscv_has_feature): Update call to riscv_read_misa_reg.
The recent commit:
commit 0dbfcfffe9abbc5198bce95eb8c66b6bc9b364be
Date: Tue Oct 16 22:40:09 2018 +0100
gdb/riscv: Fix register access for register aliases
broke the CSR names for RISC-V, now all of the CSRs have names like,
csr0, csr1, csr2, etc. This commit restores the previous
user-friendly names.
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_name): Use the user-friendly names
for CSRs.
When using QEMU as a RISCV simulator, hardware watchpoint events are
reported to GDB before the target memory gets written. GDB currently
expects the event to be reported after it is written. As a result of
this mismatch, upon receiving the event, GDB sees that the target
memory region has not changed, and therefore decides to ignore the
event. It therefore resumes the program's execution with a continue,
which is the start of an infinite loop between QEMU repeatedly
reporting the same watchpoint event over and over, and GDB repeatedly
ignoring it.
This patch fixes the issue by telling GDB to expect the watchpoint
event to be reported ahead of the memory region being modified.
Upon receiving the event, GDB then single-steps the program before
checking the watched memory value.
gdb/ChangeLog:
* riscv-tdep.c (riscv_gdbarch_init): Set the gdbarch's
have_nonsteppable_watchpoint attribute to 1.
Some confusion over how the register names and aliases are setup in
riscv means that we currently can't access registers through their
architectural name.
This commit fixes this issue, and moves some of the csr register
handling out of the alias handling code and deals with it separately.
This has the benefit that we can now directly access some arrays
rather than having to iterate over them.
A new test is added to ensure that register aliases now work
correctly.
gdb/ChangeLog:
* riscv-tdep.c (riscv_gdb_reg_names): Update comment, and all
register names.
(struct register_alias): Rename to...
(struct riscv_register_alias): ...this, and update comment.
(riscv_register_aliases): Update type, and alias names. Remove
CSR names from this list.
(riscv_register_name): Use riscv_gdb_reg_names for int and float
register names. Add an extra assertion.
(riscv_is_regnum_a_named_csr): New function.
(riscv_register_reggroup_p): Use riscv_is_regnum_a_named_csr.
gdb/testsuite/ChangeLog:
* gdb.arch/riscv-reg-aliases.c: New file.
* gdb.arch/riscv-reg-aliases.exp: New file.
The hardware requires that values in FP registers be NaN-boxed, so we must
extend them with 1's instead of 0's as we do for integer values.
gdb/
* riscv-tdep.c (riscv_push_dummy_call) <in_reg>: Check for value in
FP reg smaller than FP reg size, and fill with -1 instead of 0.
A 64-bit FP register can hold either a single or double float value, so
print it as both types by using a union type for FP registers. Likewise
for 128-bit regs which can also hold long double.
gdb/
* riscv-tdep.c (riscv_fpreg_d_type, riscv_fpreg_q_type): New.
(riscv_register_type): Use them.
(riscv_print_one_register_info): Handle union of floats same as float.
* riscv-tdep.h (struct gdbarch_tdep): Add riscv_fpreg_d_type and
riscv_fpreg_q_type fields.
This fixes all the straightforward -Wshadow=local warnings in gdb. A
few standard approaches are used here:
* Renaming an inner (or outer, but more commonly inner) variable;
* Lowering a declaration to avoid a clash;
* Moving a declaration into a more inner scope to avoid a clash,
including the special case of moving a declaration into a loop header.
I did not consider any of the changes in this patch to be particularly
noteworthy, though of course they should all still be examined.
gdb/ChangeLog
2018-10-04 Tom Tromey <tom@tromey.com>
* ctf.c (SET_ARRAY_FIELD): Rename "u32".
* p-valprint.c (pascal_val_print): Split inner "i" variable.
* xtensa-tdep.c (xtensa_push_dummy_call): Declare "i" in loop
header.
* xstormy16-tdep.c (xstormy16_push_dummy_call): Declare "val" in
more inner scope.
* xcoffread.c (read_xcoff_symtab): Rename inner "symbol".
* varobj.c (varobj_update): Rename inner "newobj",
"type_changed".
* valprint.c (generic_emit_char): Rename inner "buf".
* valops.c (find_overload_match): Rename inner "temp".
(value_struct_elt_for_reference): Declare "v" in more inner
scope.
* v850-tdep.c (v850_push_dummy_call): Rename "len".
* unittests/array-view-selftests.c (run_tests): Rename inner
"vec".
* tui/tui-stack.c (tui_show_frame_info): Declare "i" in loop
header.
* tracepoint.c (merge_uploaded_trace_state_variables): Declare
"tsv" in more inner scope.
(print_one_static_tracepoint_marker): Rename inner
"tuple_emitter".
* tic6x-tdep.c (tic6x_analyze_prologue): Declare "inst" lower.
(tic6x_push_dummy_call): Don't redeclare "addr".
* target-float.c: Declare "dto" lower.
* symtab.c (lookup_local_symbol): Rename inner "sym".
(find_pc_sect_line): Rename inner "pc".
* stack.c (print_frame): Don't redeclare "gdbarch".
(return_command): Rename inner "gdbarch".
* s390-tdep.c (s390_prologue_frame_unwind_cache): Renam inner
"sp".
* rust-lang.c (rust_internal_print_type): Declare "i" in loop
header.
* rs6000-tdep.c (ppc_process_record): Rename inner "addr".
* riscv-tdep.c (riscv_push_dummy_call): Declare "info" in inner
scope.
* remote.c (remote_target::update_thread_list): Don't redeclare
"tp".
(remote_target::process_initial_stop_replies): Rename inner
"thread".
(remote_target::remote_parse_stop_reply): Don't redeclare "p".
(remote_target::wait_as): Don't redeclare "stop_reply".
(remote_target::get_thread_local_address): Rename inner
"result".
(remote_target::get_tib_address): Likewise.
RISC-V supports instructions of varying lengths. Standard existing
instructions in the base ISA are 4 bytes in length, but the 'C'
extension adds support for compressed, 2 byte instructions. RISC-V
supports two different breakpoint instructions: EBREAK is a 4 byte
instruction in the base ISA, and C.EBREAK is a 2 byte instruction only
available on processors implementing the 'C' extension. Using EBREAK
to set breakpoints on compressed instructions causes problems as the
second half of EBREAK will overwrite the first 2 bytes of the
following instruction breaking other threads in the process if their
PC is the following instruction. Thus, breakpoints on compressed
instructions need to use C.EBREAK instead of EBREAK.
Previously, the riscv architecture checked the MISA register to
determine if the 'C' extension was available. If so, it used C.EBREAK
for all breakpoints. However, the MISA register is not necessarily
available to supervisor mode operating systems. While native targets
could provide a fake MISA register value, this patch instead examines
the existing instruction at a breakpoint target to determine which
breakpoint instruction to use. If the existing instruction is a
compressed instruction, C.EBREAK is used, otherwise EBREAK is used.
gdb/ChangeLog:
* disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to
case with explicit breakpoint kind.
* riscv-tdep.c (show_use_compressed_breakpoints): Remove
'additional_info' and related logic.
(riscv_debug_breakpoints): New variable.
(riscv_breakpoint_kind_from_pc): Use the length of the existing
instruction to determine the breakpoint kind.
(_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints'
flag. Update description of 'set/show riscv
use-compressed-breakpoints' flag.
This commit improves the prologue scanning stack unwinder, to better
support AUIPC, LUI, and more variants of ADD and ADDI.
This allows unwinding over frames containing large local variables,
where the frame size does not fit into a single instruction immediate,
and is first loaded into a temporary register, before being added to
the stack pointer.
A new test is added that tests this behaviour. As there's nothing
truely RiscV specific about this test I've added it into gdb.base, but
as this depends on target specific code to perform the unwind it is
possible that some targets might fail this new test.
gdb/ChangeLog:
* riscv-tdep.c (riscv_insn::decode): Decode c.lui.
(riscv_scan_prologue): Split handling of AUIPC, LUI, ADD, ADDI,
and NOP.
gdb/testsuite/ChangeLog:
* gdb.base/large-frame-1.c: New file.
* gdb.base/large-frame-2.c: New file.
* gdb.base/large-frame.exp: New file.
* gdb.base/large-frame.h: New file.
This patch fixes an ARI violation in riscv-tdep.c (line ends with
'+').
gdb/ChangeLog:
* riscv-tdep.c (riscv_frame_cache): Fix ARI warning, don't end a
line with '+'.
Collects information during the prologue scan and uses this to unwind
registers when no DWARF information is available.
This patch has been tested by disabling the DWARF stack unwinders, and
running the complete GDB testsuite against a range of RISC-V targets.
The results are comparable to running with the DWARF unwinders in
place.
gdb/ChangeLog:
* riscv-tdep.c: Add 'prologue-value.h' include.
(struct riscv_unwind_cache): New struct.
(riscv_debug_unwinder): New global.
(riscv_scan_prologue): Update arguments, capture register details
from prologue scan.
(riscv_skip_prologue): Reformat arguments line, move end of
prologue calculation into riscv_scan_prologue.
(riscv_frame_cache): Update return type, create
riscv_unwind_cache, scan the prologue, and fill in remaining cache
details.
(riscv_frame_this_id): Use frame id computed in riscv_frame_cache.
(riscv_frame_prev_register): Use the trad_frame within the
riscv_unwind_cache.
(_initialize_riscv_tdep): Add 'set/show debug riscv unwinder'
flag.
Extends the instruction decoder used during prologue scan and software
single step to cover more instructions. These instructions are
encountered when running the current GDB testsuite with the DWARF
stack unwinders turned off.
gdb/ChangeLog:
* riscv-tdep.c (riscv_insn::decode): Decode c.addi4spn, c.sd,
c.sw, c.swsp, and c.sdsp.
The RISC-V had a mechanism in place to cache the contents of the misa
register per-inferior, the original intention behind this was to
reduce the number of times the misa register had to be read (as the
contents should be constant), but it was pointed out on the mailing
list[1] that the register cache will mean the register is only
accessed once each time GDB stops, and any additional caching is
probably just unneeded extra complexity.
As such, until it can be shown that there's a real need for additional
caching, this commit removes all of the additional caching of the misa
register, and just accesses the misa register like a normal register.
[1] https://sourceware.org/ml/gdb-patches/2018-03/msg00136.html
gdb/ChangeLog:
* riscv-tdep.c (struct riscv_inferior_data): Delete.
(riscv_read_misa_reg): Don't cache value read into inferior data.
(riscv_new_inferior_data): Delete.
(riscv_inferior_data_cleanup): Delete.
(riscv_inferior_data): Delete.
(riscv_invalidate_inferior_data): Delete.
(_initialize_riscv_tdep): Remove initialisation of inferior data.
This adds software single step support that is needed by the linux native port.
This is modeled after equivalent code in the MIPS port.
This also fixes a few bugs in the compressed instruction decode support. Some
instructions are RV32/RV64 specific, and this wasn't being checked. Also, a
few instructions were accidentally using the non-compressed is_* function.
This has been tested on a HiFive Unleashed running Fedora, by putting a
breakpoint on start, typing stepi, and then holding down the return key until
it finishes, and observing that I see everything I expect to see along the way.
There is a problem in _dl_addr where I get into an infinite loop, but it seems
to be some synchronization code that doesn't agree with single step, so I have
to find the end of the loop, put a breakpoint there, continue, and then single
step again until the end.
gdb/
* riscv-tdep.c (enum opcode): Add jump, branch, lr, and sc opcodes.
(decode_register_index_short): New.
(decode_j_type_insn, decode_cj_type_insn): New.
(decode_b_type_insn, decode_cb_type_insn): New.
(riscv_insn::decode): Add support for jumps, branches, lr, and sc. New
local xlen. Check xlen when decoding ambiguous compressed insns. In
compressed decode, use is_c_lui_insn instead of is_lui_insn, and
is_c_sw_insn instead of is_sw_insn.
(riscv_next_pc, riscv_next_pc_atomic_sequence): New.
(riscv_software_single_step): New.
* riscv-tdep.h (riscv_software_single_step): Declare.
This allows the function to be used from riscv OS files, which also need to
depend on XLEN size.
gdb/
* riscv-tdep.c (riscv_isa_xlen): Drop static.
* riscv-tdep.h (riscv_isa_xlen): Add extern declaration.
gdb/
* riscv-tdep.c (riscv_has_feature): Delete comment that refers to
set_gdbarch_decr_pc_after_break. Call riscv_read_misa_reg always.
(riscv_gdbarch_init): Delete local has_compressed_isa. Delete now
unecessary braces after EF_RISCV_RVC test. Delete call to
set_gdbarch_decr_pc_after_break.
An assertion when setting up arguments for an inferior call checks the
size of the argument against xlen. However, if xlen and flen are
different sizes, and the argument is being placed into a floating
pointer register then we should be comparing against flen not xlen.
This issue shows up as an assertion failure when running on an rv32g
target with a binary compiled using the rv32f abi and making an
inferior call involving large floating point arguments, for example
the test gdb.base/infcall-nested-structs.exp.
gdb/ChangeLog:
* riscv-tdep.c (riscv_is_fp_regno_p): New function.
(riscv_register_reggroup_p): Use new function, remove unneeded
parenthesis.
(riscv_push_dummy_call): Extend assert to compare against xlen or
flen based on register type.
In debug printing, use TYPE_SAFE_NAME instead of replicating the
functionality using TYPE_NAME and a null check.
gdb/ChangeLog:
* riscv-tdep.c (riscv_print_arg_location): Use TYPE_SAFE_NAME.
The "fp" register name is an alias for "s0" which is an alias for "x8".
The "fp" name is only understood by very recent Binutils and thus not
used by GCC. GCC does not emit a frame pointer with common optimization
options such as -Og or -O2.
It is still possible to use the "fp" register name, e.g.
(gdb) p/x $fp
$1 = 0x800367c8
works.
However, in the register dump you see now:
(gdb) info registers
...
t2 0xffffffffffffffff 18446744073709551615
s0 0x800367c8 0x800367c8
s1 0x80033280 2147693184
...
gdb/
* riscv-tdep.c (riscv_register_aliases): Swap "fp" and "s0"
entries.
This patch fixes the subset of -Wimplicit-fallthrough warnings that I
considered obvious. In most cases it was obvious from context that
falling through was desired; here I added the appropriate comment. In
a couple of cases it seemed clear that a "break" was missing.
ChangeLog
2018-05-04 Tom Tromey <tom@tromey.com>
* riscv-tdep.c (riscv_isa_xlen): Add fall-through comment.
* utils.c (can_dump_core) <LIMIT_CUR>: Add fall-through comment.
* eval.c (fetch_subexp_value) <MEMORY_ERROR>: Add fall-through
comment.
* d-valprint.c (d_val_print) <TYPE_CODE_STRUCT>: Add fall-through
comment.
* coffread.c (coff_symtab_read) <C_LABEL>: Add fall-through
comment.
This converts observers from using a special source-generating script
to be plain C++. This version of the patch takes advantage of C++11
by using std::function and variadic templates; incorporates Pedro's
patches; and renames the header file to "observable.h" (this change
eliminates the need for a clean rebuild).
Note that Pedro's patches used a template lambda in tui-hooks.c, but
this failed to compile on some buildbot instances (presumably due to
differing C++ versions); I replaced this with an ordinary template
function.
Regression tested on the buildbot.
gdb/ChangeLog
2018-03-19 Pedro Alves <palves@redhat.com>
Tom Tromey <tom@tromey.com>
* unittests/observable-selftests.c: New file.
* common/observable.h: New file.
* observable.h: New file.
* ada-lang.c, ada-tasks.c, agent.c, aix-thread.c, annotate.c,
arm-tdep.c, auto-load.c, auxv.c, break-catch-syscall.c,
breakpoint.c, bsd-uthread.c, cli/cli-interp.c, cli/cli-setshow.c,
corefile.c, dummy-frame.c, event-loop.c, event-top.c, exec.c,
extension.c, frame.c, gdbarch.c, guile/scm-breakpoint.c,
infcall.c, infcmd.c, inferior.c, inflow.c, infrun.c, jit.c,
linux-tdep.c, linux-thread-db.c, m68klinux-tdep.c,
mi/mi-cmd-break.c, mi/mi-interp.c, mi/mi-main.c, objfiles.c,
ppc-linux-nat.c, ppc-linux-tdep.c, printcmd.c, procfs.c,
python/py-breakpoint.c, python/py-finishbreakpoint.c,
python/py-inferior.c, python/py-unwind.c, ravenscar-thread.c,
record-btrace.c, record-full.c, record.c, regcache.c, remote.c,
riscv-tdep.c, sol-thread.c, solib-aix.c, solib-spu.c, solib.c,
spu-multiarch.c, spu-tdep.c, stack.c, symfile-mem.c, symfile.c,
symtab.c, thread.c, top.c, tracepoint.c, tui/tui-hooks.c,
tui/tui-interp.c, valops.c: Update all users.
* tui/tui-hooks.c (tui_bp_created_observer)
(tui_bp_deleted_observer, tui_bp_modified_observer)
(tui_inferior_exit_observer, tui_before_prompt_observer)
(tui_normal_stop_observer, tui_register_changed_observer):
Remove.
(tui_observers_token): New global.
(attach_or_detach, tui_attach_detach_observers): New functions.
(tui_install_hooks, tui_remove_hooks): Use
tui_attach_detach_observers.
* record-btrace.c (record_btrace_thread_observer): Remove.
(record_btrace_thread_observer_token): New global.
* observer.sh: Remove.
* observer.c: Rename to observable.c.
* observable.c (namespace gdb_observers): Define new objects.
(observer_debug): Move into gdb_observers namespace.
(struct observer, struct observer_list, xalloc_observer_list_node)
(xfree_observer_list_node, generic_observer_attach)
(generic_observer_detach, generic_observer_notify): Remove.
(_initialize_observer): Update.
Don't include observer.inc.
* Makefile.in (generated_files): Remove observer.h, observer.inc.
(clean mostlyclean): Likewise.
(observer.h, observer.inc): Remove targets.
(SUBDIR_UNITTESTS_SRCS): Add observable-selftests.c.
(COMMON_SFILES): Use observable.c, not observer.c.
* .gitignore: Remove observer.h.
gdb/doc/ChangeLog
2018-03-19 Tom Tromey <tom@tromey.com>
* observer.texi: Remove.
gdb/testsuite/ChangeLog
2018-03-19 Tom Tromey <tom@tromey.com>
* gdb.gdb/observer.exp: Remove.
Fix some ARI issues in recently added riscv code, the ARI email is:
https://sourceware.org/ml/gdb-patches/2018-03/msg00156.html
gdb/ChangeLog:
* riscv-tdep.c (riscv_sw_breakpoint_from_kind): Add localization
to error message string.
(riscv_register_name): Use xsnprintf instead of sprintf.
(riscv_insn::fetch_instruction): Use gdb_assert instead of
internal_error.
(riscv_print_arg_location): Use gdb_assert_not_reached instead of
error.
(riscv_push_dummy_call): Likewise.
Some parts of the target description support were committed with the
initial riscv patch. As target descriptions are not currently supported
on riscv this commit removes the two pieces for code that relate to
target description support.
It is expected that target description support will be added in the
future, at which point this, or similar code will be added back.
gdb/ChangeLog:
* riscv-tdep.c (riscv_register_name): Remove target description
support.
(riscv_gdbarch_init): Remove target description check.
The GDB coding standard states these lines should never have been
added.
gdb/ChangeLog:
* riscv-tdep.c: Remove 'Contributed by ...' lines from header
comment.
* riscv-tdep.h: Likewise.
The code making use of pseudo registers was initially intended to
support running 32-bit ABI files on 64-bit riscv targets. However, the
implementation was incomplete, and broken.
For now I've removed all reference to pseudo registers from the riscv
target, we've not lost any functionality, and this cleans up failures in
the selftests.
Once the riscv target has matured a little we'll probably end up
bringing back some of the use of pseudo registers in order to better
support running 32-bit executables on a 64-bit target.
gdb/ChangeLog:
* riscv-tdep.c (riscv_pseudo_register_read): Delete.
(riscv_pseudo_register_write): Delete.
(riscv_gdbarch_init): Remove all use of pseudo registers.
Should use a ULONGEST when reading from the regcache.
gdb/ChangeLog:
* riscv-tdep.c (riscv_return_value): Change type to ULONGEST for
reading values from registers.
Some of the format strings used in the new riscv target were incorrect,
resulting in build failures on some hosts. This commit does the
following:
1. Uses core_addr_to_string for formatting CORE_ADDR types.
2. Fixes legacy use of stderr for logging in one place that got
missed, instead gdb_stdlog is used.
3. Re-indent a few printf related lines that were wrong.
This should resolve some (but not all) of the build failures the new
riscv target introduced.
gdb/ChangeLog:
* riscv-tdep.c (riscv_print_arg_location): Add header comment,
change parameter type. Use GDB's print functions, and use
core_addr_to_string where appropriate.
(riscv_push_dummy_call): Use core_addr_to_string where
appropriate, update call to riscv_print_arg_location, and reindent
a few lines.
(riscv_return_value): Update call to riscv_print_arg_location.
This commit introduces basic support for baremetal RiscV as a GDB
target. This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit. The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.
Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.
The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing. The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature. As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.
gdb/ChangeLog:
* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
(HFILES_NO_SRCDIR): Add riscv-tdep.h.
(ALLDEPFILES): Add riscv-tdep.c
* configure.tgt: Add riscv support.
* riscv-tdep.c: New file.
* riscv-tdep.h: New file.
* NEWS: Mention new target.
* MAINTAINERS: Add entry for riscv.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: New file.
* gdb.base/infcall-nested-structs.c: New file.
* gdb.base/float.exp: Add riscv support.
