OpenE2K/binutils-gdb
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813 Commits

Author SHA1 Message Date
Andrew Cagney
3a8e858f24 Add test for dbt/rtd instructions 1997-06-27 08:33:16 +00:00
Jeff Law
d05b86b7fb * interp.c (sim_resume): Clear State.exited. 
(sim_stop_reason): If State.exited is nonzero, then indicate that
        the simulator exited instead of stopped.
        * mn10300_sim.h (struct _state): Add exited field.
        * simops.c (syscall): Set State.exited for SYS_exit.

Fixes problem found bin Felix.
 1997-06-24 19:45:17 +00:00
Jeff Law
c370b3cd95 * simops.c: Fix thinko in last change. 1997-06-12 04:14:42 +00:00
Jeff Law
dbdb5bd881 * simops.c: "call" stores the callee saved registers into the 
stack!  Update the stack pointer properly when done with
        register saves.
 1997-06-10 22:59:13 +00:00
Jeff Law
0a8fa63cb8 * simops.c: Fix return address computation for "call" instructions. 1997-06-10 18:32:40 +00:00
Andrew Cagney
84e8cd0fcf Open in binary mode when available. 1997-06-06 02:34:55 +00:00
Andrew Cagney
0bdfae1167 Clean up formatting of instruction traces. 1997-06-06 00:31:08 +00:00
Andrew Cagney
897f67b74f Verify magic number of simulator struct. 1997-06-05 04:51:34 +00:00
Andrew Cagney
896eab009e Initialize the sim-engine module. 1997-06-04 02:47:49 +00:00
Andrew Cagney
56e7c84918 o Fixes to repeated watchpoints 
o	Add mips ISA instructions needed to handle interrupts
 1997-06-03 23:03:50 +00:00
Andrew Cagney
c7cebfa32c o Fix padd insn 
o	Take an interrupt when an int event occures.
 1997-06-02 15:00:43 +00:00
Andrew Cagney
128b51546e Add assembler information to igen input files. 1997-05-30 07:25:13 +00:00
Andrew Cagney
4e95b94e1e Fix subu immed - was incorrectly using unsigned. 1997-05-29 07:25:20 +00:00
Andrew Cagney
efe4f1cbf8 Add a simple dissasembler to igen 1997-05-29 07:06:41 +00:00
Andrew Cagney
1a70e182aa Fix watching PC for 64bit (mips) target. 
Stop watchpoints corrupting the event queue.
 1997-05-27 11:25:47 +00:00
Andrew Cagney
2f2e6c5d5b Extend xor-endian and per-cpu support in core module. 
Allow negated test when watching value within core.
 1997-05-27 06:48:20 +00:00
Andrew Cagney
cd0d873d0f Preliminary suport for xor-endian suport in core module. 1997-05-23 09:19:43 +00:00
Andrew Cagney
b526378484 Incorrect test for zero-r0 code gen. 1997-05-23 02:01:04 +00:00
Andrew Cagney
8167e102a5 Enumerate longjmp's return type. 1997-05-23 01:29:16 +00:00
Gavin Romig-Koch
d3d2a9f718 ifdef out uses of simSTOP, simSTEP and simBE when DEBUG is defined. 1997-05-22 13:30:01 +00:00
Gavin Romig-Koch
6e61ecfc92 Change longjmp param/setjmp return value used for simulator restart from 0 to 2. 1997-05-22 13:16:03 +00:00
Jeff Law
09e142d5a2 * interp.c (sim_resume): Add missing case in big switch 
statement (for extb instruction).
 1997-05-22 05:28:34 +00:00
Andrew Cagney
50a2a69182 Watchpoint interface. 1997-05-21 06:54:13 +00:00
Jeff Law
003c91bec4 * interp.c: Replace all references to load_mem and store_mem 
with references to load_byte, load_half, load_3_byte, load_word
        and store_byte, store_half, store_3_byte, store_word.
        (INLINE): Delete definition.
        (load_mem_big): Likewise.
        (max_mem): Make it global.
        (dispatch): Make this function inline.
        (load_mem, store_mem): Delete functions.
        * mn10300_sim.h (INLINE): Define.
        (RLW): Delete unused definition.
        (load_mem, store_mem): Delete declarations.
        (load_mem_big): New definition.
        (load_byte, load_half, load_3_byte, load_word): New functions.
        (store_byte, store_half, store_3_byte, store_word): New functions.
        * simops.c:  Replace all references to load_mem and store_mem
        with references to load_byte, load_half, load_3_byte, load_word
        and store_byte, store_half, store_3_byte, store_word.
 1997-05-20 23:53:47 +00:00
Andrew Cagney
ff82f21409 Part II of adding callback argument to sim_open(). Update all the 
other simulators; remove SIM_DESC from depreciated function
sim_set_callbacks().
 1997-05-20 01:57:43 +00:00
Andrew Cagney
24aa2b57af Depreciate sim_set_callbacks() function. Set simulator callbacks 
during sim_open().
 1997-05-20 00:05:27 +00:00
Michael Meissner
8c5b6ead7d Make getpid, kill supported system calls 1997-05-19 23:02:30 +00:00
Jeff Law
4df7aeb3c5 * interp.c (dispatch): Make this an inline function. 
* simops.c (syscall): Use callback->write regardless of
        what file descriptor we're writing too.
 1997-05-19 19:55:31 +00:00
Andrew Cagney
2e61a3ad9c Graft sim/common event and other code onto the mips simulator. 1997-05-19 13:30:30 +00:00
Andrew Cagney
ba2374064d Update. 1997-05-19 09:35:51 +00:00
Andrew Cagney
fd76456bdb Make simulator event-queue manager a bit more signal safe. 1997-05-19 06:55:56 +00:00
Andrew Cagney
f03b093cd3 o Implement generic halt/restart/abort module. 
Use in tic80 and d30v simulators.
o	Add signal hook to sim-core module
 1997-05-19 03:42:33 +00:00
Andrew Cagney
11ab132f16 Pacify gcc. 1997-05-19 01:24:31 +00:00
Jeff Law
b07a1e78c5 * interp.c (load_mem_big): Remove function. It's now a macro 
defined elsewhere.
        (compare_simops): New function.
        (sim_open): Sort the Simops table before inserting entries
        into the hash table.
        * mn10300_sim.h: Remove unused #defines.
        (load_mem_big): Define.
Another 20% so performance improvement for the mn10300 simulator.
 1997-05-18 22:57:49 +00:00
Michael Meissner
63aa80ff51 Treat infinities like normal numbers for purposes of comparisons 1997-05-17 02:28:11 +00:00
Jeff Law
248c1fb830 * callback.c (os_close): Mark the descriptor as being 
available if the close succeeded.
        (os_open): Pass 0644 as the mode of the file being created.
Bring Bob's changes over from the mec branch.
 1997-05-16 22:39:08 +00:00
Jeff Law
234a9a49cf * interp.c (load_mem): If we get a load from an out of range 
address, abort.
        (store_mem): Likewise for stores.
        (max_mem): New variable.
 1997-05-16 22:37:02 +00:00
Andrew Cagney
37a684b84d o Make tic80 insn file more `cache ready' 
o	Have igen always zero r0 instead of constantly checking if
	the designated register is r0.
 1997-05-16 03:27:40 +00:00
Andrew Cagney
07b4c0a66c Remove some of the flake from the c80 floating point. 1997-05-15 16:39:38 +00:00
Andrew Cagney
d24f06eef2 More floating point operations. 1997-05-15 02:22:37 +00:00
Andrew Cagney
aa3a044769 Fix double conversion problem. 1997-05-15 02:21:11 +00:00
Andrew Cagney
2310e3c2b5 Passify gcc's warnings. 1997-05-15 00:14:33 +00:00
Michael Meissner
93555c3b02 Make columns line up for fpu operation tracing 1997-05-14 22:06:45 +00:00
Michael Meissner
1b6f4dde35 Make sure r0 == 0; Return EINVAL for system calls that are defined but not provided; Provide traps 74-79 as debugging traps 1997-05-13 22:04:32 +00:00
Andrew Cagney
8490235019 Remove ANNULed cycle - was confusing gdb. 1997-05-13 13:57:49 +00:00
Michael Meissner
d01082ada2 Fix ld/st tracing 1997-05-12 21:16:26 +00:00
Andrew Cagney
9af5dcea8f Clear cntrl-c after handling it. 1997-05-12 08:33:56 +00:00
Andrew Cagney
c445af5a2b c80 simulator fixes. 1997-05-12 04:57:49 +00:00
Andrew Cagney
e05e76e8a4 Match commands like `(gdb) sim a b c' against options --a-b-c. 1997-05-12 04:30:38 +00:00
Michael Meissner
8ad6078850 Fix endian problems with ld.d/st.d 1997-05-12 02:04:02 +00:00