Commit Graph

127 Commits

Author SHA1 Message Date
Richard Henderson
07f5f4c683 or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns
Also fix the incorrect definitions of multiply and divide carry and
overflow float.

Changes to the instructions are made in the .cpu file, then we
regenerate the binutils and sim files.

The changes also required a few fixups for tests and additional sim helpers.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU.
	(insn-opcode-alu-regreg): Add opcodes for MULD and MULDU.
	(l-mul): Fix overflow support and indentation.
	(l-mulu): Fix overflow support and indentation.
	(l-muld, l-muldu, l-msbu, l-macu): New instructions.
	(l-div); Remove incorrect carry behavior.
	(l-divu): Fix carry and overflow behavior.
	(l-mac): Add overflow support.
	(l-msb, l-msbu): Add carry and overflow support.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* or1k-desc.c: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.c: Regenerate.
	* or1k-opc.h: Regenerate.
	* or1k-opinst.c: Regenerate.

sim/common/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* cgen-ops.h (ADDCFDI): New function, add carry flag DI variant.
	(ADDOFDI): New function, add overflow flag DI variant.
	(SUBCFDI): New function, subtract carry flag DI variant.
	(SUBOFDI): New function, subtract overflow flag DI variant.

sim/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* or1k/cpu.h: Regenerate.
	* or1k/decode.c: Regenerate.
	* or1k/decode.h: Regenerate.
	* or1k/model.c: Regenerate.
	* or1k/sem-switch.c: Regenerate.
	* or1k/sem.c: Regenerate:

sim/testsuite/sim/or1k/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* div.S: Fix tests to match correct overflow/carry semantics.
	* mul.S: Likewise.

gas/ChangeLog:

yyyy-mm-dd  Stafford Horne  <shorne@gmail.com>

	* testsuite/gas/or1k/allinsn.s: Add instruction tests for
	l.muld, l.muldu, l.macu, l.msb, l.msbu.
	* testsuite/gas/or1k/allinsn.d: Add test results for new
	instructions.
2018-10-05 11:41:42 +09:00
Stafford Horne
c8e98e3692 or1k: Add the l.adrp insn and supporting relocations
This patch adds the new instruction and relocation as per proposal:
   https://openrisc.io/proposals/ladrp

This is to be added to the spec in an upcoming revision.  The new instruction
l.adrp loads the page offset of the current instruction offset by
a 21-bit immediate shifted left 13-bits.  This is meant to be used with
a 13-bit lower bit page offset.  This allows us to free up the got
register r16.

  l.adrp  r3, foo
  l.ori   r4, r3, po(foo)
  l.lbz   r5, po(foo)(r3)
  l.sb    po(foo)(r3), r6

The relocations we add are:

 - BFD_RELOC_OR1K_PLTA26	For PLT jump relocation with PLT entry
   asm: plta()			implemented using l.ardp, meaning
				no need for r16 (the GOT reg)

 - BFD_RELOC_OR1K_GOT_PG21	Upper 21-bit Page offset got address
   asm: got()
 - BFD_RELOC_OR1K_TLS_GD_PG21	Upper 21-bit Page offset with TLS General
   asm: tlsgd()			Dynamic calculation
 - BFD_RELOC_OR1K_TLS_LDM_PG21	Upper 21-bit Page offset with TLS local
   asm: tlsldm()		dynamic calculation
 - BFD_RELOC_OR1K_TLS_IE_PG21	Upper 21-bit Page offset with TLS Initial
   asm: gottp() 		Executable calculation
 - BFD_RELOC_OR1K_PCREL_PG21	Default relocation for disp21 (l.adrp
				instructions)

 - BFD_RELOC_OR1K_LO13		low 13-bit page offset relocation
   asm: po()			i.e. mem loads, addi etc
 - BFD_RELOC_OR1K_SLO13		low 13-bit page offset relocation
   asm: po()			i.e. mem stores, with split immediate
 - BFD_RELOC_OR1K_GOT_LO13,	low 13-bit page offset with GOT calcs
   asm: gotpo()
 - BFD_RELOC_OR1K_TLS_GD_LO13	Lower 13-bit offset with TLS GD calcs
   asm: tlsgdpo()
 - BFD_RELOC_OR1K_TLS_LDM_LO13	Lower 13-bit offset with TLS LD calcs
   asm: tlsldmpo()
 - BFD_RELOC_OR1K_TLS_IE_LO13	Lower 13-bit offset with TLS IE calcs
   asm: gottppo()

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c: (or1k_elf_howto_table): Fix formatting for
	R_OR1K_PLT26, Add R_OR1K_PCREL_PG21, R_OR1K_GOT_PG21,
	R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21, R_OR1K_TLS_IE_PG21,
	R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13,
	R_OR1K_TLS_IE_LO13, R_OR1K_SLO13, R_OR1K_PLTA26.
	(or1k_reloc_map): Add BFD_RELOC_OR1K_PCREL_PG21,
	BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_LDM_PG21, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_LO13, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_GD_LO13,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_PLTA26.
	(elf_or1k_link_hash_table): Add field saw_plta.
	(or1k_final_link_relocate): Add value calculations for new relocations.
	(or1k_elf_relocate_section): Add section relocations for new
	relocations.
	(or1k_write_plt_entry): New function.
	(or1k_elf_finish_dynamic_sections): Add support for PLTA relocations
	using new l.adrp instruction.  Cleanup PLT relocation code generation.
	* libbfd.h: Regenerated.
	* reloc.c: Add BFD_RELOC_OR1K_PCREL_PG21, BFD_RELOC_OR1K_LO13,
	BFD_RELOC_OR1K_SLO13, BFD_RELOC_OR1K_GOT_PG21, BFD_RELOC_OR1K_GOT_LO13,
	BFD_RELOC_OR1K_PLTA26, BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc (parse_disp26): Add support for plta() relocations.
	(parse_disp21): New function.
	(or1k_rclass): New enum.
	(or1k_rtype): New enum.
	(or1k_imm16_relocs): Define new PO and SPO relocation mappings.
	(parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations.
	(parse_imm16): Add support for the new 21bit and 13bit relocations.
	* or1korbis.cpu (f-disp26): Don't assume SI.
	(f-disp21): New pc-relative 21-bit 13 shifted to right.
	(insn-opcode): Add ADRP.
	(l-adrp): New instruction.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* config/tc-or1k.c (or1k_apply_fix): Add BFD_RELOC_OR1K_TLS_GD_PG21,
	BFD_RELOC_OR1K_TLS_GD_LO13, BFD_RELOC_OR1K_TLS_LDM_PG21,
	BFD_RELOC_OR1K_TLS_LDM_LO13, BFD_RELOC_OR1K_TLS_IE_PG21,
	BFD_RELOC_OR1K_TLS_IE_LO13.
	* testsuite/gas/or1k/allinsn.s: Add test for l.adrp.
	* testsuite/gas/or1k/allinsn.d: Add test results for new
	instructions.
	* testsuite/gas/or1k/reloc-1.s: Add tests to generate
	R_OR1K_PLTA26, R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13, R_OR1K_TLS_GD_LO13,
	R_OR1K_TLD_LDM_LO13, R_OR1K_TLS_IE_LO13, R_OR1K_LO13, R_OR1K_SLO13
	relocations.
	* testsuite/gas/or1k/reloc-1.d: Add relocation results for
	tests.
	* testsuite/gas/or1k/reloc-2.s: Add negative tests for store to
	gotpo().
	* testsuite/gas/or1k/reloc-2.l: Add expected error test results.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/or1k.exp: Add test cases for plt generation.
	* testsuite/ld-or1k/plt1.dd: New file.
	* testsuite/ld-or1k/plt1.s: New file.
	* testsuite/ld-or1k/plt1.x.dd: New file.
	* testsuite/ld-or1k/plta1.dd: New file.
	* testsuite/ld-or1k/plta1.s: New file.
	* testsuite/ld-or1k/pltlib.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
	R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
	R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
	R_OR1K_SLO13, R_OR1K_PLTA26.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerated.
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Regenerated.
	* or1k-dis.c: Regenerated.
	* or1k-ibld.c: Regenerated.
	* or1k-opc.c: Regenerated.
	* or1k-opc.h: Regenerated.
	* or1k-opinst.c: Regenerated.
2018-10-05 11:41:41 +09:00
Richard Henderson
1c4f3780f7 or1k: Add relocations for high-signed and low-stores
This patch adds the following target relocations:

 - BFD_RELOC_HI16_S		High 16-bit relocation, for used with signed
   asm: ha()			lower.
 - BFD_RELOC_HI16_S_GOTOFF	High 16-bit GOT offset relocation for local
   asm: gotoffha()		symbols, for use with signed lower.
 - BFD_RELOC_OR1K_TLS_IE_AHI16	High 16-bit TLS relocation with initial
   asm: gottpoffha()		executable calculation, for use with signed
				lower.
 - BFD_RELOC_OR1K_TLS_LE_AHI16	High 16-bit TLS relocation for local executable
   asm: tpoffha()		variables, for use with signed lower.

 - BFD_RELOC_OR1K_SLO16		Split lower 16-bit relocation, used with
   asm: lo()			OpenRISC store instructions.
 - BFD_RELOC_OR1K_GOTOFF_SLO16	Split lower 16-bit GOT offset relocation for
   asm: gotofflo()		local symbols, used with OpenRISC store
				instructions.
 - BFD_RELOC_OR1K_TLS_LE_SLO16	Split lower 16-bit relocation for TLS local
   asm: tpofflo()		executable variables, used with OpenRISC store
				instructions.

bfd/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>
	    Stafford Horne  <shorne@gmail.com>

	* bfd-in2.h: Regenerated.
	* elf32-or1k.c (N_ONES): New macro.
	(or1k_elf_howto_table): Fix R_OR1K_PLT26 to complain on overflow.
	Add definitions for R_OR1K_TLS_TPOFF, R_OR1K_TLS_DTPOFF,
	R_OR1K_TLS_DTPMOD, R_OR1K_AHI16, R_OR1K_GOTOFF_AHI16,
	R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16, R_OR1K_SLO16,
	R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
	(or1k_reloc_map): Add entries for BFD_RELOC_HI16_S,
	BFD_RELOC_LO16_GOTOFF, BFD_RELOC_HI16_GOTOFF, BFD_RELOC_HI16_S_GOTOFF,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_SLO16, BFD_RELOC_OR1K_GOTOFF_SLO16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.
	(or1k_reloc_type_lookup): Change search loop to start ad index 0 and
	also check results before returning.
	(or1k_reloc_name_lookup): Simplify loop to use R_OR1K_max as index
	limit.
	(or1k_final_link_relocate): New function.
	(or1k_elf_relocate_section): Add support for new AHI and SLO
	relocations.  Use or1k_final_link_relocate instead of generic
	_bfd_final_link_relocate.
	(or1k_elf_check_relocs): Add support for new AHI and SLO relocations.
	* reloc.c: Add new enums for BFD_RELOC_OR1K_SLO16,
	BFD_RELOC_OR1K_GOTOFF_SLO16, BFD_RELOC_OR1K_TLS_IE_AHI16,
	BFD_RELOC_OR1K_TLS_IE_AHI16, BFD_RELOC_OR1K_TLS_LE_AHI16,
	BFD_RELOC_OR1K_TLS_LE_SLO16.  Remove unused BFD_RELOC_OR1K_GOTOFF_HI16
	and BFD_RELOC_OR1K_GOTOFF_LO16.
	* libbfd.h: Regenerated.

cpu/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k.opc: Add RTYPE_ enum.
	(INVALID_STORE_RELOC): New string.
	(or1k_imm16_relocs): New array array.
	(parse_reloc): New static function that just does the parsing.
	(parse_imm16): New static function for generic parsing.
	(parse_simm16): Change to just call parse_imm16.
	(parse_simm16_split): New function.
	(parse_uimm16): Change to call parse_imm16.
	(parse_uimm16_split): New function.
	* or1korbis.cpu (simm16-split): Change to use new simm16_split.
	(uimm16-split): Change to use new uimm16_split.

gas/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/gas/or1k/allinsn.d (l_ha): Add result for ha() relocation.
	* testsuite/gas/or1k/allinsn.s (l_ha): Add test for ha() relocations.
	* testsuite/gas/or1k/allinsn.exp: Renamed to or1k.exp.
	* testsuite/gas/or1k/or1k.exp: Add reloc-2 list test.
	* testsuite/gas/or1k/reloc-1.d: New file.
	* testsuite/gas/or1k/reloc-1.s: New file.
	* testsuite/gas/or1k/reloc-2.l: New file.
	* testsuite/gas/or1k/reloc-2.s: New file.

include/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
	R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
	R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.

ld/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* testsuite/ld-or1k/offsets1.d: New file.
	* testsuite/ld-or1k/offsets1.s: New file.
	* testsuite/ld-or1k/or1k.exp: New file.

opcodes/ChangeLog:

yyyy-mm-dd  Richard Henderson  <rth@twiddle.net>

	* or1k-asm.c: Regenerate.
2018-10-05 11:41:40 +09:00
Alan Modra
67ce483baa PR23430, Indices misspelled
PR 23430
include/
	* elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
bfd/
	* dwarf2.c (dwarf_debug_section_enum): Fix comment typo.
	* elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise.
binutils/
	* elfcomm.h (struct archive_info): Rename uses_64bit_indicies
	to uses_64bit_indices.
	* elfcomm.c (setup_archive): Update uses of above.
	* readelf.c (process_archive): Likewise.
	(get_section_type_name): Rename indicies to indices.
	(get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise.
	(process_section_groups): Likewise.
cpu/
	* or1kcommon.cpu (spr-reg-indices): Fix description typo.
opcodes/
	* or1k-desc.h: Regenerate.
2018-07-24 19:58:12 +09:30
Alan Modra
84f9f8c330 PR22069, Several instances of register accidentally spelled as regsiter
PR 22069
binutils/
	* od-macho.c (dump_unwind_encoding_x86): Adjust for macro renaming.
cpu/ChangeLog
	* or1kcommon.cpu (spr-reg-info): Typo fix.
include/ChangeLog
	* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
	Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
	(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
	MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
opcodes/ChangeLog
	* cr16-opc.c (cr16_instruction): Comment typo fix.
	* hppa-dis.c (print_insn_hppa): Likewise.
sim/ppc/ChangeLog
	* e500_registers.h: Comment typo fix.
	* ppc-instructions (ppc_insn_mfcr): Likewise.
2018-05-09 15:55:28 +09:30
Alan Modra
a6743a5420 opcodes error messages
Another patch aimed at making binutils comply with the GNU coding
standard.  The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html

cpu/
	* frv.opc: Include opintl.h.
	(add_next_to_vliw): Use opcodes_error_handler to print error.
	Standardize error message.
	(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
	* sysdep.h (opcodes_error_handler): Define.
	(_bfd_error_handler): Declare.
	* Makefile.am: Remove stray #.
	* opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
	EDIT" comment.
	* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
	* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
	* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
	opcodes_error_handler to print errors.  Standardize error messages.
	* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
	and include opintl.h.
	* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
	* i386-gen.c: Standardize error messages.
	* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
	* Makefile.in: Regenerate.
	* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
	* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
	* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
	* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
	* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
	* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
	* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
	* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
	* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
	* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
	* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
	* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
	* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2018-03-03 11:34:26 +10:30
Nick Clifton
faf766e317 Add note about 2.30 branch creation to changelogs 2018-01-13 13:26:38 +00:00
Stafford Horne
4ea0266c22 Update the openrisc previous program counter (ppc) when running code in the cgen based simulator.
* or1kcommon.cpu: Add pc set semantics to also update ppc.
2017-03-20 15:33:51 +00:00
Alan Modra
b781683b71 Add fall through comment to source in cpu/
I edited opcodes/mep-asm.c in 1a0670f3 without noticing it was a
generated file.

	* mep.opc (expand_string): Add fall through comment.
2016-10-06 22:48:37 +10:30
Alan Modra
439baf7121 Correct fr30 comment
* fr30.cpu (f.m4): Replace bogus comment with a better guess
	at what is really going on.
2016-03-03 12:55:30 +10:30
Alan Modra
62de1c630f Fix shift left warning at source
cpu/
	* fr30.cpu (f-m4): Replace -1 << 4 with -16.
opcodes/
	* fr30-ibld.c: Regenerate.
2016-03-02 13:35:41 +10:30
Andrew Burgess
b89807c67b epiphany/disassembler: Improve alignment of output.
Always set the bytes_per_line field (of struct disassemble_info) to the
same constant value, this is inline with the advice contained within
include/dis-asm.h.

Setting this field to a constant value will cause the disassembler
output to be better aligned.

cpu/ChangeLog:

	* epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to
	a constant to better align disassembler output.

opcodes/ChangeLog:

	* epiphany-dis.c: Regenerated from latest cpu files.

gas/ChangeLog:

	* testsuite/gas/epiphany/sample.d: Update expected output.
2016-02-02 11:09:17 +00:00
H.J. Lu
72f4393d8c Remove leading/trailing white spaces in ChangeLog 2015-07-24 04:16:47 -07:00
Stefan Kristiansson
018dc9bedf or1k: add missing l.msync, l.psync and l.psync instructions.
Even though the opcodes were defined for these instructions,
the actual instruction definitions were lacking.

cpu/
	* or1korbis.cpu (l-msync, l-psync, l-csync): New instructions.

opcodes/
	* or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
	* or1k-opinst.c: Regenerate.
2014-07-20 20:26:09 +03:00
Alan Modra
c151b1c645 Whitespace fixes for cpu/or1k.opc
* or1k.opc: Whitespace fixes.
2014-06-12 12:30:57 +09:30
Stefan Kristiansson
999b995ddc or1k: add support for l.swa/l.lwa atomic instructions
This adds support for the load-link/store-conditional
l.lwa/l.swa atomic instructions.
The support is added in such way, that the cpu description not
only describes the mnemonics, but also the functionality.

A couple of fixes to typos in nearby/related code are also snuck
into this.

cpu/
	* or1korbis.cpu (h-atomic-reserve): New hardware.
	(h-atomic-address): Likewise.
	(insn-opcode): Add opcodes for LWA and SWA.
	(atomic-reserve): New operand.
	(atomic-address): Likewise.
	(l-lwa, l-swa): New instructions.
	(l-lbs): Fix typo in comment.
	(store-insn): Clear atomic reserve on store to atomic-address.
	Fix register names in fmt field.

opcodes/
	* or1k-desc.c: Regenerated.
	* or1k-desc.h: Likewise.
	* or1k-opc.c: Likewise.
	* or1k-opc.h: Likewise.
	* or1k-opinst.c: Likewise.
2014-05-08 09:02:50 +03:00
Christian Svensson
73589c9dbd Remove support for the (deprecated) openrisc and or32 configurations and replace
with support for the new or1k configuration.
2014-04-22 15:57:47 +01:00
Mike Frysinger
594d8fa8e9 strip off +x bits on non-executable/script files
These files are source files and have no business being +x.  We couldn't
easily fix it in CVS (you need login+write access to the raw rcs files),
but we can fix this w/git.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2013-12-07 02:03:03 -05:00
Nick Clifton
87a8d6cbe0 PR binutils/15241
* lm32.cpu (Control and status registers): Add CFG2, PSW,
	TLBVADDR, TLBPADDR and TLBBADVADDR.

	* lm32-desc.c: Regenerate.
2013-03-08 17:25:12 +00:00
Nick Clifton
752937aa0c Add copyright notices 2012-12-10 12:48:03 +00:00
Joern Rennecke
02a79b89fd 2012-11-30 Oleg Raikhman <oleg@adapteva.com>
Joern Rennecke  <joern.rennecke@embecosm.com>

cpu:
        * epiphany.cpu (keyword gr-names): Move sb/sl/ip after r9/r10/r12.
        (load_insn): Add NO-DIS attribute to x, p, d, dpm, dl0, dl0.l.
        (testset-insn): Add NO_DIS attribute to t.l.
        (store-insn): Add NO-DIS attribute to x.l, p.l, d.l, dpm.l, dl0.l.
        (move-insns): Add NO-DIS attribute to cmov.l.
        (op-mmr-movts): Add NO-DIS attribute to movts.l.
        (op-mmr-movfs): Add NO-DIS attribute to movfs.l.
        (op-rrr): Add NO-DIS attribute to .l.
        (shift-rrr): Add NO-DIS attribute to .l.
        (op-shift-rri): Add NO-DIS attribute to i32.l.
        (bitrl, movtl): Add NO-DIS attribute.
        (op-iextrrr): Add NO-DIS attribute to .l
        (op-two_operands-float, op-fabs-float): Add NO-DIS attribute to f32.l.
        (op-fix2float-float, op-float2fix-float, op-fextop-float): Likewise.

opcodes:
        * epiphany-desc.c, epiphany-desc.h, epiphany-opc.c: Regenerate.
2012-11-30 17:54:58 +00:00
Alan Modra
a597d2d3d2 cpu/
* mt.opc (print_dollarhex): Trim values to 32 bits.
opcodes/
	* mt-dis.c: Regenerate.
2012-02-27 06:57:57 +00:00
Nick Clifton
5011093dd0 * frv.opc (parse_uhi16): Fix handling of %hi operator on 64-bit
hosts.

	* cgen-asm.c (cgen_parse_signed_integer): Add code to handle the
	sign extension of negative values on a 64-bit host.
	* frv-asm.c: Regenerate.

	* gas/frv/immediates.s: New test file - checks assembly of
	constant values.
	* gas/frv/immediates.d: Expected disassmbly.
	* gas/frv/allinsn.exp: Run the new test.
2011-12-15 10:21:51 +00:00
Joern Rennecke
926e2094bb bfd:
* cpu-epiphany.c: Reinstate full list of Copyright years.
        * elf32-epiphany.c: Likewise.
cpu:
        * epiphany.cpu, epiphany.opc: Likewise.
gas:
        * config/tc-epiphany.c, config/tc-epiphany.h: Likewise.
        * doc/c-epiphany.texi: Likewise.
include:
        * elf/epiphany.h: Likewise.
2011-10-27 14:27:16 +00:00
Joern Rennecke
fd936b4c69 cpu:
* epiphany.opc (parse_branch_addr): Fix type of valuep.
        Cast value before printing it as a long.
        (parse_postindex): Fix type of valuep.
opcodes:
        * epiphany-asm.c, epiphany-opc.h: Regenerate.
2011-10-26 12:46:04 +00:00
Nick Clifton
cfb8c0921c bfd:
* Makefile.am (ALL_MACHINES): Add cpu-epiphany.lo .
	(ALL_MACHINES_CFILES): Add cpu-epiphany.c .
	(BFD32_BACKENDS): Add elf32-epiphany.lo .
	(BFD32_BACKENDS_CFILES): Add elf32-epiphany.c .
	* Makefile.in, bfd-in2.h, configure, libbfd.h: Regenerate.
	* archures.c (bfd_arch_epiphany): Add.
	(bfd_mach_epiphany16, bfd_mach_epiphany32): Define.
	(bfd_epiphany_arch): Declare.
	(bfd_archures_list): Add &bfd_epiphany_arch.
	* config.bfd (epiphany-*-elf): New target case.
	* configure.in (bfd_elf32_epiphany_vec): New target vector case.
	* reloc.c (BFD_RELOC_EPIPHANY_SIMM8): New relocation.
	(BFD_RELOC_EPIPHANY_SIMM24, BFD_RELOC_EPIPHANY_HIGH): Likewise.
	(BFD_RELOC_EPIPHANY_LOW, BFD_RELOC_EPIPHANY_SIMM11): Likewise.
	(BFD_RELOC_EPIPHANY_IMM11, BFD_RELOC_EPIPHANY_IMM8): Likewise.
	* targets.c (bfd_elf32_epiphany_vec): Declare.
	(_bfd_target_vector): Add bfd_elf32_epiphany_vec.
	* po/SRC-POTFILES.in, po/bfd.pot: Regenerate.
	* cpu-epiphany.c, elf32-epiphany.c: New files.
binutils:
	* readelf.c (include "elf/epiphany.h")
	(guess_is_rela, dump_relocation): Handle EM_ADAPTEVA_EPIPHANY.
	(get_machine_name, is_32bit_abs_reloc, is_32bit_pcrel_reloc): Likewise.
	(is_16bit_abs_reloc, is_none_reloc): Likewise.
	* po/binutils.pot: Regenerate.
cpu:
	* cpu/epiphany.cpu, cpu/epiphany.opc: New files.
gas:
	* NEWS: Mention addition of Adapteva Epiphany support.
	* config/tc-epiphany.c, config/tc-epiphany.h: New files.
	* Makefile.am (TARGET_CPU_CFILES): Add config/tc-epiphany.c .
	(TARGET_CPU_HFILES): Add config/tc-epiphany.h .
	* Makefile.in, configure, doc/Makefile.in, po/POTFILES.in: Regenerate.
	* configure.in: Also set using_cgen for epiphany.
	* configure.tgt: Handle epiphany.
	* doc/Makefile.am (CPU_DOCS): Add c-epiphany.texi .
	* doc/all.texi: Set EPIPHANY.
	* doc/as.texinfo: Add EPIPHANY-specific text.
	* doc/c-epiphany.texi: New file.
	* po/gas.pot: Regenerate.
gas/testsuite:
	* gas/epiphany: New directory.
include:
	* dis-asm.h (print_insn_epiphany): Declare.
	* elf/epiphany.h: New file.
	* elf/common.h (EM_ADAPTEVA_EPIPHANY): Define.
ld:
	* NEWS: Mention addition of Adapteva Epiphany support.
	* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32epiphany.c .
	(eelf32epiphany.c): New rule.
	* Makefile.in: Regenerate.
	* configure.tgt: Handle epiphany-*-elf.
	* po/ld.pot: Regenerate.
	* testsuite/ld-srec/srec.exp: xfail epiphany.
	* emulparams/elf32epiphany.sh: New file.
opcodes:
	* Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
	(TARGET_LIBOPCODES_CFILES): Add  epiphany-asm.c, epiphany-desc.c,
	epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
	(CLEANFILES): Add stamp-epiphany.
	(EPIPHANY_DEPS): Set.  Make CGEN-generated Epiphany files depend on it.
	(stamp-epiphany): New rule.
	* Makefile.in, configure, po/POTFILES.in, po/opcodes.pot: Regenerate.
	* configure.in: Handle bfd_epiphany_arch.
	* disassemble.c (ARCH_epiphany): Define.
	(disassembler): Handle bfd_arch_epiphany.
	* epiphany-asm.c, epiphany-desc.c, epiphany-desc.h: New files.
	* epiphany-dis.c, epiphany-ibld.c, epiphany-opc.c: Likewise.
	* epiphany-opc.h: Likewise.
2011-10-25 11:18:16 +00:00
Nick Clifton
dc15e575ad Move cpu files from cgen/cpu to top level cpu directory. 2011-08-22 15:25:07 +00:00
Alan Modra
9ccb8af972 Fix build with -DDEBUG=7 2010-10-08 14:00:50 +00:00
DJ Delorie
21375995bd * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it.
* m32c-ibld.c: Regenerate.
2010-07-03 04:09:56 +00:00
Doug Evans
5ff58fb071 * m32r.cpu (HASH-PREFIX): Delete.
(duhpo, dshpo): New pmacros.
	(simm8, simm16): Delete HASH-PREFIX attribute, define with dshpo.
	(uimm3, uimm4, uimm5, uimm8, uimm16, imm1): Delete HASH-PREFIX
	attribute, define with dshpo.
	(uimm24): Delete HASH-PREFIX attribute.
	* m32r.opc (CGEN_PRINT_NORMAL): Delete.
	(print_signed_with_hash_prefix): New function.
	(print_unsigned_with_hash_prefix): New function.
	* xc16x.cpu (dowh): New pmacro.
	(upof16): Define with dowh, specify print handler.
	(qbit, qlobit, qhibit): Ditto.
	(upag16): Ditto.
	* xc16x.opc (CGEN_PRINT_NORMAL): Delete.
	(print_with_dot_prefix): New functions.
	(print_with_pof_prefix, print_with_pag_prefix): New functions.
2010-02-12 04:38:21 +00:00
Doug Evans
3fa5b97b27 * desc-cpu.scm (cgen-desc.h): Don't print virtual enums.
* sid-cpu.scm (cgen-desc.h): Ditto.
	* enum.scm (enum-builtin!): New function.
	* read.scm (reader-install-builtin!): Call it.
	* rtl-c.scm (s-convop): Delete, replaced with ...
	(s-int-convop, s-float-convop): ... new fns.
	(ext, zext, trunc): Update.
	(fext, ftrunc, float, ufloat, fix, ufix): Update.
	* rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter
	`how'.
	* cpu/mep-fmax.cpu (fcvtsw): Update.
	* cpu/sh.cpu (h-fsd, h-fmov): Update.
	* doc/rtl.texi (float-convop): Update.

	* frv.cpu (floating-point-conversion): Update call to fp conv op.
	(floating-point-dual-conversion, ne-floating-point-dual-conversion,
	conditional-floating-point-conversion, ne-floating-point-conversion,
	float-parallel-mul-add-double-semantics): Ditto.
2010-01-25 03:50:44 +00:00
Doug Evans
fe8afbc48f cpu/
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
	(f-dsp-40-u20, f-dsp-40-u24): Ditto.
	opcodes/
	* cgen-ibld.in: #include "cgen/basic-modes.h".
	* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
	* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
	* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
	* xstormy16-ibld.c: Regenerate.
2010-01-06 05:30:19 +00:00
Doug Evans
caaf56fbb2 * m32c.opc (parse_signed16): Fix typo. 2010-01-02 18:37:59 +00:00
Nick Clifton
91d6fa6a03 Add -Wshadow to the gcc command line options used when compiling the binutils.
Fix up all warnings generated by the addition of this switch.
2009-12-11 13:42:17 +00:00
Doug Evans
ec84cc2be7 Must use VOID expression in VOID context.
* xc16x.cpu (mov4): Fix mode of `sequence'.
	(mov9, mov10): Ditto.
	(movbsrr, moveb1, jmprel, jmpseg, jmps): Fix mode of `if'.
	(callr, callseg, calls, trap, rets, reti): Ditto.
	(jb, jbc, jnb, jnbs): Fix mode of `if'.  Comment out no-op `sll'.
	(atomic, extr, extp, extp1, extpg1, extpr, extpr1): Fix mode of `cond'.
	(exts, exts1, extsr, extsr1, prior): Ditto.
2009-11-14 19:48:57 +00:00
Doug Evans
ac1e9eca70 cpu/
* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
	cgen-ops.h -> cgen/basic-ops.h.

	include/opcode/
	* cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
	* cgen.h: Update.  Improve multi-inclusion macro name.

	include/cgen/
	* basic-modes.h: New file.  Moved here from opcodes/cgen-types.h.
	* basic-ops.h: New file.  Moved here from opcodes/cgen-ops.h.
	* bitset.h: New file.  Moved here from ../opcode/cgen-bitset.h.
	Update license to GPL v3.

	opcodes/
	* cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h.
	* cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h.
	* cgen-bitset.c: Update.
	* fr30-desc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* openrisc-desc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
2009-10-24 00:17:08 +00:00
Alan Modra
b4744b170e * m32r.cpu (stb-plus): Typo fix. 2009-09-25 14:07:07 +00:00
Doug Evans
ab5f875d24 * m32r.cpu (sth-plus): Fix address mode and calculation.
(stb-plus): Ditto.
	(clrpsw): Fix mask calculation.
	(bset, bclr, btst): Make mode in bit calculation match expression.

	* xc16x.cpu (rtl-version): Set to 0.8.
	(gr-names, ext-names,psw-names): Update, print-name -> enum-prefix,
	make uppercase.  Remove unnecessary name-prefix spec.
	(grb-names, conditioncode-names, extconditioncode-names): Ditto.
	(grb8-names, r8-names, regmem8-names, regdiv8-names): Ditto.
	(reg0-name, reg0-name1, regbmem8-names, memgr8-names): Ditto.
	(h-cr): New hardware.
	(muls): Comment out parts that won't compile, add fixme.
	(mulu, divl, divlu, jmpabs, jmpa-, jmprel, jbc, jnbs, callr): Ditto.
	(scxti, scxtmg, scxtm, bclear, bclr18, bset19, bitset, bmov): Ditto.
	(bmovn, band, bor, bxor, bcmp, bfldl, bfldh): Ditto.
2009-09-23 22:30:55 +00:00
Alan Modra
aa820537ea update copyright dates 2009-09-02 07:25:43 +00:00
Doug Evans
0aaaf7c3ef * cpu/simplify.inc (*): One line doc strings don't need \n.
(df): Invoke define-full-ifield instead of claiming it's an alias.
	(dno): Define.
	(dnop): Mark as deprecated.
2009-07-16 17:53:25 +00:00
Alan Modra
1998a8e033 cpu/
* m32c.opc (parse_lab_5_3): Use correct enum.
opcodes/
	* m32c-asm.c: Regenerate.
2009-06-22 00:53:25 +00:00
Hans-Peter Nilsson
6347aad80c * frv.cpu (mabshs): Explicitly sign-extend arguments of abs to DI.
(DI-ext-HI, DI-ext-UHI, DI-ext-DI): New pmacros.
	(media-arith-sat-semantics): Explicitly sign- or zero-extend
	arguments of "operation" to DI using "mode" and the new pmacros.
2009-01-07 01:09:24 +00:00
Hans-Peter Nilsson
2c06b7a648 * cris.cpu (cris-implemented-writable-specregs-v32): Correct size
of number 2, PID.
2009-01-03 17:51:12 +00:00
Nick Clifton
84e94c9023 Add LM32 port. 2008-12-23 19:10:25 +00:00
Alan Modra
90518ff484 * mt.opc (parse_imm16): Apply 2007-09-26 opcodes/mt-asm.c change
to source.
2008-01-29 03:50:23 +00:00
Hans-Peter Nilsson
a69f60de1a * cris.cpu (movs, movu): Use result of extension operation when
updating flags.
2007-10-22 16:04:43 +00:00
Nick Clifton
9b201bb5e5 Change source files over to GPLv3. 2007-07-05 09:49:03 +00:00
Mark Salter
53289dcddc Support new FR-V SPRs 2007-04-30 13:21:52 +00:00
Nick Clifton
f6da2ec281 Changelog entry for previous delta 2007-04-20 13:05:18 +00:00
Nick Clifton
98693b73e9 Restore from version 1.1 2007-04-20 12:57:02 +00:00