Commit Graph

3504 Commits

Author SHA1 Message Date
Alan Modra
44e4546fa2 ubsan: m32c: left shift of negative value
cpu/
	* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-02-03 15:59:08 +10:30
Alan Modra
b2b1453ad4 ubsan: frv: left shift of negative value
More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.
2020-02-01 23:23:18 +10:30
Jan Beulich
4102be5cf9 x86: replace EXxmm_mdq by EXVexWdqScalar
There's no need to have two operand specifiers / enumerators for the
same purpose. This then renders xmm_mdq_mode unused.
2020-01-31 14:29:18 +01:00
Jan Beulich
825bd36cea x86: drop unused EXVexWdq / vex_w_dq_mode 2020-01-31 14:28:43 +01:00
Richard Sandiford
c3036ed063 aarch64: Fix MOVPRFX markup for bf16 conversions
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H.  In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

opcodes/
	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

gas/
	* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
	.s for the movprfx.
	* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
	* testsuite/gas/aarch64/sve-movprfx_28.d,
	* testsuite/gas/aarch64/sve-movprfx_28.l,
	* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
2020-01-31 13:22:46 +00:00
Alan Modra
0c115f8483 ubsan: m32c: left shift of negative value
More nonsense fixing "bugs" with left shifts of signed values.  Yes,
the C standard does say this is undefined (and right shifts of signed
values are implementation defined BTW) but in practice there is no
problem with current machines.  1's complement is a thing of the past.

cpu/
	* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
	(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
	(f-dst32-rn-prefixed-QI): Likewise.
	(f-dsp-32-s32): Mask before shifting left.
	(f-dsp-48-u32, f-dsp-48-s32): Likewise.
	(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
	shifting left.
	(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
	(h-gr-SI): Mask before shifting.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-30 23:39:55 +10:30
Jose E. Marchesi
bd434cc4d9 cpu,opcodes,gas: fix neg and neg32 instructions in BPF
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.

cpu/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-alu-insn-un): The unary BPF instructions
	(neg and neg32) use OP_SRC_K even if they operate only in
	registers.

opcodes/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

gas/ChangeLog:

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
	* testsuite/gas/bpf/alu-be.d: Likewise.
	* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
	* testsuite/gas/bpf/alu32-be.d: Likewise.
2020-01-30 13:59:04 +01:00
Jan Beulich
aeab2b26db x86-64: honor vendor specifics for near RET
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
2020-01-30 11:36:33 +01:00
Jan Beulich
62b3f54810 x86: drop further pointless/bogus DefaultSize
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.

It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
2020-01-30 11:33:53 +01:00
Alan Modra
1bd8ae1004 ubsan: tic4x: left shift cannot be represented in type 'int'
The patch also fixes a case where libopcodes built for a 64-bit
bfd_vma may print different results to libopcodes built for a 32-bit
bfd_vma.

	* tic4x-dis.c (tic4x_dp): Make unsigned.
2020-01-30 17:06:54 +10:30
H.J. Lu
bc31405ebb x86-64: Properly encode and decode movsxd
movsxd is a 64-bit only instruction.  It supports both 16-bit and 32-bit
destination registers.  Its AT&T mnemonic is movslq which only supports
64-bit destination register.  There is also a discrepancy between AMD64
and Intel64 on movsxd with 16-bit destination register.  AMD64 supports
32-bit source operand and Intel64 supports 16-bit source operand.

This patch updates movsxd encoding and decoding to alow 16-bit and 32-bit
destination registers.  It also handles movsxd with 16-bit destination
register for AMD64 and Intel 64.

gas/

	PR binutils/25445
	* config/tc-i386.c (check_long_reg): Also convert to QWORD for
	movsxd.
	* doc/c-i386.texi: Add a node for AMD64 vs. Intel64 ISA
	differences.  Document movslq and movsxd.
	* testsuite/gas/i386/i386.exp: Run PR binutils/25445 tests.
	* testsuite/gas/i386/x86-64-movsxd-intel.d: New file.
	* testsuite/gas/i386/x86-64-movsxd-intel64-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-intel64.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.l: Likewise.
	* testsuite/gas/i386/x86-64-movsxd-inval.s: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.d: Likewise.
	* testsuite/gas/i386/x86-64-movsxd.s: Likewise.

opcodes/

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.
2020-01-27 04:38:29 -08:00
Tamar Christina
7568c93bf9 AArch64: Fix cfinv disassembly issues
This fixes the preferred disassembly for cfinv.  The Armv8.4-a instruction
overlaps with the possible encoding space for msr.  This because msr allows you
to use unallocated encoding space using the general sA_B_cC_cD_E form.

However when an encoding does become allocated then we need to ensure that it's
used as the preferred disassembly.  The problem with cfinv is that its mask has
all bits sets because it has no arguments.

This causes issues for the Alias resolver in gas as it uses the mask to build
alias graph.  In this case it can't do it since it thinks almost everything
would alias with cfinv.  So instead we can only fix this by moving cfinv before
msr.

gas/ChangeLog:

	PR 25403
	* testsuite/gas/aarch64/armv8_4-a.d: Add cfinv.
	* testsuite/gas/aarch64/armv8_4-a.s: Likewise.

opcodes/ChangeLog:

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.
2020-01-27 10:55:41 +00:00
Jan Beulich
c006a730e9 x86: improve handling of insns with ambiguous operand sizes
Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).

Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.

Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).
2020-01-21 08:28:25 +01:00
Jan Beulich
c906a69a1f x86: VCVTNEPS2BF16{X,Y} should permit broadcasting
Just like other VCVT*{X,Y} templates do, and to allow the programmer
flexibility (might be relevant in particular when heavily macro-izing
code), the two templates should also have Broadcast set, just like their
X/Y-suffix-less counterparts. This in turn requires them to also have
* Dword set on their memory operands, to cover the logic added to
  i386gen by 4a1b91eabb ("x86: Expand Broadcast to 3 bits"),
* RegXMM/RegYMM set on their source operands, to satisfy broadcast
  sizing logic in gas itself.
Otherwise ATTSyntax templates wouldn't need such operand size attributes.

While extending the test cases, also add Intel syntax broadcast forms
without explicit size specifiers.
2020-01-21 08:25:31 +01:00
Nick Clifton
26916852e1 Updated translations for various binutils sub-directories 2020-01-20 15:10:23 +00:00
Alan Modra
4d6cbb6442 ubsan: hppa: negation of -2147483648
* hppa-dis.c (fput_const): Remove useless cast.
2020-01-20 15:45:50 +10:30
Alan Modra
2bddb71a74 ubsan: arm: out of bounds array access
.inst 0x81bdfe9f

disassembles as
   0:	81bdfe9f 	ldaexdhi	pc, reg-names-std, [sp]

I'm quite sure "reg-names-std" isn't an ARM register.

	* arm-dis.c (print_insn_arm): Wrap 'T' value.
2020-01-20 15:45:50 +10:30
Nick Clifton
1b1bb2c67b Update version to 2.34.50. Regenerate configure and .pot files. 2020-01-18 14:12:07 +00:00
Nick Clifton
ae77468624 Add markers for 2.34 branch to the NEWS files and ChangeLogs. 2020-01-18 13:50:25 +00:00
Christian Biesinger
07f1f3aa53 Fix spelling errors
seperate -> separate

bfd/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* coff-arm.c: Fix spelling error (seperate).
	* elfxx-riscv.c (riscv_parse_sv_or_non_std_ext): Fix spelling
	error (seperate).
	* sysdep.h (strnlen): Fix spelling error (seperate).

opcodes/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

sim/arm/ChangeLog:

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* iwmmxt.c: Fix spelling error (seperate).

Change-Id: I55e5f47bcf3cf3533d2acb7ad338f1be0d5f30f9
2020-01-17 12:34:03 -06:00
H.J. Lu
42e04b3601 x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix.  2-byte VEX prefix
can't encode all operands.  By default, assembler tries 2-byte VEX prefix
first.  {vex3} can be used to force 3-byte VEX prefix.  This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.

gas/

	* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
	with vex_encoding_vex.
	(parse_insn): Likewise.
	* doc/c-i386.texi: Replace {vex2} with {vex}.  Update {vex}
	and {vex3} documentation.
	* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
	{vex}.
	* testsuite/gas/i386/x86-64-pseudos.s: Likewise.

opcodes/

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.
2020-01-17 07:07:55 -08:00
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
2020-01-16 14:33:01 +00:00
Jan Beulich
d0849eed78 x86: drop stale Vec_Imm4 related comment
I overlooked this in commit 9d3bf266fd ("x86: drop Vec_Imm4"), presumably
because of the mis-spelling.
2020-01-16 10:07:05 +01:00
Jan Beulich
9cf70a448b x86: add a few more missing VexWIG
Alternatively it could also be VexW0 (to match other SSE2AVX), but the
VexW attribute shouldn't be left unset.
2020-01-16 10:06:21 +01:00
Jan Beulich
4814632e69 x86: VPEXTRQ/VPINSRQ are unavailable outside of 64-bit mode
The AVX512DQ patterns lacking a Cpu64 attribute made the memory operand
forms accepted even outside of 64-bit mode, and this even without any
{evex} pseudo-prefix (otherwise one could argue that this is an attempt
to follow one possible, albeit somewhat odd, interpretation of the SDM
wording to this effect).

For consistency between the various involved templates drop the
* (now) unnecessary IgnoreSize attributes
* unnecessary (due to VexW1) Size64 attributes from VEX encoded forms
* redundant (with Reg64) Qword operand attributes
uniformly.
2020-01-16 10:05:35 +01:00
Alan Modra
aad09917e0 tic4x disassembly static variables
tic4x uses a number of static variables for tables that are generated
depending on the current machine (tic4x vs. tic3x).  However, it is
possible to change the machine from one invocation of print_insn_tic4x
to the next.  This patch throws away the old state if that happens,
and uses a relatively small known size array of register names rather
than a malloc'd table.

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.
2020-01-16 00:01:13 +10:30
Sergey Belyashov
7a6bf3becb Fix various assembler testsuite failures for the Z80 target.
PR 25377
gas	* config/tc-z80.c: Add support for half precision, single
	precision and double precision floating point values.
	* config/tc-z80.h b/gas/config/tc-z80.h: Disable string escapes.
	* doc/as.texi: Add new z80 command line options.
	* doc/c-z80.texi: Document new z80 command line options.
	* testsuite/gas/z80/ez80_pref_dis.s: New test.
	* testsuite/gas/z80/ez80_pref_dis.d: New test driver.
	* testsuite/gas/z80/z80.exp: Run the new test.
	* testsuite/gas/z80/fp_math48.d: Use correct command line option.
	* testsuite/gas/z80/fp_zeda32.d: Likewise.
	* testsuite/gas/z80/strings.d: Update expected output.

opcodes	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.
2020-01-14 13:13:57 +00:00
Alan Modra
ca1eaac0ed ubsan: z8k: left shift cannot be represented in type 'int'
* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.
2020-01-14 10:57:52 +10:30
Thomas Troeger
1d67fe3b6e Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
	(detected_jumps): New variables.
	(usage): Add the new jump visualization options.
	(option_values): Add new option value.
	(long_options): Add the new option.
	(jump_info_new, jump_info_free): New functions.
	(jump_info_min_address, jump_info_max_address): Likewise.
	(jump_info_end_address, jump_info_is_start_address): Likewise.
	(jump_info_is_end_address, jump_info_size): Likewise.
	(jump_info_unlink, jump_info_insert): Likewise.
	(jump_info_add_front, jump_info_move_linked): Likewise.
	(jump_info_intersect, jump_info_merge): Likewise.
	(jump_info_sort, jump_info_visualize_address): Likewise.
	(disassemble_jumps): New function - used to locate jumps.
	(disassemble_bytes): Add ascii art generation.
	(disassemble_section): Add scan to locate jumps.
	(main): Parse the new visualization option.
	* doc/binutils.texi: Document the new feature.
	* NEWS: Mention the new feature.

opcodes	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.
2020-01-13 12:36:55 +00:00
Claudiu Zissulescu
5e4f7e0518 [ARC][committed] Code cleanup and improvements.
Code clean up and improvements when changing the cpu from command
line. Also, remove unused/old emulations.

gas/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (arc_select_cpu): Re-init the bfd if we change
	the CPU.
	* config/tc-arc.h: Add header if/defs.
	* testsuite/gas/arc/pseudos.d: Improve matching pattern.

ls/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* Makefile.am: Remove earcelf_prof.c and earclinux_prof.c
	emulations.
	* Makefile.in: Regenerate.
	* configure.tgt: Likewise.
	* emulparams/arcelf_prof.sh: Remove file.
	* emulparams/arclinux_prof.sh: Likewise.

opcodes/
xxxx-xx-xx  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (C_NE): Make it required.
2020-01-13 11:16:47 +02:00
Claudiu Zissulescu
b9fe6b8aa6 [ARC] [COMMITTED] Change ACCL/ACCH reg name to generic.
ACCL/ACCH register names are only available for ARCv2 architecture,
leading to a confusion when disassembling for any other ARC
variants. This patch is changing the default names for ACCL/ACCH to
generic r58/r59.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.
2020-01-13 10:25:50 +02:00
Alan Modra
90dee485e5 asan: ns32k: wild memory write
index_offset isn't set up for "sfsr", resulting in a random offset
being used when trying to disassemble the following.

 .byte 0x3e, 0xf7, 0x07, 0x00

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2020-01-13 18:43:34 +10:30
Alan Modra
febda64f15 ubsan: wasm32: signed integer overflow
The signed integer overflow occurred when adding one to target_count
  for (i = 0; i < target_count + 1; i++)
but that's the least of the worries here.  target_count was long and i
int, leading to the possibility of a loop that never ended.

So to avoid this type of vulnerability, this patch uses what I believe
to be the proper types for arguments of various wasm32 opcodes, rather
than using "long" which may change in size.

gas/
	* testsuite/gas/wasm32/allinsn.d: Update expected output.
opcodes/
	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.
2020-01-13 16:44:27 +10:30
Alan Modra
df08b5881b score formatting
* score-dis.c: Formatting.
	* score7-dis.c: Formatting.
2020-01-13 12:12:41 +10:30
Alan Modra
b2c759ce68 ubsan: score: left shift of negative value
* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2020-01-13 12:12:30 +10:30
Alan Modra
5496abe1c5 tic4x: sign extension using shifts
Don't do that.  Especially don't use shift counts that assume the type
being shifted is 32 bits when the type is long/unsigned long.  Also
reverts part of a change I made on 2019-12-11 to tic4x_print_register
that on closer inspection turns out to be unnecessary.

include/
	* opcode/tic4x.h (EXTR): Delete.
	(EXTRU, EXTRS, INSERTU, INSERTS): Rewrite without zero/sign
	extension using shifts.  Do trim INSERTU value to specified bitfield.
opcodes/
	* tic4x-dis.c (tic4x_print_register): Remove dead code.
gas/
	* config/tc-tic4x.c (tic4x_operands_match): Correct tic3x trap
	insertion.
2020-01-13 12:12:05 +10:30
Alan Modra
202e762b32 ubsan: fr30: left shift of negative value
cpu/
	* fr30.cpu (f-disp9, f-disp10, f-s10, f-rel9, f-rel12): Don't
	left shift signed values.
opcodes/
	* fr30-ibld.c: Regenerate.
2020-01-13 12:12:05 +10:30
Alan Modra
7ef412cf72 ubsan: xgate: left shift of negative value
* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.
2020-01-13 12:12:05 +10:30
Alan Modra
7f578b959c ubsan: tilepro: signed integer overflow
* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
2020-01-10 17:32:33 +10:30
Alan Modra
441af85bd9 ubsan: m10300: shift exponent -4
* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.
2020-01-10 17:32:33 +10:30
Nick Clifton
bce58db4fb Fix the cast used to prevent compile time warning about an always false test.
PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.
2020-01-09 14:32:49 +00:00
Sergey Belyashov
40c75bc8b0 Fix compile time warnings about comparisons always being false.
PR 25224
gas	* config/tc-z80.c (emit_ld_m_rr): Use integer types when checking
	opcode byte values.
	(emit_ld_r_r): Likewise.
	(emit_ld_rr_m): Likewise.
	(emit_ld_rr_nn): Likewise.

opcodes	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.
2020-01-09 11:49:18 +00:00
Jan Beulich
d835a58baa x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD
The disassembler change is such that in default mode we'd disassemble
the insns (for there not ebing any conflicts), but when AMD64 mode was
explicitly requested, we'd show them as "(bad)".
2020-01-09 11:38:01 +01:00
Alan Modra
030a2e78ac ubsan: z8k: index 10 out of bounds for type 'unsigned int const[10]'
The fix is the additional ARRAY_SIZE test, the rest just tidies
variable types rather than adding a cast to avoid warnings.

opcodes/
	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.
gas/
	* config/tc-z8k.c (md_begin): Make idx unsigned.
	(get_specific): Likewise for this_index.
2020-01-08 21:51:32 +10:30
Shahab Vahedi
bb82aefe17 [ARC] Add finer details for LLOCK and SCOND
This patch changes the "class" of LLOCK/SCOND from "MEMORY" to
"LLOCK/SCOND" respectively. Moreover, it corrects the "data_size_mode".

These changes are necessary for GDB's atmoic sequence handler.

Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
2020-01-07 15:25:34 +02:00
Alan Modra
cc6aa1a6e0 ubsan: m32c: left shift of negative value
There are probably a lot more of these still here.

cpu/
	* m32c.cpu (f-dsp-8-u16, f-dsp-8-s16): Rearrange to mask any sign
	bits before shifting rather than masking after shifting.
	(f-dsp-16-u16, f-dsp-16-s16, f-dsp-32-u16, f-dsp-32-s16): Likewise.
	(f-dsp-40-u16, f-dsp-40-s16, f-dsp-48-u16, f-dsp-48-s16): Likewise.
	(f-dsp-64-u16, f-dsp-8-s24): Likewise.
	(f-bitbase32-16-s19-unprefixed): Avoid signed left shift.
opcodes/
	* m32c-ibld.c: Regenerate.
2020-01-06 21:53:51 +10:30
Alan Modra
660e62b1d9 PR25344, z80 disassembler recursion
PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.
2020-01-06 21:53:16 +10:30
Alan Modra
c9ae58fe32 ubsan: m32r: left shift of negative value
cpu/
	* m32r.cpu (f-disp8): Avoid left shift of negative values.
	(f-disp16, f-disp24): Likewise.
opcodes/
	* m32r-ibld.c: Regenerate.
2020-01-04 19:20:33 +10:30
Alan Modra
5f57d4ecf5 ubsan: cr16: left shift cannot be represented in type 'int'
* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30
Alan Modra
2c5c119630 ubsan: crx: left shift cannot be represented in type 'int'
* crx-dis.c (match_opcode): Avoid shift left of signed value.
2020-01-04 19:20:33 +10:30