The inferior_exited_re regexp uses capturing parentheses by default:
...
set inferior_exited_re "(\\\[Inferior \[0-9\]+ \\(.*\\) exited)"
...
The parentheses are there to be able to use the expression as an atom, f.i.,
to have '+' apply to the whole regexp in "${inferior_exited_re}+".
But the capturing is not necessary, and it can be confusing because it's not
obvious in a regexp using "$inferior_exited_re (bla|bli)" that the first
captured expression is in $inferior_exited_re.
Replace by non-capturing parentheses. If we still want to capture the
expression, we can simply (and more clearly) use "($inferior_exited_re)".
Build and reg-tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2020-02-04 Tom de Vries <tdevries@suse.de>
* lib/gdb.exp (inferior_exited_re): Use non-capturing parentheses.
Change-Id: I7640c6129b1ada617424d6a63730d4b119c58ef3
This patch fixes test failures power8 and power9 caused by changes on
opcodes:
The dissasembler does not emit whitespace for instructions
anymore (c2b1c27545)
The dissasembler generates extended mnemonics for some instructions
instead (aae9718e4d)
The ldmx instruction was removed. This instruction was never
implemented (6fbc939cfd)
gdb/testsuite/ChangeLog:
2020-02-03 Rogerio A. Cardoso <rcardoso@linux.ibm.com>
* gdb.arch/powerpc-power8.exp: Delete trailing whitespace of
tbegin., tend. instructions. Replace bctar-, bctar+, bctarl-,
bctarl+ extended mnemonics when avaliable by bgttar, bnstarl,
blttar, bnetarl.
* gdb.arch/powerpc-power8.s: Fix comments. Fix instructions
binary for blttar, bnetarl.
* gdb.arch/powerpc-power9.exp: Delete trailing whitespace of
wait instruction. Delete ldmx test.
* gdb.arch/powerpc-power9.s: Delete ldmx instruction.
In the function f77_print_array_1, the variable 'i' which holds the
index is of datatype 'int', while bounds are of datatype LONGEST. Due to
size of int being smaller than LONGEST, the variable 'i' stores
incorrect values for high indexes (higher than max limit of int). Due
to this issue in sources, two abnormal behaviors are seen while printing
arrays with high indexes (please check array-bounds-high.f90) For high
indexes with negative sign, gdb prints empty array even if the array has
elements.
(gdb) p arr
$1 = ()
For high indexes with positive sign, gdb crashes. We have now changed
the datatype of 'i' to LONGEST which is same as datatype of bounds.
gdb/ChangeLog:
* f-valprint.c (f77_print_array_1): Changed datatype of index
variable to LONGEST from int to enable it to contain bound
values correctly.
gdb/testsuite/ChangeLog:
* gdb.fortran/array-bounds-high.exp: New file.
* gdb.fortran/array-bounds-high.f90: New file.
Change-Id: Ie2dce9380a249e634e2684b9c90f225e104369b7
Fix RISC-V native Linux support to handle a 64-bit FPU (FLEN == 64) with
both RV32 and RV64 systems, which is a part of the current Linux ABI for
hard-float systems, rather than assuming that (FLEN == XLEN) in target
description determination and that (FLEN == 64) in register access.
We can do better however and not rely on any particular value of FLEN
and probe for it dynamically, by observing that the PTRACE_GETREGSET
ptrace(2) call will only accept an exact regset size, and that will
reflect FLEN. Therefore iterate over the call in target description
determination with a geometrically increasing regset size until a match
is marked by a successful ptrace(2) call completion or we run beyond the
maximum size we can support.
Update register accessors accordingly, using FLEN determined to size the
buffer used for NT_PRSTATUS requests and then to exchange data with the
regcache.
Also handle a glibc bug where ELF_NFPREG is defined in terms of NFPREG,
however NFPREG is nowhere defined.
gdb/
* riscv-linux-nat.c [!NFPREG] (NFPREG): New macro.
(supply_fpregset_regnum, fill_fpregset): Handle regset buffer
offsets according to FLEN determined.
(riscv_linux_nat_target::read_description): Determine FLEN
dynamically.
(riscv_linux_nat_target::fetch_registers): Size regset buffer
according to FLEN determined.
(riscv_linux_nat_target::store_registers): Likewise.
Musl is giving warnings about these includes in this way:
warning: #warning redirecting incorrect #include <sys/errno.h> to <errno.h>
warning: #warning redirecting incorrect #include <sys/fcntl.h> to <fcntl.h>
gdb/testsuite/Changelog:
* gdb.base/fileio.c: Remove #include of <sys/errno.h>.
Replace #include of <sys/fcntl.h> by <fcntl.h>.
Clang's integrated assembler supports multiple section with the same
name:
.section .text,"ax",@progbits,unique,1
nop
.section .text,"ax",@progbits,unique,2
nop
"unique,N" assigns the number, N, as the section ID, to a section. The
valid values of the section ID are between 0 and 4294967295. It can be
used to distinguish different sections with the same section name.
This is useful with -fno-unique-section-names -ffunction-sections.
-ffunction-sections by default generates .text.foo, .text.bar, etc.
Using the same string can save lots of space in .strtab.
This patch adds section_id to bfd_section and reuses the linker
internal bit in BFD section flags, SEC_LINKER_CREATED, for assmebler
internal use to mark valid section_id. It also updates objdump to
compare section pointers if 2 sections comes from the same file since
2 different sections can have the same section name.
bfd/
PR gas/25380
* bfd-in2.h: Regenerated.
* ecoff.c (bfd_debug_section): Add section_id.
* section.c (bfd_section): Add section_id.
(SEC_ASSEMBLER_SECTION_ID): New.
(BFD_FAKE_SECTION): Add section_id.
binutils/
PR gas/25380
* objdump.c (sym_ok): Return FALSE if 2 sections are in the
same file with different section pointers.
gas/
PR gas/25380
* config/obj-elf.c (section_match): Removed.
(get_section): Also match SEC_ASSEMBLER_SECTION_ID and
section_id.
(obj_elf_change_section): Replace info and group_name arguments
with match_p. Also update the section ID and flags from match_p.
(obj_elf_section): Handle "unique,N". Update call to
obj_elf_change_section.
* config/obj-elf.h (elf_section_match): New.
(obj_elf_change_section): Updated.
* config/tc-arm.c (start_unwind_section): Update call to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texi: Document "unique,N" in .section directive.
* testsuite/gas/elf/elf.exp: Run "unique,N" tests.
* testsuite/gas/elf/section15.d: New file.
* testsuite/gas/elf/section15.s: Likewise.
* testsuite/gas/elf/section16.s: Likewise.
* testsuite/gas/elf/section16a.d: Likewise.
* testsuite/gas/elf/section16b.d: Likewise.
* testsuite/gas/elf/section17.d: Likewise.
* testsuite/gas/elf/section17.l: Likewise.
* testsuite/gas/elf/section17.s: Likewise.
* testsuite/gas/i386/unique.d: Likewise.
* testsuite/gas/i386/unique.s: Likewise.
* testsuite/gas/i386/x86-64-unique.d: Likewise.
* testsuite/gas/i386/i386.exp: Run unique and x86-64-unique.
ld/
PR gas/25380
* testsuite/ld-i386/pr22001-1c.S: Use "unique,N" in .section
directives.
* testsuite/ld-i386/tls-gd1.S: Likewise.
* testsuite/ld-x86-64/pr21481b.S: Likewise.
More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.
cpu/
* frv.cpu (f-u12): Multiply rather than left shift signed values.
(f-label16, f-label24): Likewise.
opcodes/
* frv-ibld.c: Regenerate.
When the command "info registers" (same as "info registers general"),
is issued, _all_ the registers from a tdesc XML are printed. This
includes the registers with empty register groups (set as "") which
are supposed to be only printed by "info registers all" (or "info
all-registers").
This bug got introduced after all the overhauls that the
tdesc_register_in_reggroup_p() went through. You can see that the
logic of tdesc_register_in_reggroup_p() did NOT remain the same after
all those changes:
git difftool c9c895b9666..HEAD -- gdb/target-descriptions.c
With the current implementation, when the reg->group is an empty
string, this function returns -1, while in the working revision
(c9c895b966), it returned 0. This patch makes sure that the 0 is
returned again.
The old implementation of tdesc_register_in_reggroup_p() returned
-1 when "reggroup" was set to "all_reggroups" at line 4 below:
1 tdesc_register_reggroup_p (...)
2 {
3 ...
4 ret = tdesc_register_in_reggroup_p (gdbarch, regno, reggroup);
5 if (ret != -1)
6 return ret;
7
8 return default_register_reggroup_p (gdbarch, regno, reggroup);
9 }
As a result, the execution continued at line 8 and the
default_register_reggroup_p(..., reggroup=all_reggroups) would
return 1. However, with the current implementation of
tdesc_register_in_reggroup_p() that allows checking against any
arbitrary group name, it returns 0 when comparing the "reg->group"
against the string "all" which is the group name for "all_reggroups".
I have added a special check to cover this case and
"info all-registers" works as expected.
gdb/ChangeLog:
* target-descriptions.c (tdesc_register_in_reggroup_p): Return 0
when reg->group is empty and reggroup is not.
Change-Id: I9eaf9d7fb36410ed5684ae652fe4756b1b2e61a3
There's already existing logic to handle this on other targets, so
this patch just makes nios2 use it.
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
bfd/
* elf-eh-frame.c (_bfd_elf_write_section_eh_frame): DW_EH_PE_datarel
encodings are relative to the GOT on nios2, too.
The nios2 ABI documentation lists %gotoff as assembler syntax for the
R_NIOS2_GOTOFF relocation, used to represent a 32-bit GOT-relative offset
in data sections. This was previously unimplemented in GAS.
2020-01-31 Sandra Loosemore <sandra@codesourcery.com>
gas/
* config/tc-nios2.c (nios2_cons): Handle %gotoff as well as
%tls_ldo.
We noticed +mve was not enabling DSP instructions as it should, reported in PR
25472.
The MVE architecture extension for Armv8.1-M Mainline implies DSP extensions.
This patch reflects that in the '+mve' command line option.
gas/ChangeLog:
2020-01-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR gas/25472
* config/tc-arm.c (armv8m_main_ext_table): Refactored +dsp adding.
(armv8_1m_main_ext_table): Refactored +dsp adding and enabled dsp for
+mve.
* testsuite/gas/arm/mve_dsp.d: New test.
This patch adds support for assembly instructions vldmia, vldmdb, vstmia
and vstmdb in MVE. This instructions are already supported for Armv8-M
Floating-point Extension.
gas/ChangeLog:
2020-01-31 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (fldmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2"
to support VLDMIA instruction for MVE.
(fldmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VLDMDB
instruction for MVE.
(fstmias): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMIA
instruction for MVE.
(fstmdbs): Moved inside "THUMB_VARIANT & arm_ext_v6t2" to support VSTMDB
instruction for MVE.
* testsuite/gas/arm/mve-ldst.d: New test.
* testsuite/gas/arm/mve-ldst.s: Likewise.
bfcvt converts a .S input to a .H output, so any predicated movprfx
needs to operate on .S rather than .H. In common with SVE2 narrowing
top operations, bfcvtnt doesn't accept movprfx.
2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
gas/
* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
.s for the movprfx.
* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_28.d,
* testsuite/gas/aarch64/sve-movprfx_28.l,
* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
ravenscar-thread.c needed a change to adapt to multi-target:
ravenscar_thread_target::mourn_inferior called the mourn_inferior
method on the target beneat -- but when the target beneath was the
remote target, this resulted in the ravenscar target being deleted.
Switching the order of the calls to unpush_target and the beneath's
mourn_inferior fixes this problem.
gdb/ChangeLog
2020-01-31 Tom Tromey <tromey@adacore.com>
* ravenscar-thread.c (ravenscar_thread_target::mourn_inferior):
Call beneath target's mourn_inferior after unpushing.
Change-Id: Ia80380515c403adc40505a6b3420c9cb35754370
In TUI mode, if the disassembly output for the program is less than
one screen long, then currently if the user scrolls down until on the
last assembly instruction is displayed and then tries to scroll up
using Page-Up, the display doesn't update - they are stuck viewing the
last line.
If the user tries to scroll up using the Up-Arrow, then the display
scrolls normally.
What is happening is on the Page-Up we ask GDB to scroll backward the
same number of lines as the height of the TUI ASM window. The back
scanner, which looks for a good place to start disassembling, fails to
find a starting address which will provide the requested number of new
lines before we get back to the original starting address (which is
not surprising, our whole program contains less than a screen height
of instructions), as a result the back scanner gives up and returns
the original starting address.
When we scroll with Up-Arrow we only ask the back scanner to find 1
new instruction, which it manages to do, so this scroll works.
The solution here is, when we fail to find enough instructions, to
return the lowest address we did manage to find. This will ensure we
jump to the lowest possible address in the disassembly output.
gdb/ChangeLog:
PR tui/9765
* tui/tui-disasm.c (tui_find_disassembly_address): If we don't
have enough lines to fill the screen, still return the lowest
address we found.
gdb/testsuite/ChangeLog:
PR tui/9765
* gdb.tui/tui-layout-asm-short-prog.S: New file.
* gdb.tui/tui-layout-asm-short-prog.exp: New file.
Change-Id: I6a6a7972c68a0559e9717fd8d82870b669a40af3
GDB has some commands ('+', '-', '<', and '>') for scrolling the SRC
and ASM TUI windows from the CMD window, however the help text for
these commands lists the arguments in the wrong order.
This commit updates the help text to match how GDB actually works, and
also extends the text to describe what the arguments mean, and what
the defaults are.
There should be no change in GDBs functionality after this commit.
gdb/ChangeLog:
* tui/tui-win.c (_initialize_tui_win): Update help text for '+',
'-', '<', and '>' commands.
Change-Id: Ib2624891de1f4ba983838822206304e4c3ed982e
This patch removes the leak of Nick's source directory into bfd.pot,
and emits #line for some generated files so that those files aren't
referenced by comments in the .pot file. You can see both of these
effects in the following diff. I've also removed use of an
unnecessary temp file in the make rules.
@@ -92,10 +92,8 @@ msgstr ""
#: elf64-nfp.c:238 elf64-ppc.c:1014 elf64-ppc.c:1349 elf64-ppc.c:1358
#: elf64-s390.c:328 elf64-s390.c:378 elf64-x86-64.c:285 elfn32-mips.c:3786
#: elfxx-ia64.c:324 elfxx-riscv.c:955 elfxx-sparc.c:589 elfxx-sparc.c:639
-#: elfxx-tilegx.c:912 elfxx-tilegx.c:952
-#: /work/sources/binutils/current/bfd/elfnn-aarch64.c:2215
-#: /work/sources/binutils/current/bfd/elfnn-aarch64.c:2313 elf32-ia64.c:214
-#: elf32-ia64.c:3862 elf64-ia64.c:214 elf64-ia64.c:3862
+#: elfxx-tilegx.c:912 elfxx-tilegx.c:952 elfnn-aarch64.c:2215
+#: elfnn-aarch64.c:2313 elfnn-ia64.c:214 elfnn-ia64.c:3862
#, c-format
msgid "%pB: unsupported relocation type %#x"
msgstr ""
* Makefile.am (elf32-target.h, elf64-target.h): Don't use a temp
file. Use $< and $@ in rules.
(elf32-aarch64.c, elf64-aarch64.c): Likewise.
(elf32-ia64.c, elf64-ia64.c): Likewise.
(elf32-riscv.c, elf64-riscv.c): Likewise.
(peigen.c, pepigen.c, pex64igen.c): Likewise.
(elf32-aarch64.c, elf64-aarch64.c): Don't emit $srcdir on #line.
(elf32-riscv.c, elf64-riscv.c): Likewise, and use $(SED).
(elf32-ia64.c, elf64-ia64.c): Do emit #line.
(peigen.c, pepigen.c, pex64igen.c): Likewise.
* Makefile.in: Regenerate.
We alloc, seek and read using section sizes in object files. Fuzzed
objects can have silly sizes, but that's OK if the system supports
memory over-commit. The read fails because we hit EOF and that
usually results in a graceful exit.
But if we memset before the read then the invalid size results in
attempting to write to a huge number of memory pages, and an eventual
Out Of Memory after probably swapping like crazy. So don't memset.
There really isn't a need to clear the section contents anyway. All
bytes are written with a good object file by the read and following
loop converting section index in target order to ELF section header
pointer, and the only untidy bytes are the 4 bytes past the group
flags when pointers are 8 bytes. Those don't matter but the patch
clears them for anyone poking around in a debugger. On error paths
it's as good to free section contents as it is to clear them.
Noticed when looking at PR4110 fourth test case.
PR 4110
* elf.c (setup_group): Don't clear entire section contents,
just the padding after group flags. Release alloc'd memory
after a seek or read failure.
Comparison of i.tm.base_opcode against particular but not sufficiently
specific values needs to be accompanied by other qualification. Exclude
VEX and alike encodings here, and also exclude all forms of prefixes
explicitly specified in the opcodes table. While using @GOT with such
insns may not be very useful, it also isn't with e.g. ADC and SBB, yet
these get explicitly listed in comments as supported.
Commit 9e7028aa1e ("PowerPC64 __tls_get_addr_desc") introduced a use
of @option which apparently newer makeinfo tolerates, but older ones
reject. Drop the unnecessary (a per all other uses of @option) blank.
More nonsense fixing "bugs" with left shifts of signed values. Yes,
the C standard does say this is undefined (and right shifts of signed
values are implementation defined BTW) but in practice there is no
problem with current machines. 1's complement is a thing of the past.
cpu/
* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.
(f-src32-rn-prefixed-QI, f-dst32-rn-unprefixed-QI): Likewise.
(f-dst32-rn-prefixed-QI): Likewise.
(f-dsp-32-s32): Mask before shifting left.
(f-dsp-48-u32, f-dsp-48-s32): Likewise.
(f-bitbase32-16-s11-unprefixed): Multiply signed field rather than
shifting left.
(f-bitbase32-24-s11-prefixed, f-bitbase32-24-s19-prefixed): Likewise.
(h-gr-SI): Mask before shifting.
opcodes/
* m32c-ibld.c: Regenerate.
These are produced by MSVC when the '/Brepro' flag is used.
To quote from the PE specification [1]:
"The presence of an entry of type IMAGE_DEBUG_TYPE_REPRO indicates the
PE file is built in a way to achieve determinism or reproducibility. If
the input does not change, the output PE file is guaranteed to be
bit-for-bit identical no matter when or where the PE is produced.
Various date/time stamp fields in the PE file are filled with part or
all the bits from a calculated hash value that uses PE file content as
input, and therefore no longer represent the actual date and time when a
PE file or related specific data within the PE is produced. The raw data
of this debug entry may be empty, or may contain a calculated hash value
preceded by a four-byte value that represents the hash value length."
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
bfd/ChangeLog:
2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
* peXXigen.c (pe_is_repro): New function.
(_bfd_XX_print_private_bfd_data_common): Note timestamp is
actually a build hash if PE_IMAGE_DEBUG_TYPE_REPRO is present.
IMAGE_DEBUG_TYPE_REPRO is defined in the latest version of the PE
specification [1]. The others are defined in Windows SDK headers and/or
reported by DUMPBIN.
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
bfd/ChangeLog:
2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
* peXXigen.c (debug_type_names): Add names for new debug data type
values.
include/ChangeLog:
2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
* coff/internal.h (PE_IMAGE_DEBUG_TYPE_VC_FEATURE)
(PE_IMAGE_DEBUG_TYPE_POGO, PE_IMAGE_DEBUG_TYPE_ILTCG)
(PE_IMAGE_DEBUG_TYPE_MPX, PE_IMAGE_DEBUG_TYPE_REPRO): Add.
Use a separate iteration variable for inner loop (😊). This
generally prevented any debug directory entries after a
IMAGE_DEBUG_TYPE_CODEVIEW entry from being reported.
Don't leak the memory allocated for the section containing the debug
directory.
bfd/ChangeLog:
2020-01-16 Jon Turney <jon.turney@dronecode.org.uk>
* peXXigen.c (pe_print_debugdata): Fix the iteration variable for
inner loop. Fix a memory leak.
This patch fixes the neg/neg32 BPF instructions, which have K (=0)
instead of X (=1) in their header source bit, despite operating on
registes.
cpu/ChangeLog:
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-alu-insn-un): The unary BPF instructions
(neg and neg32) use OP_SRC_K even if they operate only in
registers.
opcodes/ChangeLog:
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-opc.c: Regenerate.
gas/ChangeLog:
2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Update expected opcode for `neg'.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise for `neg32'.
* testsuite/gas/bpf/alu32-be.d: Likewise.
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
Other than near returns these default to 32-bit operand size, and hence
it isn't really unlikely that 64-bit forms are meant. Hence these should
have disambiguating suffixes. In Intel mode, however, don't error in
these cases unconditionally - MASM accepts these without suffix _and_
without warning.
- 64-bit CALL permitting just a single operand size doesn't need it.
- FLDENV et al should never have had it.
It remains suspicious that a number of 64-bit only insns continue to
have the attribute, despite this being intended for .code16gcc handling
only.
Alan Modra
Tom de Vries
Simon Marchi
Rogerio Alves
Alok Kumar Sharma
GDB Administrator
Andreas Schwab
Maciej W. Rozycki
Lukas Durfina
Sergei Trofimovich
H.J. Lu
Gitea
Nick Clifton
Shahab Vahedi
Sandra Loosemore
Andre Vieira
Srinath Parvathaneni
Jan Beulich
Richard Sandiford
Tom Tromey
Andrew Burgess
Jon Turney
Jose E. Marchesi