6f8c0c4ccc
* tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,
...
CpuUnknown): Renumber
(CpuP4, CpuSSE2): New.
(CpuUnknownFlags): Add CpuP4 and CpuSSE2
* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
introduced by Pentium4
2001-01-03 15:36:26 +00:00
c0d8940f87
* configure.in: Add support for x86_64 and x86_64-*-linux-gnu*
...
* NEWS: Add x86_64.
* i386.h (i386_optab): Add "rex*" instructions;
add swapgs; disable jmp/call far direct instructions for
64bit mode; add syscall and sysret; disable registers for 0xc6
template. Add 'q' suffixes to extendable instructions, disable
obsoletted instructions, add new sign/zero extension ones.
(i386_regtab): Add extended registers.
(*Suf): Add No_qSuf.
(q_Suf, wlq_Suf, bwlq_Suf): New.
2000-12-30 18:05:10 +00:00
3e73aa7c95
* tc-i386.h (i386_target_format): Define even for ELFs.
...
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
a969366f78
* COPYING: Update to current
...
ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references
to 19yy as example year in copyright notice).
2000-12-19 22:01:20 +00:00
ca6d9fb3f0
* dis-asm.h (struct disassemble_info): New member "section".
...
(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member.
Initialize section member.
2000-12-18 23:19:55 +00:00
85ec56b3e2
fix formatting
2000-12-17 03:09:45 +00:00
328cd6e949
* safe-ctype.h: Make code work on all targets and not just on
...
targets where a char is 8 bits.
2000-12-17 03:09:01 +00:00
b79e8c7865
Add link option to allow undefiedn symbols in shared libraries
2000-12-12 20:53:02 +00:00
bf40d919f9
Fix Formatting.
2000-12-12 19:25:07 +00:00
ffb34d9aac
* hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux
...
compatibility.
2000-12-11 17:55:58 +00:00
f16b83dfe5
* tc-i386.c (md_assemble): Refuse 's' and 'l' suffixes in the intel
...
mode; convert 'd' suffix to 's' or 'l'; remove all DWORD_MNEM_SUFFIX
references.
(intel_e09_1): Convert QWORD to 'l' suffix for FP operations; refuse
otherwise.
* tc-i386.h (DWORD_MNEM_SUFFIX): Kill.
(No_dSuf): Kill.
* i386.h (*_Suf): Remove No_dSuf.
(d_suf, wld_Suf,sld_Suf, sldx_Suf, bwld_Suf, d_FP, sld_FP, sldx_FP)
Remove.
(i386_optab): Remove 'd' in the suffixes.
2000-12-11 14:01:46 +00:00
d58c3cb85e
Replace #warning with #error
2000-12-11 03:43:05 +00:00
39cd252546
Actually add safe-ctype.h
2000-12-08 03:28:41 +00:00
2c6c601812
* safe-ctype.h: New file.
2000-12-08 03:26:46 +00:00
0aec643be7
#warn -> #warning
2000-12-07 23:48:01 +00:00
324069ad94
* getopt.h obstack.h: Standarize copyright statement.
2000-12-07 02:06:09 +00:00
f93eaf706d
* demangle.h: Change "new_abi" to "v3" everywhere.
2000-12-05 16:49:47 +00:00
c6c98b3833
Add MIPS SB1 machine
2000-12-02 01:10:33 +00:00
84ea6cf2c5
Add MIPS V and MIPS 64 machine numbers
2000-12-02 00:55:22 +00:00
e7af610e14
Add MIPS32 as a seperate MIPS architecture
2000-12-01 21:35:38 +00:00
4372b67322
Improve MIPS32 support
2000-12-01 20:05:32 +00:00
abf1d184bd
Add x86-64 support files.
2000-11-30 19:05:18 +00:00
b13291a979
* libiberty.h: Move #includes to top. Prototype xmalloc_failed.
2000-11-29 20:14:48 +00:00
723b0f0d39
* common.h (e_machine numbers): Clarify comments to describe how
...
EM_* constants are assigned. Move EM_PJ from official section to
ad-hoc section.
(EM_CRIS): Correct comment to match official description.
(EM_MMIX): Ditto.
2000-11-27 21:52:56 +00:00
3ba3ce6627
Add new ELF ABI defines
2000-11-22 23:19:15 +00:00
1da80a8282
2000-11-20 H.J. Lu <hjl@gnu.org>
...
* common.h (ELFOSABI_MONTEREY): Renamed to ...
(ELFOSABI_AIX): This.
2000-11-20 23:45:42 +00:00
71517c7008
Update relocations per August psABI docs.
...
* ia64.h (R_IA64_SEGBASE): Remove.
(R_IA64_LTV*): Renumber to 0x74 to 0x77.
(R_IA64_EPLTMSB, R_IA64_EPLTLSB): Remove.
(R_IA64_TPREL14, R_IA64_TPREL64I): New.
(R_IA64_DTPMOD*): New.
(R_IA64_DTPREL*): New.
2000-11-16 22:48:14 +00:00
6e53a71409
Correct date and style of last entry
2000-11-15 12:01:15 +00:00
4cabd1d10f
* demangle.h: Add gnat and java demangle styles.
2000-11-15 11:47:51 +00:00
82e7f05e13
* hashtab.h (struct htab): Add member return_allocation_failure.
...
(htab_try_create): New prototype. Mention which functions may
return NULL when this is used.
2000-11-04 07:48:51 +00:00
6f72978879
* hashtab.h: Change void * to PTR where necessary.
2000-11-03 20:53:04 +00:00
19f7b01094
gas/
...
* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
instructions to loose any special insn->architecture mask.
* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
(sparc_md_end, sparc_arch_types, sparc_arch,
sparc_elf_final_processing): Handle v8plusb and v9b architectures.
(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
request v9b architecture if they are used).
bfd/
* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
elf32_sparc_object_p, elf32_sparc_final_write_processing):
Support v8plusb.
* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
sparc64_elf_object_p): Support v9b.
* archures.c: Declare v8plusb and v9b machines.
* bfd-in2.h: Ditto.
* cpu-sparc.c: Ditto.
include/opcode/
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
Note that '3' is used for siam operand.
opcodes/
* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
(compute_arch_mask): Add v8plusb and v9b machines.
(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
* opcodes/sparc-opc.c: Support for Cheetah instruction set.
(prefetch_table): Add #invalidate.
2000-10-20 10:38:47 +00:00
74bcd5294f
merge from gcc repository
2000-10-12 02:16:48 +00:00
b4db717d67
Correct date of checkin
2000-09-29 18:23:26 +00:00
fc7372e2a7
* dis-asm.h: Declare cris_get_disassembler, not print_insn_cris.
...
Fix typo in comment.
2000-09-29 18:07:47 +00:00
f680e9734e
* cris.h (EF_CRIS_UNDERSCORE): New.
2000-09-29 16:52:42 +00:00
6c26fec901
Add alloca-conf.h from libiberty.
2000-09-28 08:00:54 +00:00
47d89dba5e
.plt stub for lazy linking, --stub-group-size=N ld switch,
...
import stub fix, extra DIR14F reloc to fix abort in tc_gen_reloc
2000-09-27 17:30:19 +00:00
139368c9f3
Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.
...
gas/ChangeLog
* config/tc-ia64.c (dv_sem): Add "stop".
(specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now.
(specify_resource, case IA64_RS_PRr): New for regs 16 to 62.
(specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to
match above.
(mark_resources): Check IA64_RS_PRr.
gas/testsuite/ChangeLog
* gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/dv-imply.d: Regenerate.
* gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d,
gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l,
gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise.
include/opcode/ChangeLog
* ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP.
opcodes/ChangeLog
* ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change.
* ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP.
(lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62".
* ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update.
* ia64-asmtab.c: Regnerate.
2000-09-22 19:43:50 +00:00
32d070f0de
* sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT,
...
R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change
numbers to the range from 160 to 167.
(R_SH_FIRST_INVALID_RELOC): Adjust.
(R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2):
New relocs to fill in the gap.
2000-09-14 04:56:55 +00:00
156c2f8bf7
Add support for the MIPS32
2000-09-14 01:47:38 +00:00
6221ac1b93
* dyn-string.h: Adjust formatting.
...
(dyn_string_insert_char): New macro. New declaration.
2000-09-08 01:04:58 +00:00
3e9907faea
* md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX.
...
* md5.h: New file.
2000-09-08 01:03:08 +00:00
3c5ce02eb8
doco addition.
2000-09-05 05:22:24 +00:00
de98ed8b01
Add some reloc types.
2000-09-05 02:14:38 +00:00
b18903cb91
Add ARRAY_SIZE macro from egcs version
2000-09-03 17:35:07 +00:00
d155c6ea0b
Fix formatting, add copyright notice
2000-09-03 17:28:21 +00:00
6785ddd1ac
* sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT,
...
R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): New relocs.
(R_SH_FIRST_INVALID_RELOC): Adjust.
2000-09-02 02:24:02 +00:00
50b81f1903
Fix 3 DV bugs, and a few minor cleanups.
...
gas/
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
2000-08-16 23:20:15 +00:00
fc29466dba
2000-08-15 H.J. Lu <hjl@gnu.org>
...
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
IgnoreSize change.
2000-08-16 17:29:23 +00:00
Jan Hubicka
DJ Delorie
Hans-Peter Nilsson
Nick Clifton
Jeff Law
Alan Modra
Christopher Faylor
H.J. Lu
Richard Henderson
Jakub Jelinek
Jim Wilson
Alexandre Oliva