2005-04-01 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (md_apply_fix3): Also handle BFD_RELOC_X86_64_32S.
(tc_gen_reloc): Handle BFD_RELOC_X86_64_32S in the default case.
gas/testsuite/
2005-04-01 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-pcrel.[sd]: New.
* gas/i386/i386.exp: Run new test.
* bfd/bfd-in2.h: Regenerate.
* bfd/elf32-arm.c (elf32_arm_is_target_special_symbol): Rename call to
bfd_elf32_is_arm_mapping_symbol_name.
(elf32_arm_output_symbol_hook): Likewise.
(arm_elf_find_function): Likewise, and include STT_NOTYPE in test for
mapping symbols.
(is_arm_mapping_symbol_name): Function moved from here...
* bfd/cpu-arm.c (bfd_elf32_is_arm_mapping_symbol_name): ...to here,
renamed and made global.
* gas/config/tc-arm.c (mapping_state): Change documentation in function
comment to cross-reference spec instead. Change type of mapping symbols
to BSF_NO_TYPE.
(arm_adjust_symtab): Don't change type of mapping symbols here.
* gas/testsuite/gas/arm/mapping.d: Update expected output.
* ld/testsuite/ld-arm/arm-app-abs32.d: Likewise.
* ld/testsuite/ld-arm/arm-app.d: Likewise.
* ld/testsuite/ld-arm/mixed-app.d: Likewise.
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
x86-64-segment and x86-64-inval-seg for x86-64.
* gas/i386/intel.d: Expect movw for moving between memory and
segment register.
* gas/i386/naked.d: Likewise.
* gas/i386/opcode.d: Likewise.
* gas/i386/x86-64-opcode.d: Likewise.
* gas/i386/opcode.s: Use movw for moving between memory and
segment register.
* gas/i386/x86-64-opcode.s: Likewise.
* : Likewise.
* gas/i386/inval-seg.l: New.
* gas/i386/inval-seg.s: New.
* gas/i386/segment.l: New.
* gas/i386/segment.s: New.
* gas/i386/x86-64-inval-seg.l: New.
* gas/i386/x86-64-inval-seg.s: New.
* gas/i386/x86-64-segment.l: New.
* gas/i386/x86-64-segment.s: New.
include/opcode/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Don't allow the `l' suffix for moving
moving between memory and segment register. Allow movq for
moving between general-purpose register and segment register.
opcodes/
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SEG_Fixup): New.
(Sv): New.
(dis386): Use "Sv" for 0x8c and 0x8e.
indicates whether personality routine index N has been output for this
section.
(mapping_state): tc_segment_info_data now struct not enum.
(arm_elf_change_section): Likewise, and marked_pr_dependency is now
handled on section change.
(create_unwind_entry): Previous code to output dependency removed.
(s_arm_unwind_fnend): Output dependency if it hasn't been done already
for this section.
* gas/config/tc-arm.h (TC_SEGMENT_INFO_TYPE): Redefined as struct
arm_segment_info_type.
(arm_segment_info_type): New struct.
* gas/testsuite/gas/arm/unwind.d: Update expected output.
(xtensa_frob_label): Compute "freq" before possibly switching frags.
Insert a LOOP_END frag before every loop target, and do not overload
DESIRE_ALIGN_IF_TARGET frags with loop end information.
(xg_assemble_vliw_tokens): Use do_align_targets.
(xtensa_fix_target_frags): Remove code to convert a
DESIRE_ALIGN_IF_TARGET frag to a LOOP_END frag when there is a
negatable branch at the end of a loop.
(frag_can_negate_branch): Delete.
(xg_symbolic_immeds_fit): Check for direct calls and return TRUE if
the use_longcalls flag is set. Do this before checking the segment.
(xg_expand_assembly_insn): Rearrange to use new do_expand flag. Never
expand direct calls at this point.
(xtensa_set_frag_assembly_state): Set use_longcalls flag.
(xtensa_find_unmarked_state_frags): Likewise.
(md_assemble): Do not disable longcalls by setting is_specific_opcode.
(xg_assemble_vliw_tokens): Switch frags when use_longcalls changes.
(convert_frag_immed): Remove unnecessary check of is_specific_opcode.
* config/tc-xtensa.h (xtensa_frag_type): Add use_longcalls flag.
* config/tc-cris.c: Ditto.
(md_estimate_size_before_relax): Remove obsolete comment for
parameter "segment_type".
(md_begin): Document reason for cast of hash_insert argument.
(md_atof): Correct type of parameter "type".
xg_apply_fix_value and return a value to indicate success.
(md_pcrel_from): Skip check of fx_done. Return 0 if not PC-relative.
(xtensa_force_relocation): Remove checks for VTABLE relocs.
(xtensa_validate_fix_sub): New.
(xtensa_fix_adjustable): Remove check for external or weak symbols.
(tc_gen_reloc): Move code to handle difference of symbols and code to
apply tentative fix values to ...
(md_apply_fix3): ...here. Enable standard overflow checks for simple
8, 16, and 32 bit relocations. Apply fixes for slot-specific
relocations when linkrelax flag is not set.
* config/tc-xtensa.h (xtensa_validate_fix_sub): Add prototype.
(TC_FORCE_RELOCATION_SUB_SAME, TC_VALIDATE_FIX_SUB): Define.
2005-03-17 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (i386_scale): Beautify error message.
(Intel syntax comments): Update.
(struct intel_parser_s): Add fields in_offset, in_bracket, and
next_operand.
(intel_e04_1, intel_e05_1, intel_e05_1, intel_e09_1, intel_e10_1):
Remove declarations.
(intel_bracket_expr): Declare.
(i386_intel_operand): Initialize new intel_parser fields. Wrap most
of the function body in a loop allowing to split an operand into two.
Replace calls to malloc and checks of it returning non-NULL with
calls to xmalloc/xstrdup.
(intel_expr): SHORT no longer handled here. Add comment indicating
comparison ops need implementation.
(intel_e04, intel_e04_1): Combine, replace recursion with loop.
Check right operand of - does not specify a register when parsing
the address of a memory reference.
(intel_e05, intel_e05_1): Combine, replace recursion with loop.
Check operands do not specify a register when parsing the address of
a memory reference.
(intel_e06, intel_e06_1): Likewise.
(intel_e09, intel_e09_1): Combine, replace recursion with loop. Also
handle SHORT as well as unary + and -. Don't accept : except for
segment overrides or in direct far jump/call insns.
(intel_brack_expr): New.
(intel_e10, intel_e10_1): Combine, replace recursion with loop. Use
intel_brack_expr.
(intel_e11): Replace chain of if/else-if by switch, alloing fall-
through in certain cases. Use intel_brack_expr. Add new diagnostics.
Allow symbolic constants as register scale value.
(intel_get_token): Replace call to malloc and check of return value
with call to xmalloc. Change handling for FLAT to match MASM's.
(intel_putback_token): Don't try to back up/free current token if
that is T_NIL.
gas/testsuite/
2005-03-17 Jan Beulich <jbeulich@novell.com>
* gas/i386/intel.d: Add stderr directive.
* gas/i386/intel.e: New.
* gas/i386/intel16.d: Add stderr directive. Adjust for changed
source.
* gas/i386/intel16.e: New.
* gas/i386/intel16.s: Add instances of addressing forms with base
and index specified in reverse order.
* gas/i386/intelbad.l: Adjust for changed source.
* gas/i386/intelbad.s: Add more operand forms to check.
* gas/i386/intelok.d: Remove -r from objdump options. Add stderr
directive. Adjust for changed source.
* gas/i386/intelok.e: New.
* gas/i386/intelok.s: Define MASM constants byte, word, etc. Add
more operand forms to check.
* gas/i386/x86_64.d: Add stderr directive.
* gas/i386/x86_64.e: New.
* gas/i386/x86_64.s: Adjust for parser changes.
* ppc-opc.c (insert_sprg, extract_sprg): New Functions.
(powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
(SPRG_MASK): Delete.
(XSPRG_MASK): Mask off extra bits now part of sprg field.
(powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
mfsprg4..7 after msprg and consolidate.
gas/testsuite
* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
* gas/ppc/booke.d: Likewise.
Jan Beulich
Julian Brown
Aaron W. LaFramboise
H.J. Lu
Daniel Jacobowitz
Bob Wilson
Ian Lance Taylor
Hans-Peter Nilsson
Nick Clifton
Jim Blandy
Alan Modra
Maciej W. Rozycki
Zack Weinberg
Eric Christopher
Aldy Hernandez
Richard Sandiford