Nick Clifton
48c9f030c9
Add support for CRX co-processor opcodes
2004-10-07 14:18:17 +00:00
Nick Clifton
0dd132b63c
Apply Paul Brook's patch to implement armv6k instructions
2004-09-30 16:21:50 +00:00
Marek Michalkiewicz
23794b24aa
* gas/config/tc-avr.c: Add support for
...
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
* include/opcode/avr.h: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2004-09-11 13:15:05 +00:00
Alan Modra
2a309db040
opcodes/
...
* ppc-opc.c (L): Make this field not optional.
include/opcode/
* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2004-09-09 12:42:37 +00:00
Nick Clifton
b18c562e39
Apply Dmitry Diky's patches to add relaxation to msp430.
2004-08-25 12:54:15 +00:00
Nick Clifton
45d313cd66
O_JSR): Do not allow VECIND addressing for non-SX processors.
2004-08-13 08:14:02 +00:00
Michal Ludvig
30d1c83669
Added new instructions for next version of VIA PadLock core.
2004-07-30 12:36:38 +00:00
H.J. Lu
9a45f1c2c4
2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
...
* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2004-07-22 19:10:49 +00:00
Nick Clifton
543613e933
For DefaultSize instructions, don't guess a 'q' suffix if the instruction
...
doesn't support it.
2004-07-21 18:18:04 +00:00
Richard Earnshaw
b781e55836
* arm.h: Remove all old content. Replace with architecture defines
...
from gas/config/tc-arm.c.
2004-07-16 21:59:35 +00:00
Andreas Schwab
8577e690b5
binutils/testsuite/:
...
* binutils-all/m68k/movem.s: New file.
* binutils-all/m68k/objdump.exp: New file.
include/opcode/:
* m68k.h: Fix comment.
opcodes/:
* m68k-dis.c (m68k_valid_ea): Check validity of all codes.
2004-07-09 18:42:14 +00:00
Nick Clifton
1fe1f39c06
Add new port: crx-elf
2004-07-07 17:28:53 +00:00
Alan Modra
1d9f512f33
include/opcode/
...
* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
opcodes/
* i386-dis.c (x_mode): Comment.
(two_source_ops): File scope.
(float_mem): Correct fisttpll and fistpll.
(float_mem_mode): New table.
(dofloat): Use it.
(OP_E): Correct intel mode PTR output.
(ptr_reg): Use open_char and close_char.
(PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
operands. Set two_source_ops.
gas/testsuite/
* gas/i386/prescott.s: Remove fisttpd and fisttpq.
* gas/i386/prescott.d: Update.
2004-06-23 15:06:58 +00:00
Nick Clifton
be8c092bb0
Reorganise m68k instruction decoding and improve handling of MAC/EMAC
2004-05-24 14:33:22 +00:00
Nick Clifton
6b6e92f432
Add support for 521x,5249,547x,548x.
2004-05-05 14:33:14 +00:00
Nick Clifton
fd99574ba5
Add support for ColdFire MAC instructions and tidy up support for other m68k
...
variants.
2004-04-22 10:33:16 +00:00
H.J. Lu
3922a64ca2
Reorder it.
2004-03-20 23:44:18 +00:00
H.J. Lu
83afed5481
Correct the ChangeLog entry.
2004-03-20 23:36:18 +00:00
Alan Modra
fdd12ef3c6
opcodes/
...
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 00:58:43 +00:00
Michal Ludvig
1f45d98889
2004-03-12 Michal Ludvig <mludvig@suse.cz>
...
* i386.h (i386_optab): Added xstore as an alias for xstorerng.
2004-03-12 13:38:46 +00:00
Michal Ludvig
0f10071e3d
2004-03-12 Michal Ludvig <mludvig@suse.cz>
...
* gas/config/tc-i386.c (output_insn): Handle PadLock instructions.
* gas/config/tc-i386.h (CpuPadLock): New define.
(CpuUnknownFlags): Added CpuPadLock.
* include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns.
* opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
(padlock_table): New struct with PadLock instructions.
(print_insn): Handle PADLOCK_SPECIAL.
2004-03-12 10:14:29 +00:00
Nick Clifton
3255318a04
Add support for relaxing the 32bit ldc/stc instructions.
2004-02-09 12:15:57 +00:00
Nick Clifton
ca9a79a174
Add support for relaxation of bit manipulation instructions.
2004-01-12 15:02:22 +00:00
Nick Clifton
875a0b1471
(BITOP): Dissallow operations on @aa:16 and @aa:32 except for the H8S.
2004-01-09 17:47:17 +00:00
Alan Modra
c9e214e571
Split ChangeLog files.
2004-01-02 11:16:21 +00:00
Nick Clifton
3e60263266
Add ColfFire v4 support
2003-10-21 13:28:59 +00:00
Hans-Peter Nilsson
906e88d4fb
* mmix.h (JMP_INSN_BYTE): Define.
2003-10-19 01:16:56 +00:00
Chris Demetriou
5f74bc130d
[ bfd/ChangeLog ]
...
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* archures.c (bfd_mach_mipsisa64r2): New define.
* bfd-in2.h: Regenerate.
* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
* cpu-mips.c (I_mipsisa64r2): New enum value.
(arch_info_struct): Add entry for I_mipsisa64r2.
* elfxx-mips.c (_bfd_elf_mips_mach)
(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.
[ binutils/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.
[ gas/Changelog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
* configure: Regenerate.
* config/tc-mips.c (imm2_expr): New variable.
(md_assemble, mips16_ip): Initialize imm2_expr.
(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
(macro): Handle M_DEXT and M_DINS.
(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
(mips_ip): Likewise.
(OPTION_MIPS64R2): New define.
(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
(md_parse_option): Handle OPTION_MIPS64R2.
(s_mipsset): Handle setting "mips64r2" ISA.
(mips_cpu_info_table): Add mips64r2.
(md_show_usage): Document -mips64r2 option.
* doc/as.texinfo: Docuemnt -mips64r2 option.
* doc/c-mips.texi: Likewise.
[ gas/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips64r2.d: New file.
* gas/mips/cp0sel-names-mips64r2.d: New file.
* gas/mips/elf_arch_mips64r2.d: New file.
* gas/mips/hwr-names-mips64r2.d: New file.
* gas/mips/mips32r2-ill-fp64.l: New file.
* gas/mips/mips32r2-ill-fp64.s: New file.
* gas/mips/mips64r2-ill.l: New file.
* gas/mips/mips64r2-ill.s: New file.
* gas/mips/mips64r2.d: New file.
* gas/mips/mips64r2.s: New file.
* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.
[ include/elf/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h (E_MIPS_ARCH_64R2): New define.
[ include/opcode/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips.h: Document +E, +F, +G, +H, and +I operand types.
Update documentation of I, +B and +C operand types.
(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
(M_DEXT, M_DINS): New enum values.
[ ld/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ldmain.c (get_emulation): Ignore "-mips64r2".
[ ld/testsuite/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
with MIPS64r2.
[ opcodes/ChangeLog ]
2003-09-30 Chris Demetriou <cgd@broadcom.com>
* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
(print_insn_args): Add handing for +E, +F, +G, and +H.
* mips-opc.c (I65): New define for MIPS64r2.
(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to
be supported on MIPS64r2.
2003-09-30 16:17:15 +00:00
Nick Clifton
8ad30312ff
Add binutils support for v850e1 processor
2003-09-04 11:04:38 +00:00
Alan Modra
68d23d2157
* ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
...
PPC_OPCODE_* defines.
2003-08-19 07:08:20 +00:00
Jason Eckhardt
be6389fdef
include/opcode/ChangeLog:
...
2003-08-16 Jason Eckhardt <jle@rice.edu>
* i860.h (fmov.ds): Expand as famov.ds.
(fmov.sd): Expand as famov.sd.
(pfmov.ds): Expand as pfamov.ds.
gas/testsuite/ChangeLog:
2003-08-16 Jason Eckhardt <jle@rice.edu>
* gas/i860/pseudo-ops01.{s,d}: New files.
* gas/i860/i860.exp: Execute the new test above.
* gas/i860/README.i860: Mention that pseudo-ops need more testing
and remove the align fill defect from the list.
2003-08-17 03:16:23 +00:00
Michael Meissner
10e05405ac
Convert cgen to C-90
2003-08-08 21:21:24 +00:00
Alan Modra
8cf3f35467
Convert to C90.
2003-08-07 02:25:50 +00:00
Michael Snyder
7951f401ae
2003-07-18 Michael Snyder <msnyder@redhat.com>
...
* include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
2003-07-29 21:05:31 +00:00
Richard Sandiford
5a7ea74950
include/opcode/
...
* mips.h (CPU_RM7000): New macro.
(OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.
bfd/
* archures.c (bfd_mach_mips7000): New.
* bfd-in2.h: Regenerated.
* cpu-mips.c (arch_info_struct): Add an entry for mips:7000.
* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000.
(mips_mach_extensions): Add an entry for it.
opcodes/
* mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries.
gas/
* config/tc-mips.c (hilo_interlocks): True for CPU_RM7000.
(mips_cpu_info_table): Add rm7000 and rm9000 entries.
gas/testsuite/
* gas/mips/rm7000.[sd]: New test.
* gas/mips/mips.exp: Run it.
2003-07-15 07:50:39 +00:00
Alexandre Oliva
7ba1864d6b
2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
...
* mn10300.h (AM33_2): Renamed from AM33.
2000-03-31 Alexandre Oliva <aoliva@cygnus.com>
* mn10300.h (AM332, FMT_D3): Defined.
(MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise.
(MN10300_OPERAND_FPCR): Likewise.
2003-07-10 02:49:07 +00:00
Martin Schwidefsky
c72a8f697c
* s390.h (s390_opcode_cpu_val): Add enum for cpu type z990.
2003-07-01 14:46:57 +00:00
Richard Sandiford
2d0d09ca83
include/opcode/
...
* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
(IMM8U, IMM8U_NS): Define.
(h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
gas/
* config/tc-h8300.c (get_specific): Allow ':8' to be used for
unsigned 8-bit operands.
gas/testsuite/
* gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy.
2003-06-25 15:31:59 +00:00
Richard Sandiford
8d1e520a64
* include/opcode/h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd
...
and mov.l ERs,@(dd:32,ERd) entries.
2003-06-25 15:19:40 +00:00
H.J. Lu
ca164297eb
gas/
...
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
Instructions.
* gas/config/tc-i386.h (CpuPNI): New.
(CpuUnknownFlags): Add CpuPNI.
gas/testsuite/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Add prescott.
* gas/i386/prescott.d: New file.
* gas/i386/prescott.s: Likewise.
include/opcode/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Support Intel Precott New Instructions.
opcodes/
2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
Intel Precott New Instructions.
(PREGRP27): New. Added for "addsubpd" and "addsubps".
(PREGRP28): New. Added for "haddpd" and "haddps".
(PREGRP29): New. Added for "hsubpd" and "hsubps".
(PREGRP30): New. Added for "movsldup" and "movddup".
(PREGRP31): New. Added for "movshdup" and "movhpd".
(PREGRP32): New. Added for "lddqu".
(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
entry 0xd0. Use PREGRP32 for entry 0xf0.
(twobyte_has_modrm): Updated.
(twobyte_uses_SSE_prefix): Likewise.
(grps): Use PNI_Fixup in the "sidtQ" entry.
(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
PREGRP31 and PREGRP32.
(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
Use "fisttpll" in entry 1 in opcode 0xdd.
Use "fisttp" in entry 1 in opcode 0xdf.
2003-06-23 20:15:34 +00:00
Michael Snyder
50649e423e
Fix typo.
2003-06-19 02:56:24 +00:00
Alan Modra
adadcc0cc9
Add "attn", "lq" and "stq" power4 insns.
2003-06-10 07:44:11 +00:00
Richard Sandiford
2a93846b50
include/opcode/
...
* h8300.h (IMM4_NS, IMM8_NS): New.
(h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l.
gas/testsuite
* gas/h8300/h8sx_mov_imm.[sd]: New test.
* gas/h8300/h8300.exp: Run it.
2003-06-10 07:33:46 +00:00
Michael Snyder
66f2268e0d
2003-06-03 Michael Snyder <msnyder@redhat.com>
...
* h8sx.h (enum h8_model): Add AV_H8S to distinguish from H8H.
(ldc): Split ccr ops from exr ops (which are only available
on H8S or H8SX).
(stc): Ditto.
(andc, orc, xorc): Ditto.
(ldmac, stmac, clrmac, mac): Change access to AV_H8S.
2003-06-05 18:47:12 +00:00
Michael Snyder
5f250e29bf
2003-06-03 Michael Snyder <msnyder@redhat.com>
...
and Bernd Schmidt <bernds@redhat.com>
and Alexandre Oliva <aoliva@redhat.com>
* h8300.h: Add support for h8300sx instruction set.
2003-06-03 21:23:21 +00:00
Jason Eckhardt
14218d5f24
2003-05-23 Jason Eckhardt <jle@rice.edu>
...
gas:
* config/tc-i860.c (target_xp): Declare variable.
(OPTION_XP): Declare macro.
(md_longopts): Add option -mxp.
(md_parse_option): Set target_xp.
(md_show_usage): Add -mxp usage.
(i860_process_insn): Recognize XP registers bear, ccr, p0-p3.
(md_assemble): Don't try expansions if XP_ONLY is set.
* doc/c-i860.texi: Document -mxp option.
gas/testsuite:
* gas/i860/xp.s: New file.
* gas/i860/xp.d: New file.
include/opcode:
* i860.h (expand_type): Add XP_ONLY.
(scyc.b): New XP instruction.
(ldio.l): Likewise.
(ldio.s): Likewise.
(ldio.b): Likewise.
(ldint.l): Likewise.
(ldint.s): Likewise.
(ldint.b): Likewise.
(stio.l): Likewise.
(stio.s): Likewise.
(stio.b): Likewise.
(pfld.q): Likewise.
opcodes:
* i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
(print_insn_i860): Grab 4 bits of the control register field
instead of 3.
2003-05-24 04:22:23 +00:00
Jason Eckhardt
941bbe7882
2003-05-20 Jason Eckhardt <jle@rice.edu>
...
opcode/i860.h (flush): Set lower 3 bits properly and use 'L'
for the immediate operand type instead of 'i'.
2003-05-21 05:06:49 +00:00
Jason Eckhardt
ca464f3718
2003-05-20 Jason Eckhardt <jle@rice.edu>
...
opcode/i860.h (fzchks): Both S and R bits must be set.
(pfzchks): Likewise.
(faddp): Likewise.
(pfaddp): Likewise.
(fix.ss): Remove (invalid instruction).
(pfix.ss): Likewise.
(ftrunc.ss): Likewise.
(pftrunc.ss): Likewise.
2003-05-21 02:06:40 +00:00
Jason Eckhardt
b645cb1726
2003-05-18 Jason Eckhardt <jle@rice.edu>
...
gas:
* config/tc-i860.c (i860_process_insn): Initialize fc after
each opcode mismatch.
include/opcode:
* i860.h (form, pform): Add missing .dd suffix.
opcodes:
* i860-dis.c (print_insn_i860): Instruction shrd has a dual bit,
print it.
bfd:
* elf32-i860.c (elf32_i860_relocate_highadj): Simplify calculation.
2003-05-18 21:24:33 +00:00
Stephane Carrez
87a45149d4
* m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000
2003-05-13 19:28:14 +00:00