Commit Graph

34 Commits

Author SHA1 Message Date
Nick Clifton fd7ed446fb Add support for FMLA (by element) to AArch64 sim.
* simulator.c (do_FMLA_by_element): New function.
	(do_vec_op2): Call it.
2016-05-06 10:35:33 +01:00
Nick Clifton 2cdad34c4f Add support for the --trace-decode option to the AArch64 simulator.
* simulator.c: Add TRACE_DECODE statements to all emulation
	functions.
2016-04-27 11:39:14 +01:00
Nick Clifton 67f101eece Ignore DWARF debug information with a version of 0 - assume that it is padding.
PR 19872
bfd	* dwarf2.c (parse_comp_unit): Skip warning about unrecognised
	version number if the version is zero.

bin	* dwarf.c (display_debug_aranges): Skip warning about unrecognised
	version number if the version is zero.
2016-04-04 12:53:33 +01:00
Nick Clifton 7517e550ce Fix more bugs in AArch64 simulator.
* cpustate.c (aarch64_set_reg_s32): New function.
	(aarch64_set_reg_u32): New function.
	(aarch64_get_FP_half): Place half precision value into the correct
	slot of the union.
	(aarch64_set_FP_half): Likewise.
	* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
	aarch64_set_reg_u32.
	* memory.c (FETCH_FUNC): Cast the read value to the access type
	before converting it to the return type.  Rename to FETCH_FUNC64.
	(FETCH_FUNC32): New macro.  Duplicates FETCH_FUNC64 but for 32-bit
	accesses.  Use for 32-bit memory access functions.
	* simulator.c (ldrsb_wb): Use sign extension not zero extension.
	(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
	(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
	(ldrsh_scale_ext, ldrsw_abs): Likewise.
	(ldrh32_abs): Store 32 bit value not 64-bits.
	(ldrh32_wb, ldrh32_scale_ext): Likewise.
	(do_vec_MOV_immediate): Fix computation of val.
	(do_vec_MVNI): Likewise.
	(DO_VEC_WIDENING_MUL): New macro.
	(do_vec_mull): Use new macro.
	(do_vec_mul): Use new macro.
	(do_vec_MLA): Read values before writing.
	(do_vec_xtl): Likewise.
	(do_vec_SSHL): Select correct shift value.
	(do_vec_USHL): Likewise.
	(do_scalar_UCVTF): New function.
	(do_scalar_vec): Call new function.
	(store_pair_u64): Treat reads of SP as reads of XZR.
2016-03-30 10:29:04 +01:00
Nick Clifton ef0d8ffc45 Tidy up AArch64 simulator code.
* cpustate.c: Remove space after asterisk in function parameters.
	* decode.h (greg): Delete unused function.
	(vreg, shift, extension, scaling, writeback, condcode): Likewise.
	* simulator.c: Use INSTR macro in more places.
	(HALT_NYI): Use sim_io_eprintf in place of fprintf.
	Remove extraneous whitespace.
2016-03-29 11:34:22 +01:00
Nick Clifton 5ab6d79e70 More AArch64 simulator improvements.
* cpustate.c (aarch64_get_FP_half): New function.  Read a vector
	register as a half precision floating point number.
	(aarch64_set_FP_half): New function.  Similar, but for setting
	a half precision register.
	(aarch64_get_thread_id): New function.  Returns the value of the
	CPU's TPIDR register.
	(aarch64_get_FPCR): New function.  Returns the value of the CPU's
	floating point control register.
	(aarch64_set_FPCR): New function.  Set the value of the CPU's FPCR
	register.
	* cpustate.h: Add prototypes for new functions.
	* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
	* memory.c: Use unaligned core access functions for all memory
	reads and writes.
	* simulator.c (HALT_NYI): Generate an error message if tracing
	will not tell the user why the simulator is halting.
	(HALT_UNREACHABLE): Delete.  Delete (unneeded) uses of the macro.
	(INSTR): New time-saver macro.
	(fldrb_abs): New function.  Loads an 8-bit value using a scaled
	offset.
	(fldrh_abs): New function.  Likewise for 16-bit values.
	(do_vec_SSHL): Allow for negative shift values.
	(do_vec_USHL): Likewise.
	(do_vec_SHL): Correct computation of shift amount.
	(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
	shifts and computation of shift value.
	(clz): New function.  Counts leading zero bits.
	(do_vec_CLZ): New function.  Implements CLZ (vector).
	(do_vec_MOV_element): Call do_vec_CLZ.
	(dexSimpleFPCondCompare): Implement.
	(do_FCVT_half_to_single): New function.  Implements one of the
	FCVT operations.
	(do_FCVT_half_to_double): New function.  Likewise.
	(do_FCVT_single_to_half): New function.  Likewise.
	(do_FCVT_double_to_half): New function.  Likewise.
	(dexSimpleFPDataProc1Source): Call new FCVT functions.
	(do_scalar_SHL): Handle negative shifts.
	(do_scalar_shift): Handle SSHR.
	(do_scalar_USHL): New function.
	(do_double_add): Simplify to just performing a double precision
	add operation.  Move remaining code into...
	(do_scalar_vec): ... New function.
	(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
	functions.
	(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
	registers.
	(system_set): New function.
	(do_MSR_immediate): New function.  Stub for now.
	(do_MSR_reg): New function.  Likewise. Partially implements MSR
	instruction.
	(do_SYS): New function.  Stub for now,
	(dexSystem): Call new functions.
2016-03-23 17:37:30 +00:00
Nick Clifton 87bba7a5e0 Fix thinko in new GET_VEC_ELEMENT macro.
* cpustate.c: (GET_VEC_ELEMENT): And fix thinko using macro arguments.
2016-03-18 17:08:27 +00:00
Nick Clifton 4c0ca98e58 Fix code to check for illegal element numbers when accessing AArch64 vector registers in AArch64 sim.
* cpustate.c (GET_VEC_ELEMENT): Fix off by one error checking
	for an invalid element index.
	(SET_VEC_ELEMENT): Likewise.
2016-03-18 14:46:42 +00:00
Nick Clifton e101a78be9 Add simulation of MUL and NEG instructions to AArch64 simulator.
* cpustate.c: Remove spurious spaces from TRACE strings.
	Print hex equivalents of floats and doubles.
	Check element number against array size when accessing vector
	registers.
	* memory.c: Trace memory reads when --trace-memory is enabled.
	Remove float and double load and store functions.
	* memory.h (aarch64_get_mem_float): Delete prototype.
	(aarch64_get_mem_double): Likewise.
	(aarch64_set_mem_float): Likewise.
	(aarch64_set_mem_double): Likewise.
	* simulator (IS_SET): Always return either 0 or 1.
	(IS_CLEAR): Likewise.
	(fldrs_pcrel): Load and store floats using 32-bit memory accesses
	and doubles using 64-bit memory accesses.
	(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
	(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
	(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
	(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
	(store_pair_double, load_pair_float, load_pair_double): Likewise.
	(do_vec_MUL_by_element): New function.
	(do_vec_op2): Call do_vec_MUL_by_element.
	(do_scalar_NEG): New function.
	(do_double_add): Call do_scalar_NEG.
2016-03-18 09:32:32 +00:00
Nick Clifton 57aa174243 Fix bugs in the simulation of the AArch64's ADDP, FADDP, LD1, CCMP and CCMP instructions.
* simulator.c (set_flags_for_sub32): Correct type of signbit.
	(CondCompare): Swap interpretation of bit 30.
	(DO_ADDP): Delete macro.
	(do_vec_ADDP): Copy source registers before starting to update
	destination register.
	(do_vec_FADDP): Likewise.
	(do_vec_load_store): Fix computation of sizeof_operation.
	(rbit64): Fix type of constant.
	(aarch64_step): When displaying insn value, display all 32 bits.
2016-03-03 15:22:53 +00:00
Mike Frysinger ce39bd3890 sim: move many common settings from CPPFLAGS to config.h
Rather than stuffing the command line with a bunch of -D flags, start
moving things to config.h which is managed by autoheader.  This makes
the makefile a bit simpler and the build output tighter, and it makes
the migration to automake easier as there are fewer vars to juggle.

We'll want to move the other options out too, but it'll take more work.
2016-01-10 18:54:41 -05:00
Mike Frysinger e19418e02e sim: drop unused SIM_AC_OPTION_PACKAGES
This was imported from the ppc sim, but that was only used to control
a single file, and that is already governed by the hw models.  There's
no need to have a sep configure option here, especially since none of
the other sims are using it.  Even when the code is enabled, there's
no runtime overhead.
2016-01-10 17:54:04 -05:00
Mike Frysinger 16f7876d71 sim: allow the environment configure option everywhere
Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in
order to make the configure flag available.  There's no real reason
to not allow this flag for all ports, so move it to the common sim
macro.  This way we get standard behavior across all ports too.
2016-01-10 17:03:36 -05:00
Mike Frysinger 35656e9521 sim: allow the assert configure option everywhere
Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order
to make the configure flag available, which none of them do.  There's
no real reason to not allow this flag for all ports, so move it to the
common sim macro.  This way we get standard behavior across all ports.
2016-01-10 16:13:13 -05:00
Mike Frysinger 99d8e87993 sim: drop targ-vals.def->nltvals.def indirection
We don't have alternative nltvals.def files, so always symlinking
the targ-vals.def file to it doesn't gain us anything.  It does
make the build more complicated though and a pain to convert to
something newer (like automake).  Drop the symlinking entirely.

In the future, we'll want to explode this file anyways into the
respective arch dirs so things can be selected dynamically at
runtime, so it's not like we'll be bringing this back.
2016-01-10 04:01:16 -05:00
Mike Frysinger 347fe5bb86 sim: allow the inline configure option everywhere
Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order
to make the configure flag available.  There's no real reason to not
allow this flag for all ports, so move it to the common sim macro.
This way we get standard behavior across all ports too.
2016-01-10 03:36:32 -05:00
Mike Frysinger 0dc73ef7c3 sim: drop --enable-sim-{regparm,stdcall} options
These options were never exposed for most sims (just the ppc one),
and they are really only useful on 32-bit x86 systems.  Considering
modern systems tend to be 64-bit x86_64 and how well modern compilers
are at optimizing code, these have outlived their usefulness.
2016-01-10 03:15:01 -05:00
Mike Frysinger 22be3fbeac sim: drop --enable-sim-cflags option
No other sub directory provides such a configuration option, so
drop it from the sim dir as well.  This cleans up a good bit of
code in the process.

If people want to use custom flags for just the sim, they can
still run configure+make by hand in the sim subdir and use the
normal CFLAGS settings.
2016-01-10 02:54:59 -05:00
Mike Frysinger 936df7568a sim: drop common/cconfig.h in favor of a single config.h
The common subdir sets up a cconfig.h file to hold checks for the common
code.  In practice, most files still end up using config.h instead which
just leads to confusion.

Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON
so we can drop the cconfig.h file altogether.  Now there is only a single
config.h file like normal.
2016-01-09 03:52:30 -05:00
Mike Frysinger 2e3d4f4d5d sim: sim_{create_inferior,open,parse_args}: constify argv/env slightly
2016-01-03  Mike Frysinger  <vapier@gentoo.org>

	* sim-options.c (sim_parse_args): Mark argv array const.
	* sim-options.h (sim_parse_args): Likewise.
2016-01-06 21:48:59 -05:00
Mike Frysinger 1a846c6262 sim: aarch64: switch to common disassembler tracing
The output should largely be the same.
2016-01-05 14:37:46 -05:00
Mike Frysinger bc273e1751 sim: unify min/max macros
Import defines from gdb/defs.h to the sim core so we can delete the
various copies that already exist.
2016-01-04 22:24:03 -05:00
Tristan Gingold ac8eefeb24 sim: aarch64: drop syscall.h include to fix build
The simulator is including syscall.h which is not standard and apparently
not required (builds correctly without it on my machine).
2016-01-04 20:09:24 -05:00
Mike Frysinger 9bbf6f91c6 sim: punt x86-specific bswap logic
The compiler/C library should produce reasonable code for htonl/ntohl,
and at least glibc tries pretty hard to always produce good code for
them.  This logic only had support for 32-bit x86 systems anymore, and
it's unlikely people were even opting into this, so drop it all.
2016-01-04 05:04:30 -05:00
Mike Frysinger 0cb8d8513c sim: drop host endian configure option
The --enable-sim-hostendian flag was purely so people had an escape route
for when cross-compiling.  This is because historically, AC_C_BIGENDIAN
did not work in those cases.  That was fixed a while ago though, so we can
require that macro everywhere now and simplify a good bit of code.
2016-01-03 00:52:51 -05:00
Mike Frysinger 1ac72f0659 sim: convert to bfd_endian
Rather than re-invent endian defines, as well as maintain our own list
of OS & arch-specific includes, punt all that logic in favor of the bfd
ones already set up and maintained elsewhere.  We already rely on the
bfd library, so leveraging the endian aspect should be fine.
2016-01-03 00:18:07 -05:00
Joel Brobecker 618f726fcb GDB copyright headers update after running GDB's copyright.py script.
gdb/ChangeLog:

        Update year range in copyright notice of all files.
2016-01-01 08:43:22 +04:00
Mike Frysinger 5d01527536 sim: aarch64/msp430: fix disassembler usage
The disasm framework reserves the private_data field for the disassemblers
themselves, not for people who use the disassembler.  Instead, there is an
application_data field for callers such as the sim.  Switch to it to avoid
random corruption/crashes when the disassemblers use private_data.
2015-12-27 01:44:37 -05:00
Mike Frysinger 5e744ef887 sim: unify sim-hload
Pretty much all targets are using this module already, so add it to the
common list of objects.  The only oddball out here is cris and that's
because it supports loading via an offset for all the phdrs.  We drop
support for that.
2015-12-27 00:54:41 -05:00
Mike Frysinger 1b393626ce sim: punt WITH_DEVICES & tconfig.h support
No arch is using this anymore, and we want all new ports using the
hardware framework instead.  Punt WITH_DEVICES and the two callbacks
device_io_{read,write}_buffer.

We can also punt the tconfig.h file as no port is using it anymore.
This fixes in-tree builds that get confused by picking up the wrong
one (common/ vs <port>/) caused by commit ae7d0cac8c.

Any port that needs to set up a global define can use their own
sim-main.h file that they must provide regardless.
2015-12-26 20:38:31 -05:00
Mike Frysinger 0e9672991e sim: standardize sim_create_inferior handling of argv a bit more
For targets that process argv in sim_create_inferior, improve the code:
- provide more details in the comment
- make the check for when to re-init more robust
- clean out legacy sim_copy_argv code

This will be cleaned up more in the future when we have a common inferior
creation function, but at least help new ports get it right until then.
2015-12-26 07:19:07 -05:00
Mike Frysinger f66affe97c sim: aarch64: move ChangeLog content 2015-12-26 07:12:33 -05:00
Nick Clifton caa8d70005 Add support for the MRS instruction to the AArch64 simulator.
* aarch64/simulator.c (system_get): New function.  Provides read
	access to the dczid system register.
	(do_mrs): New function - implements the MRS instruction.
	(dexSystem): Call do_mrs for the MRS instruction.  Halt on
	unimplemented system instructions.
2015-12-15 11:01:03 +00:00
Nick Clifton 2e8cf49e13 Add an AArch64 simulator to GDB.
sim	* configure.tgt: Add aarch64 entry.
	* configure: Regenerate.
	* sim/aarch64/configure.ac: New configure template.
	* sim/aarch64/aclocal.m4: Generate.
	* sim/aarch64/config.in: Generate.
	* sim/aarch64/configure: Generate.
	* sim/aarch64/cpustate.c: New file - functions for accessing
	AArch64 registers.
	* sim/aarch64/cpustate.h: New header.
	* sim/aarch64/decode.h: New header.
	* sim/aarch64/interp.c: New file - interface between GDB and
	simulator.
	* sim/aarch64/Makefile.in: New makefile template.
	* sim/aarch64/memory.c: New file - functions for simulating
	aarch64 memory accesses.
	* sim/aarch64/memory.h: New header.
	* sim/aarch64/sim-main.h: New header.
	* sim/aarch64/simulator.c: New file - aarch64 simulator
	functions.
	* sim/aarch64/simulator.h: New header.

include/gdb * sim-aarch64.h: New file.

sim/test * configure: Regenerate.
	* sim/aarch64: New directory.
2015-11-24 08:47:59 +00:00