Convert microMIPS branches and jumps whose delay slot would be filled by
a generated NOP instruction to the corresponding compact form where one
exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap.
Do so even where the transformation switches from a 16-bit to a 32-bit
branch encoding for no benefit in code size reduction, as this is still
advantageous. This is because a branch/NOP pair takes 2 pipeline slots
or a 2-cycle completion latency except in superscalar implementations.
Whereas a compact branch may or may not stall on its target fetch, so it
will at most have a 2-cycle completion latency and may have only 1 even
in scalar implementations, and in superscalar implementations it is
expected to have no worse latency as a branch/NOP pair has. Also it
won't stall and therefore take the extra latency cycle in the not-taken
case.
Technically this is the same as MIPS16 compaction: for the qualifying
instruction encodings the APPEND_ADD_COMPACT machine code generation
method is selected where APPEND_ADD_WITH_NOP otherwise would and tells
the code generator in `append_insn' to convert the regular form of an
instruction to its corresponding compact form. For this the opcode is
tweaked as necessary and the microMIPS opcode table is scanned for the
matching updated instruction. A non-$0 `rt' operand to BEQ and BNE
instructions is moved to the `rs' operand field of BEQZC and BNEZC
encodings as required.
Unlike with MIPS16 compaction however we need to handle out-of-distance
branch relaxation as well. We do this by deferring the generation of
any delay-slot NOP required to relaxation made in `md_convert_frag', by
converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD
where a relaxed instruction is recorded. Relaxation then, depending on
actual code produced, chooses between either using a compact branch or
jump encoding and emitting the NOP outstanding if no compact encoding is
possible.
For code simplicity's sake the relaxation pass is retained even if the
principle of preferring a compact encoding to a 16-bit branch/NOP pair
means, in the absence of out-of-range branch relaxation, that a single
compact branch machine code instruction will eventually be produced from
a given assembly source instruction.
gas/
* config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag.
(RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16)
(RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16)
(RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32)
(RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits.
(get_append_method): Also return APPEND_ADD_COMPACT for
microMIPS instructions.
(find_altered_mips16_opcode): Exclude macros from matching.
Factor code out...
(find_altered_opcode): ... to this new function.
(find_altered_micromips_opcode): New function.
(frag_branch_delay_slot_size): Likewise.
(append_insn): Handle microMIPS branch/jump compaction.
(macro_start): Likewise.
(relaxed_micromips_32bit_branch_length): Likewise.
(md_convert_frag): Likewise.
* testsuite/gas/mips/micromips.s: Add conditional explicit NOPs
for delay slot filling.
* testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for
delay slot filling.
* testsuite/gas/mips/micromips-size-1.s: Likewise.
* testsuite/gas/mips/micromips.l: Adjust line numbers.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips-size-1.l: Likewise.
* testsuite/gas/mips/micromips.d: Adjust padding.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips@beq.d: Update patterns for
branch/jump compaction.
* testsuite/gas/mips/micromips@bge.d: Likewise.
* testsuite/gas/mips/micromips@bgeu.d: Likewise.
* testsuite/gas/mips/micromips@blt.d: Likewise.
* testsuite/gas/mips/micromips@bltu.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d:
Likewise.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d:
Likewise.
* testsuite/gas/mips/micromips@loc-swap.d: Likewise.
* testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise.
* testsuite/gas/mips/micromips@relax.d: Likewise.
* testsuite/gas/mips/micromips@relax-at.d: Likewise.
* testsuite/gas/mips/micromips@relax-swap3.d: Likewise.
* testsuite/gas/mips/branch-extern-2.d: Likewise.
* testsuite/gas/mips/branch-extern-4.d: Likewise.
* testsuite/gas/mips/branch-section-2.d: Likewise.
* testsuite/gas/mips/branch-section-4.d: Likewise.
* testsuite/gas/mips/branch-weak-2.d: Likewise.
* testsuite/gas/mips/branch-weak-5.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/micromips-compact.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
* testsuite/ld-mips-elf/micromips-branch-absolute.d: Update
patterns for branch compaction.
* testsuite/ld-mips-elf/micromips-branch-absolute-addend.d:
Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
"beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
"j".
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
Remove R_MIPS_PC26_S2 and R_MIPS_PC21_S2 relocation references that went
into `mips_force_relocation' with commit 9d862524f6 ("MIPS: Verify the
ISA mode and alignment of branch and jump targets") by mistake. Their
BFD_RELOC_MIPS_26_PCREL_S2 and BFD_RELOC_MIPS_21_PCREL_S2 equivalents
are already handled there.
gas/
* config/tc-mips.c (mips_force_relocation): Remove
R_MIPS_PC26_S2 and R_MIPS_PC21_S2.
Convert cross-mode regular MIPS and microMIPS BAL instructions to JALX,
similarly to how JAL instructions are converted.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Convert cross-mode
BAL to JALX.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add a
corresponding error message.
gas/
* config/tc-mips.c (mips_force_relocation, mips_fix_adjustable):
Adjust comments for BAL to JALX linker conversion.
(fix_bad_cross_mode_branch_p): Accept cross-mode BAL.
* testsuite/gas/mips/unaligned-branch-1.l: Update error messages
expected.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: Likewise.
* testsuite/gas/mips/branch-local-4.d: New test.
* testsuite/gas/mips/branch-local-n32-4.d: New test.
* testsuite/gas/mips/branch-local-n64-4.d: New test.
* testsuite/gas/mips/branch-addend.d: New test.
* testsuite/gas/mips/branch-addend-n32.d: New test.
* testsuite/gas/mips/branch-addend-n64.d: New test.
* testsuite/gas/mips/branch-local-4.s: New test source.
* testsuite/gas/mips/branch-addend.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-branch-2.d: Update error
messages expected.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: Likewise.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: Likewise.
* testsuite/ld-mips-elf/bal-jalx-addend.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d: New test.
* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-3.s: New test source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-2.s: New test
source.
* testsuite/ld-mips-elf/unaligned-jalx-addend-3.s: New test
source.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Verify that the ISA mode of branch targets is the same as the referring
relocation, so that an attempt to produce a branch between instructions
encoded in different ISA modes each causes an error rather than silently
producing non-functional code. Make sure that no symbol or addend bits
are silently truncated: terminate with an error if the relocation value
calculated cannot be encoded in the relocatable field of a branch; for
REL targets also applying to any intermediate addend.
Also make jump target's alignment verification consistent with that for
branches.
This change will require an update to some obscure handcoded assembly
sources which make branches to labels placed at data objects, however
for microMIPS code only. These labels will have to be updated with the
`.insn' directive for containing code to assemble and link successfully.
Such code is broken as any such labels have always been required by the
microMIPS architecture specification[1][2] to be annotated this way for
correct interpretation, and with our old code missing `.insn' directives
caused labels to present different semantics depending on whether they
were referred with branch (ISA bit ignored) or other relocations (ISA
bit respected).
Enforcing these checks however will ensure errors in building software,
like mixed regular MIPS and microMIPS code links with branches between,
will be diagnosed at the build time rather than causing odd run-time
errors such as intermittent crashes. It will also let cross-mode BAL
instructions be converted to JALX instructions, with a separate change.
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level
Compatibility", p. 533
[2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level
Compatibility", p. 623
bfd/
* elfxx-mips.c (b_reloc_p): Add R_MICROMIPS_PC16_S1,
R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC7_S1.
(branch_reloc_p): New function.
(mips_elf_calculate_relocation): Handle ISA mode determination
for relocations against section symbols, against absolute
symbols and absolute relocations. Also set `*cross_mode_jump_p'
for branches.
<R_MIPS16_26, R_MIPS_26, R_MICROMIPS_26_S1>: Suppress alignment
checks for weak undefined symbols. Also check target alignment
within the same ISA mode.
<R_MIPS_PC16, R_MIPS_GNU_REL16_S2>: Handle cross-mode branches
in the alignment check.
<R_MICROMIPS_PC7_S1>: Add an alignment check.
<R_MICROMIPS_PC10_S1>: Likewise.
<R_MICROMIPS_PC16_S1>: Likewise.
(mips_elf_perform_relocation): Report a failure for unsupported
same-mode JALX instructions and cross-mode branches.
(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Add
error messages for jumps to misaligned addresses.
gas/
* config/tc-mips.c (mips_force_relocation): Also retain branch
relocations against MIPS16 and microMIPS symbols.
(fix_bad_cross_mode_jump_p): New function.
(fix_bad_same_mode_jalx_p): Likewise.
(fix_bad_misaligned_jump_p): Likewise.
(fix_bad_cross_mode_branch_p): Likewise.
(fix_bad_misaligned_branch_p): Likewise.
(fix_validate_branch): Likewise.
(md_apply_fix) <BFD_RELOC_MIPS_JMP, BFD_RELOC_MIPS16_JMP>
<BFD_RELOC_MICROMIPS_JMP>: Separate from BFD_RELOC_MIPS_SHIFT5,
etc. Verify the ISA mode and alignment of the jump target.
<BFD_RELOC_MIPS_21_PCREL_S2>: Replace the inline alignment check
with a call to `fix_validate_branch'.
<BFD_RELOC_MIPS_26_PCREL_S2>: Likewise.
<BFD_RELOC_16_PCREL_S2>: Likewise.
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Retain the original addend.
Verify the ISA mode and alignment of the branch target.
(md_convert_frag): Verify the ISA mode and alignment of resolved
MIPS16 branch targets.
* testsuite/gas/mips/branch-misc-1.s: Annotate non-instruction
branch targets with `.insn'.
* testsuite/gas/mips/branch-misc-5.s: Likewise.
* testsuite/gas/mips/micromips@branch-misc-5-64.d: Update
accordingly.
* testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromips-branch-relax.s: Annotate
non-instruction branch target with `.insn'.
* testsuite/gas/mips/micromips.s: Replace microMIPS JALX targets
with external symbols.
* testsuite/gas/mips/micromips-insn32.d: Update accordingly.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/mips16.s: Annotate non-instruction branch
targets with `.insn'.
* testsuite/gas/mips/mips16.d: Update accordingly.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-dwarf2.s: Annotate non-instruction
branch target with `.insn'.
* testsuite/gas/mips/relax-swap3.s: Likewise.
* testsuite/gas/mips/branch-local-2.l: New list test.
* testsuite/gas/mips/branch-local-3.l: New list test.
* testsuite/gas/mips/branch-local-n32-2.l: New list test.
* testsuite/gas/mips/branch-local-n32-3.l: New list test.
* testsuite/gas/mips/branch-local-n64-2.l: New list test.
* testsuite/gas/mips/branch-local-n64-3.l: New list test.
* testsuite/gas/mips/unaligned-jump-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-3.d: New test.
* testsuite/gas/mips/unaligned-jump-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-jump-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-jump-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-jump-micromips-3.d: New test.
* testsuite/gas/mips/unaligned-branch-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-3.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-3.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-4.l: New list test.
* testsuite/gas/mips/unaligned-branch-r6-5.d: New test.
* testsuite/gas/mips/unaligned-branch-r6-6.d: New test.
* testsuite/gas/mips/unaligned-branch-mips16-1.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-2.l: New list test.
* testsuite/gas/mips/unaligned-branch-mips16-3.d: New test.
* testsuite/gas/mips/unaligned-branch-micromips-1.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-2.l: New list
test.
* testsuite/gas/mips/unaligned-branch-micromips-3.d: New test.
* testsuite/gas/mips/branch-local-2.s: New test source.
* testsuite/gas/mips/branch-local-3.s: New test source.
* testsuite/gas/mips/branch-local-n32-2.s: New test source.
* testsuite/gas/mips/branch-local-n32-3.s: New test source.
* testsuite/gas/mips/branch-local-n64-2.s: New test source.
* testsuite/gas/mips/branch-local-n64-3.s: New test source.
* testsuite/gas/mips/unaligned-jump-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-1.s: New test source.
* testsuite/gas/mips/unaligned-jump-mips16-2.s: New test source.
* testsuite/gas/mips/unaligned-jump-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-jump-micromips-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-1.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-2.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-3.s: New test source.
* testsuite/gas/mips/unaligned-branch-r6-4.s: New test source.
* testsuite/gas/mips/unaligned-branch-mips16-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-mips16-2.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-1.s: New test
source.
* testsuite/gas/mips/unaligned-branch-micromips-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error message
expected.
* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d:
Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
* testsuite/ld-mips-elf/undefweak-overflow.s: Add jumps,
microMIPS BAL and MIPS16 instructions.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update
accordingly.
* testsuite/ld-mips-elf/unaligned-branch-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-r6-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-mips16.d: New test.
* testsuite/ld-mips-elf/unaligned-jump-micromips.d: New test.
* testsuite/ld-mips-elf/unaligned-jump.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
It can be initialized with values greater than 0x80000000, which don't fit in a
signed int. Further it appears to be used as a set of bit flags where unsigned
int is more typical.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (struct nds32_pseudo_opcode): Make pseudo_val
unsigned int.
(do_pseudo_b): Adjust.
(do_pseudo_bal): Likewise.
(do_pseudo_bge): Likewise.
(do_pseudo_bges): Likewise.
(do_pseudo_bgt): Likewise.
(do_pseudo_bgts): Likewise.
(do_pseudo_ble): Likewise.
(do_pseudo_bles): Likewise.
(do_pseudo_blt): Likewise.
(do_pseudo_blts): Likewise.
(do_pseudo_br): Likewise.
(do_pseudo_bral): Likewise.
(do_pseudo_la): Likewise.
(do_pseudo_li): Likewise.
(do_pseudo_ls_bhw): Likewise.
(do_pseudo_ls_bhwp): Likewise.
(do_pseudo_ls_bhwpc): Likewise.
(do_pseudo_ls_bhwi): Likewise.
(do_pseudo_move): Likewise.
(do_pseudo_neg): Likewise.
(do_pseudo_not): Likewise.
(do_pseudo_pushpopm): Likewise.
(do_pseudo_pushpop): Likewise.
(do_pseudo_v3push): Likewise.
(do_pseudo_v3pop): Likewise.
(do_pseudo_pushpop_stack): Likewise.
(do_pseudo_push_bhwd): Likewise.
(do_pseudo_pop_bhwd): Likewise.
(do_pseudo_pusha): Likewise.
(do_pseudo_pushi): Likewise.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sparc.c (struct pop_entry): Make the type of reloc
bfd_reloc_code_real_type.
gas/ChangeLog:
2016-07-19 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-z8k.c (newfix): Make type of type argument
bfd_reloc_code_real_type.
(apply_fix): Likewise.
Don't convert PC-relative REL relocations against absolute symbols to
section-relative references and retain the original symbol reference
instead. Offsets into the absolute section may overflow the limited
range of their in-place addend field, causing an assembly error, e.g.:
$ cat test.s
.text
.globl foo
.ent foo
foo:
b bar
.end foo
.set bar, 0x12345678
$ as -EB -32 -o test.o test.s
test.s: Assembler messages:
test.s:3: Error: relocation overflow
$
With the original reference retained the source can now be assembled and
linked successfully:
$ as -EB -32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <foo>:
0: 1000ffff b 0 <foo>
0: R_MIPS_PC16 bar
4: 00000000 nop
...
$ ld -melf32btsmip -Ttext 0x12340000 -e foo -o test test.o
$ objdump -dr test
test: file format elf32-tradbigmips
Disassembly of section .text:
12340000 <foo>:
12340000: 1000159d b 12345678 <bar>
12340004: 00000000 nop
...
$
For simplicity always retain the original symbol reference, even if it
would indeed fit.
Making TC_FORCE_RELOCATION_ABS separate from TC_FORCE_RELOCATION causes
R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and R_MICROMIPS_PC16_S1 branch
relocations against absolute symbols to be converted on RELA targets to
section-relative references. This is an intended effect of this change.
Absolute symbols carry no ISA annotation in their `st_other' field and
their value is not going to change with linker relaxation, so it is safe
to discard the original reference and keep the calculated final symbol
value only in the relocation's addend.
Similarly R6 R_MIPS_PCHI16 and R_MIPS_PCLO16 relocations referring
absolute symbols can be safely converted even on REL targets, as there
the in-place addend of these relocations covers the entire 32-bit
address space so it can hold the calculated final symbol value, and
likewise the value referred won't be affected by any linker relaxation.
Add a set of suitable test cases and enable REL linker tests which now
work and were previously used as dump patterns for RELA tests only.
gas/
* config/tc-mips.h (TC_FORCE_RELOCATION_ABS): New macro.
(mips_force_relocation_abs): New prototype.
* config/tc-mips.c (mips_force_relocation_abs): New function.
* testsuite/gas/mips/branch-absolute.d: Adjust dump patterns.
* testsuite/gas/mips/mips16-branch-absolute.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/micromips-branch-absolute-addend-n64.d:
Likewise.
* testsuite/gas/mips/branch-absolute-addend.d: New test.
* testsuite/gas/mips/mips16-branch-absolute-addend.d: New test.
* testsuite/gas/mips/micromips-branch-absolute-addend.d: New
test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf.exp: Run
`branch-absolute-addend', `mips16-branch-absolute',
`mips16-branch-absolute-addend' and
`micromips-branch-absolute-addend'.
Correct a problem with the ISA bit being stripped from the addend of
compressed branch relocations, affecting RELA targets. It has been
there since microMIPS support has been added, with:
commit df58fc944d
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Sun Jul 24 14:20:15 2011 +0000
<https://sourceware.org/ml/binutils/2011-07/msg00198.html>, ("MIPS:
microMIPS ASE support") and R_MICROMIPS_PC7_S1, R_MICROMIPS_PC10_S1 and
R_MICROMIPS_PC16_S1 relocations originally affected, and the
R_MIPS16_PC16_S1 relocation recently added with commit c9775dde32
("MIPS16: Add R_MIPS16_PC16_S1 branch relocation support") actually
triggering a linker error, due to its heightened processing strictness
level:
$ cat test.s
.text
.set mips16
foo:
b bar
.set bar, 0x1235
.align 4, 0
$ as -EB -n32 -o test.o test.s
$ objdump -dr test.o
test.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1230
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o test test.o
test.o: In function `foo':
(.text+0x0): Branch to a non-instruction-aligned address
$
This is because the ISA bit of the branch target does not match the ISA
bit of the referring branch, hardwired to 1 of course.
Retain the ISA bit then, so that the linker knows this is really MIPS16
code referred:
$ objdump -dr fixed.o
fixed.o: file format elf32-ntradbigmips
Disassembly of section .text:
00000000 <foo>:
0: f000 1000 b 4 <foo+0x4>
0: R_MIPS16_PC16_S1 *ABS*+0x1231
...
$ ld -melf32btsmipn32 -Ttext 0 -e 0 -o fixed fixed.o
$
Add a set of MIPS16 tests to cover the relevant cases, excluding linker
tests though which would overflow the in-place addend on REL targets and
use them as dump patterns for RELA targets only.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS16_16_PCREL_S1>
<BFD_RELOC_MICROMIPS_7_PCREL_S1, BFD_RELOC_MICROMIPS_10_PCREL_S1>
<BFD_RELOC_MICROMIPS_16_PCREL_S1>: Keep the ISA bit in the
addend calculated.
* testsuite/gas/mips/mips16-branch-absolute.s: Set the ISA bit
in `bar', export `foo'.
* testsuite/gas/mips/mips16-branch-absolute.d: Adjust
accordingly.
* testsuite/gas/mips/mips16-branch-absolute-n32.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-n64.d: Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n32.d:
Likewise.
* testsuite/gas/mips/mips16-branch-absolute-addend-n64.d:
Likewise.
ld/
* testsuite/ld-mips-elf/mips16-branch-absolute.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n32.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-n64.d: New test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n32.d: New
test.
* testsuite/ld-mips-elf/mips16-branch-absolute-addend-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests, except
from `mips16-branch-absolute' and
`mips16-branch-absolute-addend', referred indirectly only.
gas/ChangeLog:
2016-07-05 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (arc_reloc_op_tag): Allow complex ops for dtpoff.
(tc_gen_reloc): Remove passing DTPOFF base info into reloc addendum as it is
no longer needed.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Complement:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), and remove a call to
`install_insn' from `append_insn', which as from that change has become
redundant. This is because such a call, to place an instruction's bit
pattern in output, is already made from `move_insn', called from
`add_relaxed_insn' or `add_fixed_insn' as appropriate, either of which
now always is and has to be made from `append_insn' before the repeated
call to `install_insn' is made. Previously the place where this second
invocation is made was the only one where the output stream was updated,
although the update was made inline rather than with a function call.
Remove the repeated call then, to reclaim some performance.
gas/
* config/tc-mips.c (append_insn): Remove extraneous
`install_insn' call.
A missing 'r' (or wrong 'e') register prefix needs to be complained
about if the template allows for a 64-bit register, not a 32-bit one.
I assume this was a copy-and-paste type of mistake
(from check_long_reg()).
Feature flag handling was not perfect, +nofp16 disabled fp
instructions too.
New feature flag macros were added to check features with multiple
bits set (matters for FP_F16 and SIMD_F16 opcode feature tests).
The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should
use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE
now checks all feature bits.
The aarch64_features table now contains the dependencies as
a separate field (so when the feature is enabled all dependencies
are enabled and when it is disabled everything that depends on it
is disabled).
Note that armv8-a+foo+nofoo is not equivalent to armv8-a if
+foo turns on dependent features that nofoo does not turn off.
gas/
* config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add
require field.
(aarch64_features): Initialize require fields.
(aarch64_parse_features): Handle dependencies.
(aarch64_feature_enable_set, aarch64_feature_disable_set): New.
(md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES.
* testsuite/gas/aarch64/illegal-nofp16.s: New.
* testsuite/gas/aarch64/illegal-nofp16.l: New.
* testsuite/gas/aarch64/illegal-nofp16.d: New.
include/
* opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New.
(AARCH64_CPU_HAS_ANY_FEATURES): New.
(AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES.
(AARCH64_OPCODE_HAS_FEATURE): Remove.
While address overrides are ignored in 64-bit mode (and hence shouldn't
really result in an error, but upon v1 converting this to a warning I
was told otherwise), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt. (The
added test case at once also checks that bndc{l,n,u} won't accept
16-bit register operands.)
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
Fix an assertion failure like:
test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.
triggered by assembling MIPS16 code like:
hello:
addiu $4, $4, 4
jr $31
with the generation of a listing file enabled, e.g.:
$ as -mips16 -O2 -aln=test.lst
The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag. It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.
This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.
This effectively complements:
commit 464ab0e55a
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date: Mon Aug 6 20:33:00 2012 +0000
<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.
The assertion itself was introduced with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.
gas/
* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
case MIPS16 handling.
* testsuite/gas/mips/branch-swap-3.d: New test.
* testsuite/gas/mips/branch-swap-4.d: New test.
* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
* testsuite/gas/mips/branch-swap-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Simplify non-MIPS16 branch swapping by copying the MIPS16 variant, which
sets the new position for the current instruction first and reduces the
calculation of the new position of the previous instruction. Also refer
to previous instruction's frag and position via `delay' for consistency.
Reintroduce an explanatory comment, updated, previously removed with:
commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date: Wed Mar 9 09:17:02 2005 +0000
<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]").
gas/
* config/tc-mips.c (append_insn): Simplify non-MIPS16 branch
swapping sequence.
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
cfi_add_CFA_def_cfa to generate default CFA with offset
* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
gas/ChangeLog:
2016-06-27 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (md_begin): Use ARRAY_SIZE instead of a sentinal
element in relax_table.
its only called with an argument of 0, so we might as well remove the code
supporting other values.
gas/ChangeLog:
2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_set_default_include): remove argument
and simplify accordingly.
(tic54x_include): Adjust.
(tic54x_mlib): Likewise.
Correct a MIPS16 relocation handling regression in GAS introduced with:
commit 177b4a6ad0
Author: Alexandre Oliva <aoliva@redhat.com>
Date: Mon Mar 18 18:56:18 2002 +0000
discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>,
which removed a preparatory call to `mips16_extended_frag' previously
made from `md_estimate_size_before_relax'. As a result the function is
never called with its `sec' parameter non-NULL and consequently all the
unsupported relocation checks within are dead and never trigger, causing
any unhandled relocations to silently resolve to 0. Unfortunately there
was no sufficient test suite coverage back then to catch this.
Remove all dead code then, and all the associated comments. Update the
remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass
the relocation section as the `sec' parameter and use it to mark frags
which require an external relocation, as extended. Finally handle any
outstanding MIPS16 relocations in `md_convert_frag' and report an error
since we don't support any except with percent operators.
gas/
* config/tc-mips.c (append_insn): Use any `O_symbol' expression
unchanged with relaxed MIPS16 instructions.
(mips16_extended_frag): Adjust accordingly. Return 1 right
away if a relocation will be required for the symbol requested.
Remove dead first relaxation pass code.
(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
(md_convert_frag): Adjust symbol value calculation. Raise an
error if a relocation is required for the symbol requested.
* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
add error output.
* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
* testsuite/gas/mips/mips16-branch-absolute.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Keep original microMIPS symbols in references from branch relocations so
that the ISA bit is retained and can be verified for validity in static
link. No need to update WRT MIPS16 symbols because we keep them all
anyway for other reasons.
gas/
* config/tc-mips.c (b_reloc_p): New function.
(mips_fix_adjustable): Also keep the original microMIPS symbol
referred from branch relocations.
* testsuite/gas/mips/branch-local-1.d: New test.
* testsuite/gas/mips/branch-local-n32-1.d: New test.
* testsuite/gas/mips/branch-local-n64-1.d: New test.
* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
relocations.
* testsuite/gas/mips/branch-local-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new cases.
The code supporting -mspfp, -mdpfp, and -mfpuda options are in
sections of code that are commented as being for backward
compatibility only, and having no effect. However, they do have an
effect, enabling the SPX, DPX, and DPA instruction subclasses
respectively. This commit moves the code supporting these options
away from the comments indicating that they are dummy options, and
also fixes a small issue where -mnps400 had the additional effect
of enabling SPX instructions.
A couple of other minor edits (that make no functional change) are
also included.
gas/ChangeLog:
* config/tc-arc.c (options, md_longopts, md_parse_option):
Move -mspfp, -mdpfp and -mfpuda out of the sections for
dummy options. Correct erroneous enabling of SPFP
instructions when using -mnps400.
include/ChangeLog:
* opcode/arc.h: Make insn_class_t alphabetical again.
opcodes/ChangeLog:
* arc-opc.c: Correct description of availability of NPS400
features.
There's no reason to define these macros twice.
gas/ChangeLog:
2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c: Include elf/xtensa.h.
Complement commit 7361da2c95 ("Add support for MIPS R6.") and fix
internal errors like:
foo.s: Assembler messages:
foo.s: Internal error!
Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028.
Please report this bug.
triggered by resolved R6 PC-relative relocations in sources containing
R6 code fragments wrapped into ISA override blocks embedded within code
otherwise assembled for an older ISA.
gas/
* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
<BFD_RELOC_LO16_PCREL>: New switch cases.
(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
Move switch cases along `BFD_RELOC_MIPS_JMP'.
<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
the resolved case.
* testsuite/gas/mips/pcrel-reloc-4.d: New test.
* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-5.d: New test.
* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.d: New test.
* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Avoid segmentation faults in alignment checks made in `md_apply_fix' for
BFD_RELOC_MIPS_18_PCREL_S3 and BFD_RELOC_MIPS_19_PCREL_S2 relocations
caused by dereferencing `fixP->fx_addsy' which will be null if the
relocation processed has been fully resolved.
gas/
* config/tc-mips.c (md_apply_fix) <BFD_RELOC_MIPS_18_PCREL_S3>
<BFD_RELOC_MIPS_19_PCREL_S2>: Avoid null pointer dereferences
via `fixP->fx_addsy'.
The PC-relative R_MIPS_PC18_S3 relocation and consequently its BFD
internal BFD_RELOC_MIPS_18_PCREL_S3 representation is calculated from
the address of the aligned doubleword containing the location being
relocated: (sign_extend(A) + S - (P & ~0x7)) >> 3 rather than the
address of the location itself. Reflect this in calculations made by
GAS so that the relocated field is set correctly if resolved by GAS,
such as with local symbols in the same section which do not require
relocations to be propagated to the link stage.
gas/
* config/tc-mips.c (md_pcrel_from) <BFD_RELOC_MIPS_18_PCREL_S3>:
Calculate relocation from the containing aligned doubleword.
(tc_gen_reloc) <BFD_RELOC_MIPS_18_PCREL_S3>: Calculate the
addend from the containing aligned doubleword.
Use the module level ISA setting rather than the last ISA selected with
a `.set' directive in the source file in determination as to whether to
keep PC-relative relocations and then with the original symbol referred,
for the purpose of R6 linker relaxation.
This is so that with e.g. code like this:
b foo
.set mips32r2
...
it's the command line options or any `.module' directive that decides
how to encode any relocation for `foo' rather than the presence of `.set
mips32r2'.
gas/
* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
rather than `mips_opts' for the R6 ISA check.
(mips_fix_adjustable): Likewise.
* testsuite/gas/mips/pcrel-reloc-1.d: New test.
* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-2.d: New test.
* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-3.d: New test.
* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Complement commit 44d3da2338 ("MIPS/GAS: Treat local jump relocs the
same no matter if REL or RELA") and update and clarify the comment on
jump reloc conversion.
gas/
* config/tc-mips.c (mips_fix_adjustable): Update comment on jump
reloc conversion.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.
It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.
Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (rdasr): New macro.
(wrasr): Likewise.
(rdpr): Likewise.
(wrpr): Likewise.
(rdhpr): Likewise.
(wrhpr): Likewise.
(sparc_opcodes): Use the macros above to fix and expand the
definition of read/write instructions from/to
asr/privileged/hyperprivileged instructions.
* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
%hva_mask_nz. Prefer softint_set and softint_clear over
set_softint and clear_softint.
(print_insn_sparc): Support %ver in Rd.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
%hmcddfr and %hva_mask_nz.
(sparc_ip): New handling of asr/privileged/hyperprivileged
registers, adapted to the new form of the sparc opcodes table.
* testsuite/gas/sparc/rdasr.s: New file.
* testsuite/gas/sparc/rdasr.d: Likewise.
* testsuite/gas/sparc/wrasr.s: Likewise.
* testsuite/gas/sparc/wrasr.d: Likewise.
* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
wrasr tests.
* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
registers require it.
* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
registers and write instruction modalities.
* testsuite/gas/sparc/wrpr.d: Likewise.
* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
registers.
* testsuite/gas/sparc/rdhpr.d: Likewise.
* testsuite/gas/sparc/wrhpr.s: Likewise.
* testsuite/gas/sparc/wrhpr.d: Likewise.
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.
It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
architecture according to the hardware capabilities they require.
(sparc_priv_regs): New table.
(sparc_hpriv_regs): Likewise.
(sparc_asr_regs): Likewise.
(v9anotv9m): Define.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): adjust the GAS
architectures to use the right opcode architecture.
(sparc_md_end): Handle v9{c,d,e,v,m}.
(sparc_ip): Fix some comments.
* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
instruction, which is v9d.
* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
instruction from the test, as %mwait is not readable.
* testsuite/gas/sparc/mwait.d: Likewise.
* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
mismatch architecture errors.
* testsuite/gas/sparc/mism-2.s: New file.
The current sparc assembler breaks when the name of an ancillary-state
register, privileged register or hyperprivileged register has a
%-pseudo-operation name as a prefix. For example, %hmcdper and %hm(),
or %hintp and %hi().
This patch fixes it by introducing a new table `perc_table' (for
%-table) that contains an entry for every %name supported by the
assembler, other than the general registers. This table is used to
detect name collisions when the assembler tries to detect a %-pseudo-op.
This patch also fixes a related bug, making sure that v9a_asr_table and
hpriv_reg_table are sorted in reverse lexicographic order, as otherwise
the search code may fail.
gas/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (priv_reg_table): Use NULL instead of the
empty string to mark the end of the array.
(hpriv_reg_table): Likewise.
(v9a_asr_table): Likewise.
(cmp_reg_entry): Handle entries with NULL names.
(F_POP_V9): Define.
(F_POP_PCREL): Likewise.
(F_POP_TLS_CALL): Likewise.
(F_POP_POSTFIX): Likewise.
(struct pop_entry): New type.
(pop_table): New variable.
(enum pop_entry_type): New type.
(struct perc_entry): Likewise.
(NUM_PERC_ENTRIES): Define.
(perc_table): New variable.
(cmp_perc_entry): New function.
(md_begin): Sort hpriv_reg_table and v9a_asr_table, and initialize
perc_table.
(sparc_ip): Handle entries with NULL names in priv_reg_table,
hpriv_reg_table and v9a_asr_table. Use perc_table to handle
%-pseudo-ops.
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20
reloc.
gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
instruction size.
* config/tc-mcore.c (md_assemble): Likewise.
* config/tc-mn10200.c (md_assemble): Likewise.
* config/tc-moxie.c (md_assemble): Likewise.
* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
exception targets. Add alpha, hppa, microblaze and rl78 to list
of exceptions.
(forward): Add microblaze to list of exceptions.
(fwdexp): Add alpha to list of exceptions.
(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
(do_930509a): Alpha sort list of exception targets. Add h8300 and
mn10200 to list of exceptions.
(align2): Expect to fail for nds32.
(cond): Add alpha and rl78 to list of exceptions.
* testsuite/gas/all/none.d: Skip for ft32 and hppa.
* testsuite/gas/all/string.d: Skip for tic4x.
* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
target does not support ELF.
* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH
tests for sh-pe and sh-rtemscoff targets.
* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
list of exceptions.
(type): Run the noifunc version for alpha-freebsd and visium.
* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
mn10200 or moxie targets.
* testsuite/gas/ft32/insn.d: Update expected disassembly.
* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
targets.
* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
mcore and rx targets.
* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
rl78 and vax.
(purge): Expect to fail on the ns32k and vax.
* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
* testsuite/gas/nds32/ls.d: Likewise.
* testsuite/gas/nds32/sys-reg.d: Likewise.
* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
* testsuite/gas/pe/section-align-3.d: Likewise.
* testsuite/gas/pe/section-exclude.d: Likewise.
* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
data has been seen.
* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
for variations in whitespace.
* testsuite/gas/tilepro/t_constants.d: Pass once all the required
data has been seen.
* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
Installs a 32-bit value without generating warnings on 64-bit
hosts.
Use the new macro to replace the .word directives.
opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
constants to match expected behaviour.
(nds32_parse_opcode): Likewise. Also for whitespace.
Revert an inadvertent change to make RELA JALR relocations
section-relative on MIPS R6 targets made with commit 7361da2c95 ("Add
support for MIPS R6."). There is no need to make this a special case
and the comment introduced with the said change clearly indicates this
was not intended.
gas/
* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
JALR relocations on R6.
* testsuite/gas/mips/jal-svr4pic-local.d: New test.
* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
test.
* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
etc * texi2pod.pl: Escape curly braces, whilst searching for keyword
strong.
gas * config/tc-arm.c: For non-ELF based targets skip ARM feature sets
that are not supported.
* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
constant.
* config/tc-cr16.c (check_range): Likewise.
* config/tc-nios2.c (nios2_check_overflow): Likewise.
VLE is an encoding, not a particular processor architecture, so it
isn't really proper to select insns based on PPC_OPCODE_VLE. For
example
{"evaddw", VX (4, 512), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
{"vaddubs", VX (4, 512), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
shows two insns that have the same encoding, both available with VLE.
Enabling both with VLE means we can't disassemble the second variant
even if -Maltivec is given rather than -Mspe. Also, we don't check
user assembly against the processor type as well as we could.
Another problem is that when using the VLE encoding, insns from the
main ppc opcode table are not available, except those using opcode 4
and 31. Correcting this revealed two errors in the ld testsuite,
use of "nop" and "rfmci" when -mvle.
This patch fixes those problems in the opcode table, and removes
PPCNONE. I find a plain 0 distracts less from other values.
In addition, I've implemented code to recognize some machine values
from the apuinfo note present in ppc32 objects. It's not a complete
disambiguation since we're lacking info to detect newer chips, but
what we have should help with disassembly.
include/
* elf/ppc.h (APUINFO_SECTION_NAME, APUINFO_LABEL, PPC_APUINFO_ISEL,
PPC_APUINFO_PMR, PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK,
PPC_APUINFO_SPE, PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK,
PPC_APUINFO_VLE: Define.
opcodes/
* ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
cpu for "vle" to e500.
* ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
(NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
(PPCNONE): Delete, substitute throughout.
(powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
except for major opcode 4 and 31.
(vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
bfd/
* cpu-powerpc.c (powerpc_compatible): Allow bfd_mach_ppc_vle entry
to match other 32-bit archs.
* elf32-ppc.c (_bfd_elf_ppc_set_arch): New function.
(ppc_elf_object_p): Call it.
(ppc_elf_special_sections): Use APUINFO_SECTION_NAME. Fix
overlong line.
(APUINFO_SECTION_NAME, APUINFO_LABEL): Don't define here.
* elf64-ppc.c (ppc64_elf_object_p): Call _bfd_elf_ppc_set_arch.
* bfd-in.h (_bfd_elf_ppc_at_tls_transform,
_bfd_elf_ppc_at_tprel_transform): Move to..
* elf-bfd.h: ..here.
(_bfd_elf_ppc_set_arch): Declare.
* bfd-in2.h: Regenerate.
gas/
* config/tc-ppc.c (PPC_APUINFO_ISEL, PPC_APUINFO_PMR,
PPC_APUINFO_RFMCI, PPC_APUINFO_CACHELCK, PPC_APUINFO_SPE,
PPC_APUINFO_EFS, PPC_APUINFO_BRLOCK, PPC_APUINFO_VLE): Don't define.
(ppc_setup_opcodes): Check vle disables powerpc_opcodes overridden
by vle_opcodes, and that vle flag doesn't enable opcodes. Don't
add vle_opcodes twice.
(ppc_cleanup): Use APUINFO_SECTION_NAME and APUINFO_LABEL.
ld/
* testsuite/ld-powerpc/apuinfo1.s: Delete nop.
* testsuite/ld-powerpc/apuinfo-vle2.s: New.
* testsuite/ld-powerpc/powerpc.exp: Use apuinfo-vle2.s.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.
gas/
* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
(arm_ext_ras): Renamed from arm_ext_v8_2.
(insns): Update for arm_ext_v8_2 renaming.
(arm_extensions): Add "ras".
* doc/c-arm.texi (ARM Options): Add an entry for "ras".
* testsuite/gas/arm/armv8-a+ras.d: New.
* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
options.
include/
* opcode/arm.h (ARM_EXT2_RAS): New. Also align preceding
entries.
(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.
opcodes/
* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
ARM_EXT_RAS in relevant entries.
The values are always members of the enum, except the two places -1 is assigned
only to playcate -Wuninitialized because gcc isn't or at least didn't used to
be smart enough to figure out its only used if it was set.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-sh.c (parse_reg): Change type of mode argument to
sh_arg_type.
(get_operand): Adjust.
(insert): Change type of how to bfd_reloc_code_real_type.
(insert4): Likewise.
* config/tc-sh64.c (shmedia_get_operand): Adjust.
(shmedia_parse_reg): Change type of mode to shmedia_arg_type.
it points to the result of strchr on a const char *, so it aliases
something that is const. Further its only passed to a function that expects a
const char *, so there's no reason for it to not be const.
gas/ChangeLog:
2016-06-05 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-nds32.c (nds32_parse_option): Make the type of ptr_arg
const char *.
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
This seems a little easier to understand than using a sentinal, and will
hopefully let the compiler optimize the loop better. It also has the effect
that we stop initializing a field of the sentinal that is an enum with zero.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-avr.c (avr_parse_cons_expression): Replace iteration to
sentinal with iteration to array size.
I think this is the more typical way to do this. Its also slightly shorter and
less repeditive.
gas/ChangeLog:
2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/xtensa-relax.h: Move typedefs of enums to the enums
definition.
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax. Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.
gas/
PR gas/20154
* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
cpuintel64.
(match_template): Check Intel64/AMD64 ISA.
opcodes/
PR gas/20154
* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
(opcode_modifiers): Add AMD64 and Intel64.
(main): Properly verify CpuMax.
* i386-opc.h (CpuAMD64): Removed.
(CpuIntel64): Likewise.
(CpuMax): Set to CpuNo64.
(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
(AMD64): New.
(Intel64): Likewise.
(i386_opcode_modifier): Add amd64 and intel64.
(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
on call and jmp.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
CpuMax should be CpuIntel64, not CpuNo64. i386-gen.c is updated to
verify that CpuMax is correct. X86 assembler is updated to properly
set cpuamd64 and cpuintel64.
gas/
PR gas/20154
* config/tc-i386.c (intel64): New.
(cpu_flags_match): Set cpuamd64 and cpuintel64.
(md_parse_option): Set intel64 instead of cpuamd64 and
cpuintel64.
opcodes/
PR gas/20154
* i386-gen.c (main): Fail if CpuMax is incorrect.
* i386-opc.h (CpuMax): Set to CpuIntel64.
* i386-tbl.h: Regenerated.
It contains values between 128 and 256 which fit in an unsigned char, but not a
signed char, so we should explicitly use unsigned char to not rely on how these
values are converted to signed char.
gas/ChangeLog:
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-metag.c (metag_handle_align): Make the type of noop
unsigned char.
gas/ChangeLog:
2016-05-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
bfd_reloc_code_real_type.
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit
AVX512 instruction. We must match another AVX512 bit.
PR gas/20140
* config/tc-i386.c (cpu_flags_match): Require another match
for AVX512VL.
* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
x86-64-avx512vl-1 and x86-64-avx512vl-2.
* testsuite/gas/i386/avx512vl-1.l: New file.
* testsuite/gas/i386/avx512vl-1.s: Likewise.
* testsuite/gas/i386/avx512vl-2.l: Likewise.
* testsuite/gas/i386/avx512vl-2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
PR target/2006764
* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
instruction if supported by the currently selected fpu variant.
* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
Do not convert jump relocs against local MIPS16 or microMIPS symbols to
refer to a section symbol instead even on RELA targets, as it makes it
impossible for the linker to make a JAL to JALX conversion based on ISA
symbol annotation, breaking regular and compressed MIPS interlinking.
gas/
* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
jump relocations against MIPS16 or microMIPS symbols on RELA
targets.
* testsuite/gas/mips/jalx-local.d: New test.
* testsuite/gas/mips/jalx-local-n32.d: New test.
* testsuite/gas/mips/jalx-local-n64.d: New test.
* testsuite/gas/mips/jalx-local.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-local.d: New test.
* testsuite/ld-mips-elf/jalx-local-n32.d: New test.
* testsuite/ld-mips-elf/jalx-local-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
With code refactoring made in commit b886a2ab0d and the addition of
`calculate_reloc' and a separate test for TLS relocs against constants
made there the preexisting fall-through from the TLS reloc switch case
has effectively become a dead execution path. This is because the call
to `calculate_reloc' present there is only made if `fixP->fx_done' is
true, which can only be the case if `fixP->fx_addsy' is NULL, which in
turn has already triggered the TLS reloc test and made execution break
out of the switch statement.
Remove the fall-through then and reshape code accordingly.
gas/
* config/tc-mips.c (md_apply_fix)
<BFD_RELOC_MIPS16_TLS_TPREL_LO16>: Remove fall-through, adjust
code accordingly.
It always returns an element of the enum operatorT, so it should be clearer to
make that the return type.
gas/ChangeLog:
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-xtensa.c (struct suffix_reloc_map): Change type of field
operator to operatorT.
(map_suffix_reloc_to_operator): Change return type to operatorT.
Nothing ever assigns to ft32_target_format, so its always null, which means the
bfd target arch is the default one. It looks like ft32 only has one target
format, so we can just define TARGET_FORMAT to be that literal string.
gas/ChangeLog:
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-ft32.h (DEFAULT_TARGET_FORMAT): Remove.
(ft32_target_format): Likewise.
(TARGET_FORMAT): Adjust.
They only hold values from the op_err enum, so it should be clearer to give
them the enum type.
gas/ChangeLog:
2016-05-24 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-cr16.c (check_range): Make type of retval op_err.
* config/tc-crx.c: Likewise.
The field in spu_opcode is unsigned, and for some values of opcode we can end
up shifting into the high bit. So avoid possibly creating a negative number
and then assigning it to a unsigned field by shifting an unsigned constant.
gas/ChangeLog:
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-spu.c (APUOP): Use OPCODE as an unsigned constant.
generic gas code has a struct symbol, and tic54x typedefs a struct to symbol.
This seems at least rather confusing, and it seems like target specific headers
shouldn't put such generic names in the global namespace preventing other
generic code from using them.
opcodes/ChangeLog:
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* tic54x-dis.c (sprint_mmr): Adjust.
* tic54x-opc.c: Likewise.
gas/ChangeLog:
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* config/tc-tic54x.c (tic54x_mmregs): Adjust.
(md_begin): Likewise.
(encode_condition): Likewise.
(encode_cc3): Likewise.
(encode_cc2): Likewise.
(encode_operand): Likewise.
(tic54x_undefined_symbol): Likewise.
include/ChangeLog:
2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
* opcode/tic54x.h (struct symbol_): typedef to tic54x_symbol instead of
plain symbol.
We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in
"movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax".
PR gas/19600
* config/tc-i386.c (md_apply_fix): Preserve addend for
BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
* testsuite/gas/i386/addend.d: New file.
* testsuite/gas/i386/addend.s: Likewise.
* testsuite/gas/i386/x86-64-addend.d: Likewise.
* testsuite/gas/i386/x86-64-addend.s: Likewise.
* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
* testsuite/gas/i386/reloc32.d: Updated.
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation
with microMIPS J/JAL/JALS instructions, however unlike the latters its
encoded immediate argument is unusually shifted left by 2 rather than 1
in calculating the value used for the operation requested.
We already handle this exception in `mips_elf_calculate_relocation' in
LD, in a scenario where JALX is produced as a result of relaxing JAL for
the purpose of making a cross-mode jump. We also get it right in the
disassembler in `decode_micromips_operand'.
What we don't correctly do however is processing microMIPS JALX produced
by GAS from an assembly source, where a non-zero constant argument or a
symbol reference with a non-zero in-place addend has been used. In this
case the same calculation is made as for microMIPS J/JAL/JALS, causing
the wrong encoding to be produced by GAS on making an object file, and
then again by LD in the final link. The latter in particular causes the
calculation, where the addend fits in the relocatable field, to produce
different final addresses for the same source code depending on whether
REL or RELA relocations are used.
Correct these issues by special-casing microMIPS JALX in the places that
have been previously missed.
bfd/
* elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for
microMIPS JALX.
gas/
* config/tc-mips.c (append_insn): Correct the encoding of a
constant argument for microMIPS JALX.
(tc_gen_reloc): Correct the encoding of an in-place addend for
microMIPS JALX.
* testsuite/gas/mips/jalx-addend.d: New test.
* testsuite/gas/mips/jalx-addend-n32.d: New test.
* testsuite/gas/mips/jalx-addend-n64.d: New test.
* testsuite/gas/mips/jalx-imm.d: New test.
* testsuite/gas/mips/jalx-imm-n32.d: New test.
* testsuite/gas/mips/jalx-imm-n64.d: New test.
* testsuite/gas/mips/jalx-addend.s: New test source.
* testsuite/gas/mips/jalx-imm.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalx-addend.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n32.d: New test.
* testsuite/ld-mips-elf/jalx-addend-n64.d: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
By making the flgp field of struct arc_flags constant we can remove a
place where we cast away the const-ness of a variable. Also, given that
the value assigned to this field almost always comes from compile-time
constant data, having the field non-constant is probably a bad thing.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Remove casting away of
const.
* config/tc-arc.h (struct arc_flags): Make flgp field const.
Some debug code has the wrong printf format specifier for some types
that are (ultimately) bfd_vma. Fixed by using BFD_VMA_FMT string. This
only becomes an issue when building the tc-arc.c file with -DDEBUG=1 to
build in the debug code.
gas/ChangeLog:
* config/tc-arc.c (md_pcrel_from_section): Use BFD_VMA_FMT where
appropriate.
(md_convert_frag): Likewise.
The opcode array iterator mechanism can, in some situations, result in
reading memory outside of the opcode array. When using the
iterator-next mechanism to find the next possible arc_opcode, if we find
an opcode where the name field is NULL, or the name does not match, then
the cached opcode pointer is not set to NULL. The result is that
another call to iterator-next will again increment the opcode
pointer (which might now point outside the opcode array) and attempt to
access the name field of this undefined opcode.
Fixed in this commit by clearing the cached opcode pointer.
I've added a test case, which currently shows the bug, however, this
will only expose this bug while the opcode used (dsp_fp_cmp) is the last
opcode in the table.
gas/ChangeLog:
* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
cached opcode to NULL when we reach a non-matching opcode.
* testsuite/gas/arc/asm-errors-2.d: New file.
* testsuite/gas/arc/asm-errors-2.err: New file.
* testsuite/gas/arc/asm-errors-2.s: New file.
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.
This change checks that we don't access outside the limits of the
operand array.
gas/ChangeLog:
* config/tc-arc.c (tokenize_arguments): Add checks for array
overflow.
* testsuite/gas/arc/asm-errors.s: Addition test line added.
* testsuite/gas/arc/asm-errors.err: Update expected results.
