Daniel Jacobowitz
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9b254dd1ce
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Updated copyright notices for most files.
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2008-01-01 22:53:26 +00:00 |
Joel Brobecker
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4744ac1bb0
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Switch the license of all files explicitly copyright the FSF
to GPLv3.
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2007-08-24 14:30:15 +00:00 |
Daniel Jacobowitz
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6aba47ca06
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Copyright updates for 2007.
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2007-01-09 17:59:20 +00:00 |
Nick Clifton
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16b47b253e
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Add support for the m32r2 processor
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2003-12-11 11:33:44 +00:00 |
Andrew Cagney
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0b2e03b491
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More reversion of incomplete m32r changes. Should be back to normal.
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2003-12-07 16:13:06 +00:00 |
Andrew Cagney
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cd886a95bf
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Revert last commit, build problems.
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2003-12-07 02:58:01 +00:00 |
Andrew Cagney
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3c041444b5
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2003-12-02 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* Makefile.in : Add new machine m32r2.
* m32r2.c : New file for m32r2.
* mloop2.in : Ditto
* model2.c : Ditto
* sem2-switch.c : Ditto
* m32r-sim.h : Add EVB register.
* sim-if.h : Ditto
* sim-main.h : Ditto
* traps.c : Ditto
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2003-12-07 02:27:45 +00:00 |
Jason Molenda
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2acceee218
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import gdb-1999-10-04 snapshot
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1999-10-05 23:13:56 +00:00 |
Stan Shebs
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7a292a7adf
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import gdb-19990422 snapshot
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1999-04-26 18:34:20 +00:00 |
Stan Shebs
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c906108c21
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Initial creation of sourceware repository
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1999-04-16 01:35:26 +00:00 |
Stan Shebs
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071ea11e85
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Initial creation of sourceware repository
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1999-04-16 01:34:07 +00:00 |
Doug Evans
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190659a22d
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* m32r-sim.h (m32r_trap): Update prototype.
* traps.c (m32r_trap): New arg `pc'.
* sem.c,sem-switch.c: Regenerated.
* cpux.h,readx.c,semx.c: Regenerated.
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1998-09-09 22:34:09 +00:00 |
Doug Evans
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7e92721894
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* traps.c: New file. Trap support moved here from sim-if.c.
* Makefile.in (SIM_OBJS): Add traps.o
* sim-if.c: Don't include targ-vals.h.
(sim_engine_illegal_insn): Moved to traps.c
* sim-main.h (SIM_CORE_SIGNAL): Define.
(m32r_core_signal): Declare.
* devices.c (device_io_read_buffer): Handle cache purging via MCCR
register.
* m32r-sim.h (M32R_MISC_PROFILE): Move here from sim-main.h.
(PROFILE_COUNT_SHORTINSNS,PROFILE_COUNT_LONGINSNS): New macros.
(TRAP_SYSCALL,TRAP_BREAKPOINT): New macros.
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1998-06-11 01:05:21 +00:00 |