f807f43d7e
[ARC] Disassemble correctly extension instructions.
...
For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or
2-operand, or a single operand instruction format, depending on the
values present in i-field, and a-field.
The disassembler is reading the section containing the extension
instruction format and stores them in a table. Each table element
represents a linked list with encodings for a particular MAJOR-MINOR
tuple.
The current implementation checks only against the first element of
the list, hence, the issue.
This patch is walking the linked list until empty or finds an opcode
match. It also adds a test outlining the found problem.
opcodes/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Walk the linked list pointed by einsn.
gas/
2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsnxop.d: New file.
* testsuite/gas/arc/textinsnxop.s: Likewise.
2016-09-16 14:49:33 +02:00
dce084426d
Stop the ARC disassembler from seg-faulting if initialised without a BFD present.
...
* arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
2016-09-14 12:20:13 +01:00
7763838e99
Fixed issue with NULL pointer access on header var.
...
Variable "header" in function is set conditionally, but was accessed without
verifying if pointer was NULL.
opcodes/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
* opcodes/arc-dis.c (print_insn_arc): Changed.
2016-08-30 18:21:13 +02:00
db18dbabad
Begin implementing ARC NPS-400 Accelerator instructions
...
opcodes * arc-nps400-tbl.h: Change block comments to GNU format.
* arc-dis.c: Add new globals addrtypenames,
addrtypenames_max, and addtypeunknown.
(get_addrtype): New function.
(print_insn_arc): Print colons and address types when
required.
* arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
define insert and extract functions for all address types.
(arc_operands): Add operands for colon and all address
types.
* arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
* arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
* arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
* arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE,
ARC_OPERAND_COLON. Add the arc_nps_address_type enum and
ARC_NUM_ADDRTYPES.
* opcode/arc.h: Add BMU to insn_class_t enum.
* opcode/arc.h: Add PMU to insn_class_t enum.
gas * config/tc-arc.c: Add new global arc_addrtype_hash.
Define O_colon and O_addrtype.
(debug_exp): Add O_colon and O_addrtype.
(tokenize_arguments): Handle colon and address type
tokens.
(declare_addrtype): New function.
(md_begin): Initialise arc_addrtype_hash.
(arc_parse_name): Add lookup of address types.
(assemble_insn): Handle colons and address types by
ignoring them.
* testsuite/gas/arc/nps400-8.s: New file.
* testsuite/gas/arc/nps400-8.d: New file.
* testsuite/gas/arc/nps400-8.s: Add PMU instruction tests.
* testsuite/gas/arc/nps400-8.d: Add expected PMU
instruction output.
2016-07-27 15:57:18 +01:00
37fd5ef3ec
Add support to the ARC disassembler for selecting instruction classes.
...
gas * testsuite/gas/arc/dsp.d: New file.
* testsuite/gas/arc/dsp.s: Likewise.
* testsuite/gas/arc/fpu.d: Likewise.
* testsuite/gas/arc/fpu.s: Likewise.
* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/tdpfp.d: Likewise.
* testsuite/gas/arc/tfpuda.d: Likewise.
opcodes * arc-dis.c (skipclass): New structure.
(decodelist): New variable.
(is_compatible_p): New function.
(new_element): Likewise.
(skip_class_p): Likewise.
(find_format_from_table): Use skip_class_p function.
(find_format): Decode first the extension instructions.
(print_insn_arc): Select either ARCEM or ARCHS based on elf
e_flags.
(parse_option): New function.
(parse_disassembler_options): Likewise.
(print_arc_disassembler_options): Likewise.
(print_insn_arc): Use parse_disassembler_options function. Proper
select ARCv2 cpu variant.
* disassemble.c (disassembler_usage): Add ARC disassembler
options.
binutils* doc/binutils.texi (objdump): Add ARC disassembler options.
* testsuite/binutils-all/arc/dsp.s: New file.
* testsuite/binutils-all/arc/objdump.exp: Likewise.
include * dis-asm.h: Declare print_arc_disassembler_options.
2016-07-20 17:08:07 +01:00
bdd582dbf1
Arc assembler: Convert nps400 from a machine type to an extension.
...
gas * config/tc-arc.c (check_cpu_feature, md_parse_option):
Add nps400 option and feature. Add check for nps400
feature. Refactor existing checks to check subclass before
feature enablement.
(md_show_usage): Document flags for NPS-400 and add some other
undocumented flags.
(cpu_type): Remove nps400 CPU type entry
(check_zol): Remove bfd_mach_arc_nps400 case.
(md_show_usage): Add help on -mcpu=nps400.
(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
set.
* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
-fpuda flags. Document -mcpu=nps400.
* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
expected flags to match ARC700 instead of NPS400.
* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
* testsuite/gas/arc/nps-400-2.d: Likewise.
* testsuite/gas/arc/nps-400-3.d: Likewise.
* testsuite/gas/arc/nps-400-4.d: Likewise.
* testsuite/gas/arc/nps-400-5.d: Likewise.
* testsuite/gas/arc/nps-400-6.d: Likewise.
* testsuite/gas/arc/nps-400-7.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
avoid clash with cbba instruction.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
case.
ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
* testsuite/ld-arc/nps-1b.d: Likewise.
include * opcode/arc.h: Add nps400 extension and instruction
subclass.
Remove ARC_OPCODE_NPS400
* elf/arc.h: Remove E_ARC_MACH_NPS400
opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length.
Use same method for determining instruction length on ARC700 and
NPS-400.
(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
with the NPS400 subclass.
* arc-opc.c: Likewise.
bfd * archures.c: Remove bfd_mach_arc_nps400.
* bfd-in2.h: Likewise.
* cpu-arc.c (arch_info_struct): Likewise.
* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
Likewise.
2016-06-21 14:03:08 +01:00
4eb6f89250
Add support for 48 and 64 bit ARC instructions.
...
gas * config/tc-arc.c (parse_opcode_flags): New function.
(find_opcode_match): Move flag parsing code out to new function.
Ignore operands marked IGNORE.
(build_fake_opcode_hash_entry): New function.
(find_special_case_long_opcode): New function.
(find_special_case): Lookup long opcodes.
* testsuite/gas/arc/nps400-7.d: New file.
* testsuite/gas/arc/nps400-7.s: New file.
include * opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
(struct arc_long_opcode): New structure.
(arc_long_opcodes): Declare.
(arc_num_long_opcodes): Declare.
opcodes * arc-dis.c (struct arc_operand_iterator): New structure.
(find_format_from_table): All the old content from find_format,
with some minor adjustments, and parameter renaming.
(find_format_long_instructions): New function.
(find_format): Rewritten.
(arc_insn_length): Add LSB parameter.
(extract_operand_value): New function.
(operand_iterator_next): New function.
(print_insn_arc): Use new functions to find opcode, and iterator
over operands.
* arc-opc.c (insert_nps_3bit_dst_short): New function.
(extract_nps_3bit_dst_short): New function.
(insert_nps_3bit_src2_short): New function.
(extract_nps_3bit_src2_short): New function.
(insert_nps_bitop1_size): New function.
(extract_nps_bitop1_size): New function.
(insert_nps_bitop2_size): New function.
(extract_nps_bitop2_size): New function.
(insert_nps_bitop_mod4_msb): New function.
(extract_nps_bitop_mod4_msb): New function.
(insert_nps_bitop_mod4_lsb): New function.
(extract_nps_bitop_mod4_lsb): New function.
(insert_nps_bitop_dst_pos3_pos4): New function.
(extract_nps_bitop_dst_pos3_pos4): New function.
(insert_nps_bitop_ins_ext): New function.
(extract_nps_bitop_ins_ext): New function.
(arc_operands): Add new operands.
(arc_long_opcodes): New global array.
(arc_num_long_opcodes): New global.
* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-02 14:03:23 +01:00
d9eca1df01
[ARC] Update instruction type and delay slot info.
...
This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
2016-05-23 17:41:54 +02:00
c810e0b87a
[ARC] Rename "class" named attributes.
...
gas/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* config/tc-arc.c (attributes_t): Renamed attribute class to
attr_class.
(find_opcode_match, assemble_insn, tokenize_extinsn): Changed.
opcode/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* arc-dis.c (find_format, find_format, get_auxreg)
(print_insn_arc): Changed.
* arc-ext.h (INSERT_XOP): Likewise.
include/
2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
* opcode/arc.h (struct arc_opcode): Renamed attribute class to
insn_class.
(struct arc_flag_class): Renamed attribute class to flag_class.
2016-05-23 17:25:46 +02:00
cb040366b3
opcodes/arc: Move instruction length logic to new function
...
Move the logic that calculates the instruction length out to a new
function. Restructure the code to make it simpler.
opcodes/ChangeLog:
* arc-dis.c (arc_insn_length): New function.
(print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
(find_format): Change insnLen parameter to unsigned.
2016-04-14 17:15:18 +01:00
f36e33dac1
Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
...
gas/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
(arc_flags): Delete code, add flgp.
include/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (flag_class_t): Update.
(ARC_OPCODE_NONE): Define.
(ARC_OPCODE_ARCALL): Likewise.
(ARC_OPCODE_ARCFPX): Likewise.
(ARC_REGISTER_READONLY): Likewise.
(ARC_REGISTER_WRITEONLY): Likewise.
(ARC_REGISTER_NOSHORT_CUT): Likewise.
(arc_aux_reg): Add cpu.
opcodes/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Check for extension flags.
(print_flags): New function.
(print_insn_arc): Update for .extCondCode, .extCoreRegister and
.extAuxRegister.
* arc-ext.c (arcExtMap_coreRegName): Use
LAST_EXTENSION_CORE_REGISTER.
(arcExtMap_coreReadWrite): Likewise.
(dump_ARC_extmap): Update printing.
* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
(arc_aux_regs): Add cpu field.
* arc-regs.h: Add cpu field, lower case name aux registers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:21:06 +02:00
b99747aeed
Add support for .extInstruction pseudo-op.
...
gas/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textinsn-errors.d: New File.
* testsuite/gas/arc/textinsn-errors.err: Likewise.
* testsuite/gas/arc/textinsn-errors.s: Likewise.
* testsuite/gas/arc/textinsn2op.d: Likewise.
* testsuite/gas/arc/textinsn2op.s: Likewise.
* testsuite/gas/arc/textinsn2op01.d: Likewise.
* testsuite/gas/arc/textinsn2op01.s: Likewise.
* testsuite/gas/arc/textinsn3op.d: Likewise.
* testsuite/gas/arc/textinsn3op.s: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extInstruction
documentation.
* config/tc-arc.c (arcext_section): New variable.
(arc_extinsn): New function.
(md_pseudo_table): Add .extInstruction pseudo op.
(attributes_t): New type.
(suffixclass, syntaxclass, syntaxclassmod): New constant
structures.
(find_opcode_match): Remove arc_num_opcodes.
(md_begin): Likewise.
(tokenize_extinsn): New function.
(arc_set_ext_seg): Likewise.
(create_extinst_section): Likewise.
include/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (arc_num_opcodes): Remove.
(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
(ARC_SUFFIX_FLAG): Define.
(flags_none, flags_f, flags_cc, flags_ccf): Declare.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
opcodes/
2016-04-04 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
Initialize.
(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
(arc_opcode arc_opcodes): Null terminate the array.
(arc_num_opcodes): Remove.
* arc-ext.h (INSERT_XOP): Define.
(extInstruction_t): Likewise.
(arcExtMap_instName): Delete.
(arcExtMap_insn): New function.
(arcExtMap_genOpcode): Likewise.
* arc-ext.c (ExtInstruction): Remove.
(create_map): Zero initialize instruction fields.
(arcExtMap_instName): Remove.
(arcExtMap_insn): New function.
(dump_ARC_extmap): More info while debuging.
(arcExtMap_genOpcode): New function.
* arc-dis.c (find_format): New function.
(print_insn_arc): Use find_format.
(arc_get_disassembler): Enable dump_ARC_extmap only when
debugging.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
2016-04-12 10:06:07 +02:00
f2dd88387a
[ARC] Add support for Quarkse opcodes.
...
gas/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/ext2op.d: New file.
* testsuite/gas/arc/ext2op.s: Likewise.
* testsuite/gas/arc/ext3op.d: Likewise.
* testsuite/gas/arc/ext3op.s: Likewise.
opcodes/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h (invld07): Remove.
* arc-ext-tbl.h: New file.
* arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
* arc-opc.c (arc_opcodes): Add ext-tbl include.
include/
2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add QUARKSE subclass.
(FIELDA, FIELDB, FIELDC, FIELDF, FIELDQ, INSN3OP, INSN2OP)
(INSN2OP, INSN3OP_ABC, INSN3OP_ALC, INSN3OP_ABL, INSN3OP_ALL)
(INSN3OP_0BC, INSN3OP_0LC, INSN3OP_0BL, INSN3OP_0LL, INSN3OP_ABU)
(INSN3OP_ALU, INSN3OP_0BU, INSN3OP_0LU, INSN3OP_BBS, INSN3OP_0LS)
(INSN3OP_CBBC, INSN3OP_CBBL, INSN3OP_C0LC, INSN3OP_C0LL)
(INSN3OP_CBBU, INSN3OP_C0LU, MINSN3OP_ABC, MINSN3OP_ALC)
(MINSN3OP_ABL, MINSN3OP_ALL, MINSN3OP_0BC, MINSN3OP_0LC)
(MINSN3OP_0BL, MINSN3OP_0LL, MINSN3OP_ABU, MINSN3OP_ALU)
(MINSN3OP_0BU, MINSN3OP_0LU, MINSN3OP_BBS, MINSN3OP_0LS)
(MINSN3OP_CBBC, MINSN3OP_CBBL, MINSN3OP_C0LC, MINSN3OP_C0LL)
(MINSN3OP_CBBU, MINSN3OP_C0LU, INSN2OP_BC, INSN2OP_BL, INSN2OP_0C)
(INSN2OP_0L INSN2OP_BU, INSN2OP_0U, MINSN2OP_BC, MINSN2OP_BL)
(MINSN2OP_0C, MINSN2OP_0L, MINSN2OP_BU, MINSN2OP_0U): Define.
2016-03-29 14:49:22 +02:00
8699fc3e88
arc: Add nps400 machine type, and assembler flag.
...
This commit introduces the nps400 machine type as a variant of arc.
There's a new flag in the assembler to select this machine type. All
other changes are just adding handling of the new machine type into the
relevant places.
The nps400 is an arc700 variant with some vendor specific instructions
added into the instruction set. This commit does not add any of the new
instructions, this is just laying the groundwork for future commits.
However, in preparation for these new instructions a new opcode define for
nps400 has been added to include/opcode/arc.h, this new opcode define is
used in the assembler and disassembler along with the existing define
for arc700 such that when assembling and disassembling for nps400 the
user will have access to all arc700 instructions and all the nps400
vendor extension instructions.
bfd/ChangeLog:
* archures.c (bfd_mach_arc_nps400): Define.
* bfd-in2.h: Regenerate.
* cpu-arc.c (arch_info_struct): New entry for nps400, renumber
some existing entries to make space.
* elf32-arc.c (arc_elf_object_p): Add nps400 case.
(arc_elf_final_write_processing): Likewise.
binutils/ChangeLog:
* readelf.c (decode_ARC_machine_flags): Handle nps400.
gas/ChangeLog:
* config/tc-arc.c (cpu_types): Add nps400 entry.
(check_zol): Handle nps400.
include/ChangeLog:
* elf/arc.h (E_ARC_MACH_NPS400): Define.
* opcode/arc.h (ARC_OPCODE_NPS400): Define.
opcodes/ChangeLog:
* arc-dis.c (print_insn_arc): Handle nps400.
2016-03-21 16:44:49 +00:00
6f2750feaf
Copyright update for binutils
2016-01-01 23:00:01 +10:30
24b368f853
Fix failures in the GAS testsuite for the ARC architecture.
...
gas * config/tc-arc.c (arc_option): Sets all internal gas options when
parsing .cpu directive.
(declare_register_set): Declare all 64 registers.
(md_section_align): Refactor.
(md_pcrel_from_section): Remove assert.
(pseudo_operand_match): Fix pseudo operand match.
(find_reloc): Use flags filed, extend matching.
* config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
relocation.
testsuite * gas/arc/bic.d: Update test.
* gas/arc/add_s-err.s: New file.
* gas/arc/cpu-warn1.s: Likewise.
* gas/arc/pcl-relocs.d: Likewise.
* gas/arc/pcl-relocs.s: Likewise.
* gas/arc/pcrel-relocs.d: Likewise.
* gas/arc/pcrel-relocs.s: Likewise.
* gas/arc/pic-relocs.d: Likewise.
* gas/arc/pic-relocs.s: Likewise.
* gas/arc/plt-relocs.d: Likewise.
* gas/arc/plt-relocs.s: Likewise.
* gas/arc/pseudos.d: Likewise.
* gas/arc/pseudos.s: Likewise.
* gas/arc/sda-relocs.d: Likewise.
* gas/arc/sda-relocs.s: Likewise.
* gas/arc/sda-relocs2.d: Likewise.
* gas/arc/sda-relocs2.s: Likewise.
* gas/arc/tls-relocs.d: Likewise.
* gas/arc/tls-relocs.s: Likewise.
opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
opcodes * arc-dis.c (special_flag_p): Match full mnemonic.
* arc-opc.c (print_insn_arc): Check section size to read
appropriate number of bytes. Fix printing.
* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
arguments.
2015-12-04 10:49:57 +00:00
3f94e60d92
Fix compile time warning compiling ARC port.
2015-10-08 12:34:13 +01:00
886a250647
New ARC implementation.
...
bfd * archures.c: Remove support for older ARC. Added support for new
ARC cpus (ARC600, ARC601, ARC700, ARCV2).
* bfd-in2.h: Likewise.
* config.bfd: Likewise.
* cpu-arc.c: Likewise.
* elf32-arc.c: Totally changed file with a refactored
inplementation of the ARC port.
* libbfd.h: Added ARC specific relocation types.
* reloc.c: Likewise.
gas * config/tc-arc.c: Revamped file for ARC support.
* config/tc-arc.h: Likewise.
* doc/as.texinfo: Add new ARC options.
* doc/c-arc.texi: Likewise.
ld * configure.tgt: Added target arc-*-elf* and arc*-*-linux-uclibc*.
* emulparams/arcebelf_prof.sh: New file
* emulparams/arcebelf.sh: Likewise.
* emulparams/arceblinux_prof.sh: Likewise.
* emulparams/arceblinux.sh: Likewise.
* emulparams/arcelf_prof.sh: Likewise.
* emulparams/arcelf.sh: Likewise.
* emulparams/arclinux_prof.sh: Likewise.
* emulparams/arclinux.sh: Likewise.
* emulparams/arcv2elfx.sh: Likewise.
* emulparams/arcv2elf.sh: Likewise.
* emultempl/arclinux.em: Likewise.
* scripttempl/arclinux.sc: Likewise.
* scripttempl/elfarc.sc: Likewise.
* scripttempl/elfarcv2.sc: Likewise
* Makefile.am: Add new ARC emulations.
* Makefile.in: Regenerate.
* NEWS: Mention the new feature.
opcodes * arc-dis.c: Revamped file for ARC support
* arc-dis.h: Likewise.
* arc-ext.c: Likewise.
* arc-ext.h: Likewise.
* arc-opc.c: Likewise.
* arc-fxi.h: New file.
* arc-regs.h: Likewise.
* arc-tbl.h: Likewise.
binutils * readelf.c (get_machine_name): Remove A5 reference. Add ARCompact
and ARCv2.
(get_machine_flags): Handle EM_ARCV2 and EM_ARCOMPACT.
(guess_is_rela): Likewise.
(dump_relocations): Likewise.
(is_32bit_abs_reloc): Likewise.
(is_16bit_abs_reloc): Likewise.
(is_none_reloc): Likewise.
* NEWS: Mention the new feature.
include * dis-asm.h (arc_get_disassembler): Correct declaration.
* arc-reloc.def: Macro file with definition of all relocation
types.
* arc.h: Changed macros for the newly supported ARC cpus. Altered
enum defining the supported relocations.
* common.h: Changed EM_ARC_A5 definition to EM_ARC_COMPACT. Added
macro for EM_ARC_COMPACT2.
* arc-func.h: New file.
* arc.h: Likewise.
2015-10-07 14:20:19 +01:00
43e65147c0
Remove trailing spaces in opcodes
2015-08-12 04:45:07 -07:00
b90efa5b79
ChangeLog rotatation and copyright year update
2015-01-02 00:53:45 +10:30
4b95cf5c0c
Update copyright years
2014-03-05 22:16:15 +10:30
4ad3b7ef02
* aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
...
value with a default.
(do_special_encoding): Likewise.
(aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
variables with default.
* arc-dis.c (write_comments_): Don't use strncat due
size of state->commentBuffer pointer isn't predictable.
2012-10-18 06:53:16 +00:00
5eb3690ee9
* arc-dis.c: Include sysdep.h first, remove some redundant includes.
...
* bfin-dis.c: Likewise.
* i860-dis.c: Likewise.
* ia64-dis.c: Likewise.
* ia64-gen.c: Likewise.
* m68hc11-dis.c: Likewise.
* mmix-dis.c: Likewise.
* msp430-dis.c: Likewise.
* or32-dis.c: Likewise.
* rl78-dis.c: Likewise.
* rx-dis.c: Likewise.
* tic4x-dis.c: Likewise.
* tilegx-opc.c: Likewise.
* tilepro-opc.c: Likewise.
* rx-decode.c: Regenerate.
2012-05-18 01:59:38 +00:00
cdb062354e
* arc-dis.c (BITS): Don't use shifts to mask off bits.
...
(FIELDD): Sign extend with xor,sub.
2012-02-27 06:31:57 +00:00
c7e2358a88
fix set but unused variable warnings
2010-06-27 04:07:55 +00:00
21d799b5c4
Update soruces to make alpha, arc and arm targets compile cleanly
...
with -Wc++-compat:
* config/tc-alpha.c: Add casts.
(extended_bfd_reloc_code_real_type): New type. Used to avoid
enumeration conversion warnings.
(struct alpha_fixup, void assemble_insn, assemble_insn)
(assemble_tokens): Use new type.
* ecoff.c: Add casts. (mark_stabs): Use enumeration names.
* config/obj-elf.c: Add cast
* config/tc-arc.c: Add casts.
* config/obj-aout.h (text_section,data_section,bss_section):
Make extern.
* config/obj-elf.c: Add cast.
* config/tc-arm.c: Add casts.
(X, TxCE, TxCE, TxC3, TxC3w, TxCM_, TxCM, TUE, TUF, CE, CL, cCE)
(cCL, C3E, xCM_, nUF, nCE_tag): Change input format to avoid the
need for keywords as arguments.
* ecoff.c: Add casts.
* ecofflink.c: Add casts.
* elf64-alpha.c: Add casts.
(struct alpha_elf_got_entry, struct alpha_elf_reloc_entry): Move
to top level.
(SKIP_HOWTO): Use enum name.
* elf32-arm.c: Add casts.
(elf32_arm_vxworks_bed): Update code to avoid multiple
declarations.
(struct map_stub): Move to top level.
* arc-dis.c Fix casts.
* arc-ext.c: Add casts.
* arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous
enum.
* emultempl/armelf.em: Add casts.
2009-09-25 19:13:27 +00:00
9b201bb5e5
Change source files over to GPLv3.
2007-07-05 09:49:03 +00:00
0fd3a4776c
Kaveh Ghazi's printf format attribute checking patch.
...
bfd:
* elf32-xtensa.c (vsprint_msg): Add format attribute. Fix
format bugs.
* vms.h (_bfd_vms_debug): Add format attribute.
(_bfd_vms_debug, _bfd_hexdump): Fix typos.
binutils:
* bucomm.h (report): Add format attribute.
* dlltool.c (inform): Likewise.
* dllwrap.c (display, inform, warn): Likewise.
* objdump.c (objdump_sprintf): Likewise.
* readelf.c (error, warn): Likewise. Fix format bugs.
gas:
* config/tc-tic30.c (debug): Add format attribute. Fix format
bugs.
include:
* dis-asm.h (fprintf_ftype): Add format attribute.
opcodes:
* arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
v850-dis.c: Fix format bugs.
* ia64-gen.c (fail, warn): Add format attribute.
* or32-opc.c (debug): Likewise.
2005-07-07 19:27:52 +00:00
47b0e7ad8c
Update function declarations to ISO C90 formatting
2005-07-01 11:16:33 +00:00
f432110413
Update the address and phone number of the FSF
2005-05-07 07:34:31 +00:00
82b829a7d3
2005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
...
* opcodes/arc-dis.c:Add enum a4_decoding_class.
(dsmOneArcInst): Use the enum values for the decoding class
Remove redundant case in the switch for decodingClass value 11
2005-03-03 15:42:05 +00:00
19f33eeef5
* Makefile.am (sh-dis.lo): Don't put make commands in deps.
...
* Makefile.in: Regenerate.
* arc-dis.c: Use #include "" instead of <> for local header files.
* m68k-dis.c: Likewise.
2002-05-25 12:55:19 +00:00
86caa542b1
* arc-dis.c: Formatting fixes.
...
(my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE.
2001-09-26 01:54:07 +00:00
2ca0d95257
* arc-dis.c: Don't include <ctype.h>.
...
* openrisc-desc.c: Likewise.
* openrisc-ibld.c: Likewise.
2001-09-21 12:36:56 +00:00
279a96ca39
* mips-dis.c: Add missing prototypes.
...
* a29k-dis.c: Likewise.
* arc-dis.c: Likewise.
* ia64-opc.c: Likewise.
2001-08-21 08:51:12 +00:00
060d22b0d0
Fix typos in ChangeLogs; fix dates in copyright notices
2001-03-13 22:58:38 +00:00
0d2bcfafbf
Updated ARC assembler from arccores.com
2001-01-11 21:20:20 +00:00
0d8dfecfe9
More portability patches. Include sysdep.h everywhere.
2000-04-14 04:16:58 +00:00
252b5132c7
19990502 sourceware import
1999-05-03 07:29:11 +00:00
Claudiu Zissulescu
Anton Kolesov
Cupertino Miranda
Graham Markall
Andrew Burgess
Alan Modra
Nick Clifton
H.J. Lu
Kai Tietz
Jim Wilson
Ramana Radhakrishnan
Andreas Jaeger
Richard Henderson