Commit Graph

93771 Commits

Author SHA1 Message Date
Simon Marchi e6a58aa8a7 Add xml_escape_text_append and use it
[This patch should go on top of "linux_qxfer_libraries_svr4: Use
 std::string", I should have sent them together as a series.]

I noticed that linux_qxfer_libraries_svr4 used xml_escape_text, which
returns an std::string.  That string is then copied into a larger
buffer.  It would be more efficient if we had a version of
xml_escape_text which appended to an existing string instead of
returning a new one.  This is what this patch does.

I manually verified that the output of linux_qxfer_libraries_svr4 didn't
change before/after the patch.

gdb/ChangeLog:

	* common/xml-utils.c (xml_escape_text): Move code to...
	(xml_escape_text_append): ... this new function.
	* common/xml-utils.h (xml_escape_text_append): New declaration.
	* unittests/xml-utils-selftests.c (test_xml_escape_text_append):
	New function.
	(_initialize_xml_utils): register test_xml_escape_text_append as
	a selftest.

gdb/gdbserver/ChangeLog:

	* linux-low.c (linux_qxfer_libraries_svr4): Use
	xml_escape_text_append.
2018-03-08 18:04:46 -05:00
Simon Marchi f6e8a41e67 linux_qxfer_libraries_svr4: Use std::string
Use std::string, removing some manual memory management.

gdb/gdbserver/ChangeLog:

	* linux-low.c (linux_qxfer_libraries_svr4): Use std::string.
2018-03-08 18:04:07 -05:00
Simon Marchi 4872dc464d remote-stdio-gdbserver: Pass "target" to remote_exec to delete file
As described here

  https://sourceware.org/bugzilla/show_bug.cgi?id=22841

there seems to be situations where the remote-stdio-gdbserver board
fails to delete the uploaded binary file.  Passing "target" fixes the
issue for Christian who reported the bug.

I did not experience this problem, but passing "target" to remote_exec
still works for me, so I'm fine with changing it.

Any objection?

gdb/testsuite/ChangeLog:

	PR gdb/22841
	* boards/remote-stdio-gdbserver.exp (${board}_file): Pass
	"target" to remote_exec.
2018-03-08 17:54:54 -05:00
Simon Marchi e4fe375676 Don't redefine upload/download/file in gdbserver-base
Before patch

  Make native gdbserver boards no longer be "remote" (in DejaGnu terms)
  739b3f1d8f

the local gdbserver boards (except native-extended-gdbserver...) were
considered as remote by DejaGNU.  To avoid DejaGNU trying to use ssh/scp
to download the files to the target (which is actually local), the
gdbserver-base.exp file defined some _download, _upload and _file board
operations to override the default behavior, and instead just use local
operations.

The same patch also changed remote-stdio-gdbserver.exp to make it
inherit from gdbserver-base.exp.  Since then, this board (which is
actually remote) uses the overrides with local file operations.  As a
result, files are never actually copied to the target.

I think we can simply remove the overrides from gdbserver-base.exp.
Because all boards should be properly considered local or remote by
DejaGNU, it should by default use the right method for transferring
files.

gdb/testsuite/ChangeLog:

	PR gdb/22841
	* boards/gdbserver-base.exp (${board}_file, ${board}_download,
	${board}_upload): Remove.
2018-03-08 17:53:57 -05:00
H.J. Lu d3d50934a9 x86-64: Also optimize "clr reg64"
"clr reg" is an alias of "xor reg, reg".  We can encode "clr reg64" as
"xor reg32, reg32".

gas/

	* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
	as "xor reg32, reg32".
	* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
	* testsuite/gas/i386/x86-64-optimize-1.d: Updated.

opcodes/

	* i386-opc.tbl: Add Optimize to clr.
	* i386-tbl.h: Regenerated.
2018-03-08 06:41:34 -08:00
H.J. Lu 347a87745e x86: Treat relocation against IFUNC symbol as FUNC
When resolving a relocation against IFUNC symbol in a SHT_NOTE section
without SHF_ALLOC, we treat it as relocation against FUNC symbol since
it needs the address of IFUNC symbol, not the address returned by IFUNC
function.

bfd/

	PR ld/22929
	* elf32-i386.c (elf_i386_relocate_section): Treat relocation
	against IFUNC symbol in SHT_NOTE section without SHF_ALLOC as
	relocation against FUNC symbol.
	* elf64-x86-64.c (elf_x86_64_relocate_section): Likewise.

ld/

	PR ld/22929
	* testsuite/ld-i386/i386.exp: Run PR ld/22929 test.
	* testsuite/ld-x86-64/x86-64.exp: Likewise.
	* testsuite/ld-i386/pr22929.d: New file.
	* testsuite/ld-i386/pr22929.s: Likewise.
	* testsuite/ld-x86-64/pr22929.d: Likewise.
	* testsuite/ld-x86-64/pr22929.s: Likewise.
2018-03-08 06:36:52 -08:00
H.J. Lu bd5dea8822 x86: Remove support for old (<= 2.8.1) versions of gcc
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions.  Assembler translates them to correct ones with a
warning:

[hjl@gnu-cfl-1 gas]$ cat x.s
	fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$

This patch removes support for old (<= 2.8.1) versions of gcc:

[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$

gas/

	* NEWS: Mention -mold-gcc removal.
	* config/tc-i386.c (i386_error): Remove old_gcc_only.
	(old_gcc): Removed.
	(match_template): Remove old gcc support.
	(OPTION_MOLD_GCC): Removed.
	(OPTION_MRELAX_RELOCATIONS): Updated.
	(md_longopts): Remove OPTION_MOLD_GCC.
	(md_parse_option): Likewise.
	(md_show_usage): Remove -mold-gcc.
	* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
	(<= 2.8.1) versions of gcc.
	* testsuite/gas/i386/intel.s: Likewise.
	* testsuite/gas/i386/general.l: Updated.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intel.e: Likewise.
	* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.

include/

	* opcode/i386 (OLDGCC_COMPAT): Removed.

opcodes/

	* i386-gen.c (opcode_modifiers): Remove OldGcc.
	* i386-opc.h (OldGcc): Removed.
	(i386_opcode_modifier): Remove oldgcc.
	* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
	instructions for old (<= 2.8.1) versions of gcc.
	* i386-tbl.h: Regenerated.
2018-03-08 06:31:52 -08:00
Alan Hayward 4ef0bef68c Remove MAX_REGISTER_SIZE define
gdb/
	* defs.h: Remove MAX_REGISTER_SIZE.
	* regcache.c (init_regcache_descr): Remove MAX_REGISTER_SIZE
	asserts.
	* python/py-unwind.c (pyuw_sniffer): Likewise.
2018-03-08 09:42:21 +00:00
Jan Beulich e771e7c9fb x86: fold several AVX512VL templates
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.

A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
2018-03-08 08:58:55 +01:00
Jan Beulich ed438a93f1 x86: fold certain AVX512 rotate and shift templates
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust
VexNDD handling to cope with these, allowing their register and memory
forms to be folded.
2018-03-08 08:58:05 +01:00
Jan Beulich 454172a99e x86: fold VEX-encoded GFNI templates 2018-03-08 08:57:19 +01:00
Jan Beulich 3682415023 x86: fold a few AVX512F templates
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold them
as far as possible. Further folding is possible, but needs other prereq
work done first.
2018-03-08 08:56:47 +01:00
Jan Beulich e7f5c0a99e x86: fold LWP templates
Also drop the no longer necessary explicit Disp<N> from them.
2018-03-08 08:56:08 +01:00
Jan Beulich 25a4277fec x86: fold FMA and FMA4 templates 2018-03-08 08:55:37 +01:00
Jan Beulich d2224064f1 x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIX
They aren't really useful (anymore?): The conflicting operand size check
isn't applicable to any insn validly using respective memory operand
sizes (and if they're used wrongly, another error would result), and the
logic in process_suffix() can be easily changed to work without them.

While re-structuring conditionals in process_suffix() also drop the
CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode
table.
2018-03-08 08:52:27 +01:00
Jan Beulich 23e42951f2 x86: correct operand size match checks for BMI/BMI2 insns
Some BMI/BMI2 insns allow their middle operands to be a memory one. In
such a case, matching register types between operands 0 and 1 as well as
1 and 2 won't help - operands 0 and 2 also need to be checked.
2018-03-08 08:51:18 +01:00
Jan Beulich 8819ada6c4 x86: fold redundant expressions in process_suffix()
There's no point repeatedly evaluating i.types[op].bitfield.reg.
2018-03-08 08:50:13 +01:00
Jan Beulich 548d0ee6e7 x86: simplify result processing of cpu_flags_match()
Make more obvious what the success and failure paths are, and in
particular that what used to be at the "skip" label can't be reached
by what used to be straight line code.
2018-03-08 08:48:10 +01:00
Jan Beulich 929f69fa96 x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()
Just like for the AVX/AES and AVX/PCLMUL combinations, AVX/GFN,
AVX512F/GFNI, AVX512F/VAES, and AVX512F/PCLMUL need special handling to
deal with the pair of required checks specified in the templates.
2018-03-08 08:47:32 +01:00
Jan Beulich ab592e757e x86: change AVX512VL handling in cpu_flags_match()
In order to add an AVX512F counterpart to the present AVX checking, it
is better to move the AVX512VL check out of the conditional it's
currently in.
2018-03-08 08:45:56 +01:00
Jan Beulich db12e14ea0 x86: drop CPU_FLAGS_32BIT_MATCH
It has become a plain alias of CPU_FLAGS_ARCH_MATCH now.
2018-03-08 08:45:25 +01:00
Jan Beulich b9d498173c x86: simplify AVX checks in cpu_flags_match()
No caller cares about the specifics of CPU_FLAGS_{AES,AVX,PCLMUL}_MATCH,
so drop those and fold the nested if()-s.
2018-03-08 08:44:52 +01:00
Jan Beulich bcb1753ee6 x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCH 2018-03-08 08:44:12 +01:00
Jan Beulich 1b193f0b12 x86: drop bogus NoAVX
These are meaningful only for insns with CpuSSE* (and a few other Cpu*)
attribute.
2018-03-08 08:36:41 +01:00
Jan Beulich f2f6a710f4 x86: avoid SSE check for LDMXCSR/STMXCSR
Neither touches any XMM register, so the check is pointless. It is imo
even questionable whether in SSE2AVX mode the two should be converted to
their AVX counterparts.
2018-03-08 08:35:48 +01:00
Jan Beulich 6e3e5c9e41 x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns
When aiming at not mixing SSE and AVX insns, these should be warned
about the same way other non-AVX ones are treated.
2018-03-08 08:35:01 +01:00
Jan Beulich 38e314eb06 x86: drop FloatD
It can be expressed by D, when making the consumer look at operand size
to tell apart both uses.
2018-03-08 08:34:09 +01:00
Jan Beulich d53e6b98a2 x86/Intel: correct disassembly of fsub*/fdiv*
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
2018-03-08 08:33:06 +01:00
Jan Beulich a477a8c4f4 x86: adjust 4-XMM-register-group related warning
Drop "second": For one there's no other source register (the other
source operand is in memory), and in Intel syntax such numbering would
also be wrong.

Take the opportunity and also
- properly place declarations ahead of statements
- use %u format for unsigned int arguments
- fix indentation
2018-03-08 08:27:28 +01:00
Jan Beulich 2907c2f555 x86: bogus VMOVD with 64-bit operands should only allow for registers
These templates exist solely to satisfy gcc's needs, and gcc only
produces these with register operands.
2018-03-08 08:26:35 +01:00
Jan Beulich 73053c1fc4 x86: fold AVX vcvtpd2ps memory forms
This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
2018-03-08 08:25:31 +01:00
Alan Modra 6a7524c6aa Really remove unnecessary power9 group terminating nop
Oops, not tested well enough.  -mpower9 sets all the PPC_OPCODE_POWERn
for n <= 9.

	* config/tc-ppc.c (ppc_handle_align): Correct last patch.  Really
	don't emit a group terminating nop for power9.  Simplify cpu
	tests.
2018-03-08 14:37:26 +10:30
Alan Modra 3fea0c3b3f Remove unnecessary power9 group terminating nop
Power9 doesn't have a group terminating nop, so we may as well emit a
normal nop for power9.  Not that it matters a great deal, I believe
ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware.

	* config/tc-ppc.c (ppc_handle_align): Don't emit a group
	terminating nop for power9.
2018-03-08 14:17:01 +10:30
Paul Pluzhnikov 6d4f21f6ee Fix PR binutils/22923.
A static buffer in get_ver_flags may overflow when e.g. German translation
is longer than English original. Avoid that by expanding the buffer.
2018-03-07 18:18:25 -08:00
GDB Administrator bdd2279f13 Automatic date update in version.in 2018-03-08 00:00:42 +00:00
Tom Tromey e0d3522b88 Return gdb::optional<std::string> from target_fileio_readlink
This changes to_fileio_readlink and target_fileio_readlink to return a
gdb::optional<std::sring>, and then fixes up the callers and
implementations.  This allows the removal of some cleanups.

Regression tested by the buildbot.

gdb/ChangeLog
2018-03-07  Tom Tromey  <tom@tromey.com>

	* linux-tdep.c (linux_info_proc): Update.
	* target.h (struct target_ops) <to_fileio_readlink>: Return
	optional<string>.
	(target_fileio_readlink): Return optional<string>.
	* remote.c (remote_hostio_readlink): Return optional<string>.
	* inf-child.c (inf_child_fileio_readlink): Return
	optional<string>.
	* target.c (target_fileio_readlink): Return optional<string>.
2018-03-07 15:36:28 -07:00
Max Filippov d6ab64818b xtensa: ld: support -z relro
ld/
2018-03-07  Max Filippov  <jcmvbkbc@gmail.com>

	* emulparams/elf32xtensa.sh (COMMONPAGESIZE): Define.
2018-03-07 13:05:12 -08:00
Sriraman Tallam 779bdadbea New option -z,keep-text-section prefix.
This option does not merge certain text sections with prefixes
.text.hot, .text.unlikely, .text.startup and .text.exit.

	* layout.cc (Layout::default_section_order): Check for text section
	prefixes.
	(Layout::text_section_name_mapping): New static member.
	(Layout::text_section_name_mapping_count): New static member.
	(Layout::match_section_name): New static function.
	(Layout::output_section_name): Check for text section prefixes.
	* layout.h (Output_section_order::ORDER_TEXT_HOT): New enum value.
	(Output_section_order::ORDER_TEXT_STARTUP): New enum value.
	(Output_section_order::ORDER_TEXT_EXIT): New enum value.
	(Output_section_order::ORDER_TEXT_UNLIKELY): New enum value.
	(Layout::text_section_name_mapping): New static member.
	(Layout::text_section_name_mapping_count): New static member.
	(Layout::match_section_name): New static function.
	* options.h (keep_text_section_prefix): New -z option.
	* testsuite/Makefile.am (keep_text_section_prefix): New test.
	* testsuite/Makefile.in: Regenerate.
	* testsuite/keep_text_section_prefix.cc: New test source.
	* testsuite/keep_text_section_prefix.sh: New test script.
2018-03-07 12:15:49 -08:00
Andrew Burgess ea005f31ca gdb: Add riscv to list of architectures with a save_reggroup
The regcache cooked_read test needs to know which architectures have a
save_reggroup, riscv does and needs adding to the list.

gdb/ChangeLog:

	* regcache.c (cooked_read_test): Add riscv to the list of
	architectures that have a save_reggroup.
2018-03-07 17:36:37 +00:00
Renlin Li 0c1ded8dc0 [PR20402][LD][AARCH64]Don't emit RELATIVE relocation for absolute symbols which are resolved at static linking time.
For absolute symbols which are forced local or not dynamic, the ABS relocation
should be resolved at static linking time.

Originally, an RELATIVE/ABS relocation will be generated even for absolution
symbols for the dynamic linker to resolve.

bfd/

2018-03-07  Renlin Li  <renlin.li@arm.com>

	PR ld/20402
	* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Check absolute symbol,
	and don't emit relocation in specific case.

ld/

2018-03-07  Renlin Li  <renlin.li@arm.com>

	PR ld/20402
	* testsuite/ld-aarch64/aarch64-elf.exp: Run new test.
	* testsuite/ld-aarch64/pr20402.s: New.
	* testsuite/ld-aarch64/pr20402.d: New.
2018-03-07 14:47:27 +00:00
Andreas Arnez e95a97d41a Fix watching structs in C++
Some of the watchpoint logic depends on the fact that the head of the
value chain represents the user-specified value to watch.  Thus no
additional values should be added to the value chain after that.  However,
if a watchpoint is defined for a C++ structure/class object, then run-time
type information (RTTI) may be present.  Thus, while constructing the
value chain for the watchpoint, the dynamic type is fetched by
gnuv3_rrti_type, which invokes value_addr, which then adds a new value to
the head of the value chain.  This new value represents the pointer to the
structure instead of the structure itself.

With such a "polluted" value chain the watchpoint logic does not recognize
when the user intended to watch a struct, and can_use_hardware_watchpoint
returns zero.  Instead of a hardware watchpoint, a software watchpoint
will then be set for no apparent reason.

This is fixed by adding an early exit to gnuv3_rtti_type when the input
value is not a dynamic class object.

gdb/testsuite/ChangeLog:

	* gdb.cp/watch-cp.cc: New test.
	* gdb.cp/watch-cp.exp: New file.

gdb/ChangeLog:

	* gnu-v3-abi.c (gnuv3_rtti_type): Add early exit if the given
	value is not a dynamic class object.
2018-03-07 14:29:19 +01:00
H.J. Lu 3ae729d5a4 x86: Rewrite NOP generation for fill and alignment
Rewrite NOP generation for fill and code alignment by:

1. Add a 11-byte NOP with another 0x66 prefix.
2. Remove the multi-byte NOP entries which consist of 2 instructions.
3. Select proper NOPs based on ISA and processor tuning.
4. Generate multiple NOPs with the longer NOPs first followed by the
shorter NOP.
5. Use jump for larger NOP padding:
   a. > 8 bytes (2 NOPs) in 16-bit mode.
   b. > 14 bytes (2 NOPs) for older processors.
   c. > 77 bytes (7 NOPs) for newer processors.
6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095.

	PR gas/22874
	* config/tc-i386.c (f32_5): Removed.
	(f32_8): Likewise.
	(f32_9): Likewise.
	(f32_10): Likewise.
	(f32_11): Likewise.
	(f32_12): Likewise.
	(f32_13): Likewise.
	(f32_14): Likewise.
	(f16_5): Likewise.
	(f16_6): Likewise.
	(f16_7): Likewise.
	(f16_8): Likewise.
	(jump_31): Likewise.
	(alt64_11): Likewise.
	(alt64_patt): Likewise.
	(jump_disp8): New.
	(jump32_disp32): Likewise.
	(jump16_disp32): Likewise.
	(alt_11): Likewise.
	(f32_patt): Updated.
	(f16_patt): Likewise.
	(alt_patt): Add alt_11.
	(i386_align_code): Merged with ...
	(i386_generate_nops): This.  Rewritten.
	(fits_in_imm7): Moved before i386_generate_nops.
	(fits_in_imm31): Likewise.
	* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to
	4095.
	(i386_align_code): Removed.
	(HANDLE_ALIGN): Rewritten with i386_generate_nops.
	* doc/as.texinfo: Update limits of control byte for x86 .nops
	directive.
	* testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7.
	* gas/testsuite/gas/i386/noavx-3.l: Updated.
	* gas/testsuite/gas/i386/nop-1.d: Likewise.
	* gas/testsuite/gas/i386/nop-1.s: Likewise.
	* gas/testsuite/gas/i386/nop-2.d: Likewise.
	* gas/testsuite/gas/i386/nop-2.s: Likewise.
	* gas/testsuite/gas/i386/nop-3.d: Likewise.
	* gas/testsuite/gas/i386/nop-4.d: Likewise.
	* gas/testsuite/gas/i386/nop-5.d: Likewise.
	* gas/testsuite/gas/i386/nop-5.s: Likewise.
	* gas/testsuite/gas/i386/nop-6.d: Likewise.
	* gas/testsuite/gas/i386/nop-bad-1.l: Likewise.
	* gas/testsuite/gas/i386/nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/nops-1.d: Likewise.
	* gas/testsuite/gas/i386/nops-2-core2.d: Likewise.
	* gas/testsuite/gas/i386/nops-2-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-2.d: Likewise.
	* gas/testsuite/gas/i386/nops-3-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-3-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-3.d: Likewise.
	* gas/testsuite/gas/i386/nops-4-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-4-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-4.d: Likewise.
	* gas/testsuite/gas/i386/nops-4a-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-5-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-5.d: Likewise.
	* gas/testsuite/gas/i386/nops-6.d: Likewise.
	* gas/testsuite/gas/i386/nops16-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise.
	* gas/testsuite/gas/i386/nops-7.d: New file.
	* gas/testsuite/gas/i386/nops-7.s: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07 04:18:56 -08:00
Alan Modra 52fe4420b7 XCOFF disassembler
xcoff (32-bit) objdump accepted but ignored -M options unless
-mpowerpc was also given.  This patch fixes that, leaving the default
as -Mpwr for xcoff.  I've also enabled more tests for xcoff targets.

binutils/
	* configure.ac: Add objdump_private_desc_xcoff for rs6000.
	* configure: Regenerate.
gas/
	* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
	* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
	* testsuite/gas/ppc/machine.d: Don't run for PE targets.
opcodes/
	* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
	bfd_arch_rs6000.
	* disassemble.h (print_insn_rs6000): Delete.
	* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
	(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
	(print_insn_rs6000): Delete.
2018-03-07 16:56:39 +10:30
Alan Modra 0118219e18 mips64 rtype_to_howto error status
* elf64-mips.c (mips_elf64_rtype_to_howto): Return NULL on error.
	(mips_elf64_slurp_one_reloc_table): Pass on error.
2018-03-07 16:56:31 +10:30
GDB Administrator 1ab3e66438 Automatic date update in version.in 2018-03-07 00:00:35 +00:00
Tom Tromey d8344f3d05 Formatting fixes in rust-exp.y
I noticed a few formatting buglets in rust-exp.y: A couple of lines
were too long, and a couple of parser rules did not follow the same
formatting as the rest of the code.

I'm checking this in as obvious.  Tested by rebuilding.

2018-03-06  Tom Tromey  <tom@tromey.com>

	* rust-exp.y: Formatting fixes.
2018-03-06 13:27:12 -07:00
Jim Wilson 770aa8a3d3 RISC-V: Disallow output format changes.
PR 22920
	* emultempl/riscvelf.em (riscv_create_output_section_statements): New.
	(LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): New.
	* testsuite/ld-elf/pr21884.d (#notarget): Add riscv*-*-*.
	* testsuite/ld-unique/pr21529.d (#notarget): Likewise.
	* testsuite/ld-srec/srec.exp (run_srec_test): For riscv*-*-* target,
	call setup_xfail.
2018-03-06 12:01:50 -08:00
Andrew Burgess 9add17f218 gdb/riscv: Remove partial target description support
Some parts of the target description support were committed with the
initial riscv patch.  As target descriptions are not currently supported
on riscv this commit removes the two pieces for code that relate to
target description support.

It is expected that target description support will be added in the
future, at which point this, or similar code will be added back.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_register_name): Remove target description
	support.
	(riscv_gdbarch_init): Remove target description check.
2018-03-06 19:12:59 +00:00
Andrew Burgess c9486dfe27 gdb/riscv: Remove 'Contributed by....' comments
The GDB coding standard states these lines should never have been
added.

gdb/ChangeLog:

	* riscv-tdep.c: Remove 'Contributed by ...' lines from header
	comment.
	* riscv-tdep.h: Likewise.
2018-03-06 19:12:46 +00:00
Andrew Burgess d74aff3d95 gdb/riscv: Remove use of pseudo registers
The code making use of pseudo registers was initially intended to
support running 32-bit ABI files on 64-bit riscv targets.  However, the
implementation was incomplete, and broken.

For now I've removed all reference to pseudo registers from the riscv
target, we've not lost any functionality, and this cleans up failures in
the selftests.

Once the riscv target has matured a little we'll probably end up
bringing back some of the use of pseudo registers in order to better
support running 32-bit executables on a 64-bit target.

gdb/ChangeLog:

	* riscv-tdep.c (riscv_pseudo_register_read): Delete.
	(riscv_pseudo_register_write): Delete.
	(riscv_gdbarch_init): Remove all use of pseudo registers.
2018-03-06 19:12:19 +00:00