Commit Graph

4968 Commits

Author SHA1 Message Date
H.J. Lu 6ba2af251c Add a testcase for PR ld/18591
PR ld/18591
	* testsuite/ld-x86-64/pr18591.d: New file.
	* testsuite/ld-x86-64/pr18591.s: Likewise.
	* testsuite/ld-x86-64/x86-64.exp: Run pr18591.
2016-02-02 06:36:52 -08:00
H.J. Lu aef2898990 Don't add DT_NEEDED for unmatched symbol
Don't add DT_NEEDED if a symbol from a library loaded via DT_NEEDED
doesn't match the symbol referenced by regular object.

bfd/

	PR ld/19553
	* elflink.c (elf_link_add_object_symbols): Don't add DT_NEEDED
	if a symbol from a library loaded via DT_NEEDED doesn't match
	the symbol referenced by regular object.

ld/testsuite/

	PR ld/19553
	* testsuite/ld-elf/indirect.exp: Run tests for PR ld/19553.
	* testsuite/ld-elf/pr19553.map: New file.
	* testsuite/ld-elf/pr19553.map: Likewise.
	* testsuite/ld-elf/pr19553a.c: Likewise.
	* testsuite/ld-elf/pr19553b.c: Likewise.
	* testsuite/ld-elf/pr19553b.out: Likewise.
	* testsuite/ld-elf/pr19553c.c: Likewise.
	* testsuite/ld-elf/pr19553c.out: Likewise.
	* testsuite/ld-elf/pr19553d.c: Likewise.
	* testsuite/ld-elf/pr19553d.out: Likewise.
2016-02-01 15:49:52 -08:00
H.J. Lu d9e3b59069 Check reloc against IFUNC symbol only with dynamic symbols
There is no need to check relocation IFUNC symbol if there are no
dynamic symbols.

bfd/

	PR ld/19539
	* elf32-i386.c (elf_i386_reloc_type_class): Check relocation
	against STT_GNU_IFUNC symbol only with dynamic symbols.
	* elf64-x86-64.c (elf_x86_64_reloc_type_class): Likewise.

ld/

	PR ld/19539
	* testsuite/ld-elf/pr19539.d: New file.
	* testsuite/ld-elf/pr19539.s: Likewise.
	* testsuite/ld-elf/pr19539.t: Likewise.
2016-01-30 16:08:20 -08:00
H.J. Lu 621ff761b3 Replace == with = in ld/configure.ac
PR ld/19533
	* configure.ac (compressed_debug_sections): Replace == with =.
	* configure: Regenerated.
2016-01-29 07:49:18 -08:00
Denis Chertykov 7585b2b8b6 Prevent .noinit section from incorrect placement for AVR.
When .data and .bss sections are empty .noinit section is placed at data
region's start. This will be incorrect for devices that has different
data start address than data region start in linker script.
The patch updates .noinit section's VMA to end of .bss section. So, .noinit
section will be placed at .data section address (-Tdata=<address>) when .data
and .bss sections are empty.

ld/

	* scripttempl/avr.sc (.noinit): Force .noinit VMA to end of .bss VMA.
	* scripttempl/avrtiny.sc (.noinit): Likewise.
2016-01-25 22:33:25 +03:00
Nick Clifton dfc4394024 Fix linker testsuite failures for ARM netbsdelf target.
PR ld/19453
	* testsuite/ld-arm/arm-elf.exp: Skip tests that do not work for
	the arm-netbsdelf target.
2016-01-21 15:20:57 +00:00
Nick Clifton aebf9be708 Fix unexpected failures in the linker testsuite for ARM VxWorks targets.
PR ld/19455
	* elf32-arm.c (elf32_arm_create_dynamic_sections): Set the ELF
	class of the linker stub bfd.
	(elf32_arm_check_relocs): Skip check for pic format after
	processing a vxWorks R_ARM_ABS12 reloc.
	* elflink.c (bfd_elf_final_link): Check for ELFCLASSNONE when
	reporting a class mismatch.

	* testsuite/ld-arm/vxworks1-lib.dd: Update for current
	disassmebler output.
	* testsuite/ld-arm/vxworks1-lib.rd: Likewise.
	* testsuite/ld-arm/vxworks1.dd: Likewise.
	* testsuite/ld-arm/vxworks1.rd: Likewise.
	* testsuite/ld-arm/vxworks1.ld: Set the output format.
2016-01-21 10:51:25 +00:00
Jiong Wang 2f340668a9 [AArch64] Relax long branch veneer insertion for non STT_FUNC symbol
As defined at AArch64 ELF Specification (4.6.7 Call and Jump
  relocations), symbol with type of non STT_FUNC but in different input
  section with relocation place should insert long branch veneer also.

  Meanwhile the current long branch veneer infrastructure havn't considered
  the situation where the branch destination is "sym_value + rela->addend".

  This was OK because we only insert veneer for long call destination is
  STT_FUNC symbol for which the addend is always zero. But as we relax the
  support to other situations by this patch, we need to handle addend be
  non-zero value. For example, for static function, relocation against
  "local symbol" are turned into relocation against "section symbol + offset"
  where there is a valid addend.

  bfd/
	* elfnn-aarch64.c (aarch64_type_of_stub): Allow insert long branch
	veneer for sym_sec != input_sec.
	(elfNN_aarch64_size_stub): Support STT_SECTION symbol.
	(elfNN_aarch64_final_link_relocate): Take rela addend into account when
	calculation destination.

  ld/
	* testsuite/ld-aarch64/farcall-section.d: Delete.
	* testsuite/ld-aarch64/farcall-section.s: Delete.
	* testsuite/ld-aarch64/farcall-b-section.d: New expectation file.
	* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
	* testsuite/ld-aarch64/farcall-b-section.s: New testcase.
	* testsuite/ld-aarch64/farcall-bl-section.s: Likewise.
	* testsuite/ld-aarch64/aarch64-elf.exp: Likewise.
2016-01-21 09:57:09 +00:00
Nick Clifton fdbd3e95ee Fix linker testsuite failures for arm-pe targets.
PR 19457
	* testsuite/ld-scripts/script.exp (extract_symbol_test): Stop test
	early for PE based targets.
	* testsuite/ld-scripts/align.t: Use 0x1000 as VMA alignment.
	* testsuite/ld-pe/tlssec32.d: Allow for relocatable output.
2016-01-20 15:41:06 +00:00
Mickael Guene 91f68a68f9 Add support for an ARM specific 'y' section attribute flag to mark the section as NOREAD.
bfd/ChangeLog:
      * elf32-arm.c ((elf32_arm_special_sections): Remove catch of noread
      section using '.text.noread' pattern.

gas/ChangeLog:
      * config/obj-elf.c (obj_elf_change_section) : Allow arm section with
      SHF_ARM_NOREAD section flag.
      * config/tc-arm.h (md_elf_section_letter) : Implement this hook to
      handle letter 'y'.
     (arm_elf_section_letter) : Declare it.
      * config/tc-arm.c (arm_elf_section_letter): Handle letter 'y' to set
      SHF_ARM_NOREAD section flag.
      * doc/c-arm.texi (ARM section attribute 'y'): Document it.

gas/testsuite/ChangeLog:
      * gas/arm/section-execute-only.s: New test case.
      * gas/arm/section-execute-only.d: Expected output.

ld/testsuite/ChangeLog:
      * ld-arm/thumb1-noread-not-present-mixing-two-section.s: Add 'y'
      attribute usage.
      * ld-arm/thumb1-noread-present-one-section.s: Likewise.
      * ld-arm/thumb1-noread-present-two-section.s: Likewise.
      * ld-arm/thumb1-input-section-flag-match.s: Likewise.

binutils/ChangeLog:
      * readelf.c (get_elf_section_flags): Display y letter for section
      with SHF_ARM_NOREAD section flag in readelf section output.
      (process_section_headers): Add y letter in readelf section output
      key mapping for ARM architecture.
2016-01-20 12:53:50 +00:00
Nick Clifton a4af960aef Fix PR18735 test for RL78.
* testsuite/ld-elf/pr18735.d: Allow for extra symbols between
	foo@FOO and bar@@FOO.
2016-01-19 09:57:03 +00:00
Nick Clifton 24f03d4ecf Re-enable rgn-at11 test for MIPS targets with adjusted section alignment.
* testsuite/ld-scripts/rgn-at11.s: New file - based on rgn-at10.s
	but with 16 byte section alignment.
	* testsuite/ld-scripts/rgn-at11.d: Use new source file.  Reenable
	test for MIPS targets.
2016-01-18 13:00:33 +00:00
Alan Modra 3d961d0d3a Provide AC_PROG_LEX that copes with LEX=missing from top-level
config/
	PR binutils/19481
	* override.m4 (AC_PROG_LEX): Define.
binutils/
	* configure: Regenerate.
gas/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
2016-01-18 22:17:57 +10:30
Nick Clifton 760f6ee894 Skip linker plugin tests if the linker has not been configured to support plugins.
* ld-plugin/plugin.exp: Skip plugin tests if the linker is not
	configured to support plugins.
2016-01-18 11:23:44 +00:00
Alan Modra 5c14705fb3 Regen configure
Picks up 2016-01-12 libtool.m4 change.

bfd/
	* configure: Regenerate.
binutils/
	* configure: Regenerate.
gas/
	* configure: Regenerate.
gprof/
	* configure: Regenerate.
ld/
	* configure: Regenerate.
opcodes/
	* configure: Regenerate.
2016-01-17 12:28:14 +10:30
Alan Modra b3066ae825 m68hc11/12 and xgate config.sub weirdness
Oddly, config.sub converts a duple ending in -elf for these target to
-unknown-none, which means they aren't seen as elf targets by
binutils.  So, counter that.  This exposes a number of testsuite
issues (ones you would have seen if configuring with a full triple,
say m68hc11-unknown-elf).

binutils/
	* testsuite/lib/binutils-common.exp (is_elf_format): Return true
	for m68hc11/12 and xgate triples.
gas/
	* testsuite/gas/cfi/cfi.exp: Exclude m68hc11/12 from m68k test.
ld/
	* testsuite/lib/ld-lib.exp (check_shared_lib_support): Exclude xgate.
	* testsuite/ld-elf/endsym.d: xfail m68hc11/12 and xgate.
	* testsuite/ld-elf/pr14156a.d: Likewise.
	* testsuite/ld-elf/pr14926.d: Don't run for m68hc11/12 and xgate.
	* testsuite/ld-elf/sec64k.exp: Likewise.
2016-01-17 12:13:43 +10:30
Thomas Preud'homme 4c4ac9642a Fix Thumb-Thumb farcall v6-M (no profile) test
2016-01-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

ld/
    * testsuite/ld-arm/arm-elf.exp (Thumb-Thumb farcall v6-M (no profile)):
    Set address of .foo section when linking.
    * testsuite/ld-arm/farcall-thumb-thumb-m-no-profile-b.s: Place myfunc
    in .foo section.
    * testsuite/ld-arm/farcall-thumb-thumb-m-no-profile.d: Adapt expected
    output to the above changes.
2016-01-14 18:00:55 +08:00
Nick Clifton 8405419985 Mark the linker's -Bsymbolic-functions test as an expected failure for MIPS targets.
* ld-elf/elf.exp (-Bymsolic-functions): Expect to fail
	for MIPS targets.
2016-01-13 10:00:49 +00:00
Nick Clifton 13ce3603be Mark the linker's extract symbols test as an expected failure for MIPS targets.
* testsuite/ld-scripts/script.exp (extract_symbol_test): Expect to
	fail for MIPS targets.
2016-01-13 09:40:11 +00:00
Nick Clifton 1bce3adf99 Mark the rgn-at11 test as an expected failure for MIPS targets.
* ld-scripts/rgn-at11.d: Expect this test to fail for
	MIPS targets.
2016-01-13 09:26:22 +00:00
Yury Usishchev ac06903dcf Add cantunwind when unwind info does not match start of section.
bfd     * elf32-arm.c (elf32_arm_fix_exidx_coverage): Insert cantunwind when
        address in first unwind entry does not match start of section.

tests   * ld-arm/arm-elf.exp: New test.
        * ld-arm/unwind-mix.d: New file.
        * ld-arm/unwind-mix1.s: New file.
        * ld-arm/unwind-mix2.s: New file.
2016-01-12 16:35:49 +00:00
Jiong Wang 109575d7eb [ARM] PR ld/19368: Add missing relocation type class for R_ARM_IRELATIVE
2016-01-08  Richard Sandiford  <richard.sandiford@arm.com>
	    Jiong Wang  <jiong.wang@arm.com>

	PR ld/19368
	bfd/
	* elf32-arm.c (elf32_arm_reloc_type_class): Map R_ARM_IRELATIVE to
	reloc_class_ifunc.

	ld/
	* testsuite/ld-arm/ifunc-3.rd: Update expected result.
	* testsuite/ld-arm/ifunc-4.rd: Likewise.
	* testsuite/ld-arm/ifunc-9.rd: Likewise.
	* testsuite/ld-arm/ifunc-10.rd: Likewise.
	* testsuite/ld-arm/ifunc-12.rd: Likewise.
	* testsuite/ld-arm/ifunc-13.rd: Likewise.
2016-01-08 09:49:03 +00:00
Nick Clifton 296ebfbb91 Fix the execution of the MSP430 simulator testsuite.
ld	* emulparams/msp430elf.sh (RAM_START): Move to 0x500 - above the
	MSP430 hardware multiply address range.
	* scripttempl/elf32msp430.sc (__romdatastart): Define.
	(__romdatacopysize): Define.
	* scripttempl/elf32msp430_3.sc: Likewise.

tests	* testutils.inc (__pass): Use the LMA addresses of the _passmsg
	symbol.
	(__fail): Likewise.
2016-01-05 16:43:58 +00:00
Maciej W. Rozycki 2f2da8fd3f MIPS/LD: Convert ELF linker emulation option macros to an enum
ld/
	* emultempl/mipself.em (PARSE_AND_LIST_PROLOGUE): Convert
	OPTION_INSN32 and OPTION_NO_INSN32 macros to an enum.
2016-01-04 23:35:03 +00:00
Maciej W. Rozycki d537eeb527 MIPS/BFD: Move attribute check after ELF file header flag check
We have a problem in that in making compatibility checks while merging
private BFD data on the MIPS target we give priority to the attribute
check, which may fail and cause the function to abort early on.  The
problem with this is the ABI compatibility aspect recorded in the
attributes is relatively minor compared to aspects recorded in the ELF
file header.  However the premature exit causes any more important
compatibility aspect violated to be masked and not reported to the user
once a problem with attributes has been noticed.

So move the attribute check after the ELF file header flag check in
`_bfd_mips_elf_merge_private_bfd_data', and do not return prematurely
there.  Take advantage of the resulting grouping of ELF file header
handling together and remove the premature success return point for the
first input object being handled, letting the code later on figure out
output ABI flags even for this object.

Update LD test cases according to messages from ELF file header checks
now preceding ones from attribute checks.

	bfd/
	* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Move
	attribute check after ELF file header flag check.

	ld/
	* testsuite/ld-mips-elf/attr-gnu-4-14.d: Update the order of
	messages expected according to MIPS BFD private data merge
	changes.
	* testsuite/ld-mips-elf/attr-gnu-4-24.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-34.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-41.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-42.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-43.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-45.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-46.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-47.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-48.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-49.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-54.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-64.d: Likewise.
	* testsuite/ld-mips-elf/attr-gnu-4-74.d: Likewise.
2016-01-04 23:30:00 +00:00
Alan Modra 6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
Alan Modra 3499769a6a New 2016 binutils ChangeLog files
Note that this does not create bfd/doc/ChangeLog, */testsuite/ChangeLog
and include/*/ChangeLog files.
2016-01-01 22:59:42 +10:30
Alan Modra 4120fa118f binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
Alan Modra 331e61312e Fix assorted ChangeLog errors 2015-12-30 11:44:35 +10:30
Thomas Preud'homme 3e1a8f9569 Add test for ARMv6-M farcall with no profile info
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

ld/testsuite/
    * ld-arm/arm-elf.exp: Run new test "Thumb-Thumb farcall v6-M (no
    profile)".
    * ld-arm/farcall-thumb-thumb-m-no-profile-a.s: New file.
    * ld-arm/farcall-thumb-thumb-m-no-profile-b.s: Likewise.
    * ld-arm/farcall-thumb-thumb-m-no-profile.d: Likewise.
2015-12-26 10:24:58 +08:00
Thomas Preud'homme 2fd158eb7b Add support for linking ARMv8-M object files
2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    * elf32-arm.c (using_thumb_only): Check that profile is 'M' and update
    logic around Tag_CPU_arch values to return TRUE for ARMv8-M
    architectures.
    (tag_cpu_arch_combine): Define v8m_baseline and v8m_mainline and update
    v4t_plus_v6_m and comb to deal with ARMv8-M Tag_CPU_arch merging logic.
    (elf32_arm_merge_eabi_attributes): Add Tag_CPU_name values for
    ARMv8-M.

bfd/testsuite/
    * ld-arm/arm-elf.exp (armeabitests_common): Run new tests
    "Thumb-Thumb farcall v8-M", "EABI attribute merging 8",
    "EABI attribute merging 9" and "EABI attribute merging 10".
    (Thumb-Thumb farcall v8-M): Renamed to ...
    (Thumb-Thumb farcall v8-M Mainline): This.
    (Thumb-Thumb farcall v8-M Baseline): New test.
    * ld-arm/attr-merge-8a.s: New file.
    * ld-arm/attr-merge-8b.s: Likewise.
    * ld-arm/attr-merge-8.attr: Likewise.
    * ld-arm/attr-merge-9a.s: Likewise.
    * ld-arm/attr-merge-9b.s: Likewise.
    * ld-arm/attr-merge-9.out: Likewise.
    * ld-arm/attr-merge-10a.s: Likewise.
    * ld-arm/attr-merge-10b.s: Likewise.
    * ld-arm/attr-merge-10.attr: Likewise.
2015-12-24 17:33:17 +08:00
Yury Usishchev 491d01d3da ARM: Fix exidx coverage for relocatable builds.
bfd  * elf-bfd.h: Add callback to count additional relocations.
     * elf32-arm.c (_arm_elf_section_data): Add new counter.
     (insert_cantunwind_after): Increment relocations counter.
     (elf32_arm_fix_exidx_coverage): Remove exidx entries and add
     terminating CANTUNWIND entry only in final builds.
     (elf32_arm_add_relocation): New function.
     (elf32_arm_write_section): Add relocations in relocatable builds.
     (elf32_arm_count_additional_relocs): New function.
     (elf_backend_count_additional_relocs): New define.
     * bfd/elflink.c (bfd_elf_final_link): Use callback and adjust size of
     .rel section.
     * bfd/elfxx-target.h (elf_backend_count_additional_relocs): New define.

ld   * emultempl/armelf.em (gld${EMULATION_NAME}_after_allocation): Call
     elf32_arm_fix_exidx_coverage for relocatable builds.

ld/testsuite
     * ld-arm/arm-elf.exp: New test.
     * ld-arm/unwind-rel.d: New file.
     * ld-arm/unwind-rel1.s: New file.
     * ld-arm/unwind-rel2.s: New file.
     * ld-arm/unwind-rel3.s: New file.
2015-12-22 15:50:13 +00:00
Mickael Guene ac4c9b0459 Add support for ARM's NOREAD section flag.
include/elf
     * arm.h: Add arm SHF_ARM_NOREAD section flag.

bfd  * bfd-in2.h: Regenerate.
     * section.c: Add SEC_ELF_NOREAD.
     * elf32-arm.c (elf32_arm_post_process_headers): Only set
     PF_X attribute if a segment only contains section with
     SHF_ARM_NOREAD flag.
     (elf32_arm_fake_sections): Add SEC_ELF_NOREAD conversion.
     (elf32_arm_section_flags): New function to convert SHF_ARM_NOREAD
     to bfd flag.
     (elf32_arm_lookup_section_flags): New function to allow
     INPUT_SECTION_FLAGS directive with SHF_ARM_NOREAD flag.
     (elf32_arm_special_sections): Add special sections array
     to catch section prefix by '.text.noread' pattern.

ld/testsuite
     * ld-arm/arm-elf.exp: New tests.
     * ld-arm/thumb1-input-section-flag-match.d: New
     * ld-arm/thumb1-input-section-flag-match.s: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.d: New
     * ld-arm/thumb1-noread-not-present-mixing-two-section.s: New
     * ld-arm/thumb1-noread-present-one-section.d: New
     * ld-arm/thumb1-noread-present-one-section.s: New
     * ld-arm/thumb1-noread-present-two-section.d: New
     * ld-arm/thumb1-noread-present-two-section.s: New

binutils
	* readelf.c (get_elf_section_flags): Add support for ARM specific
	section flags.
2015-12-22 14:12:35 +00:00
Christophe Lyon 0bef041426 Add forgotten ChangeLog updates for 72d98d16ed09584660d0cbb759d90f8dfeef2343:
2015-12-16  Mickael Guene <mickael.guene@st.com>

	bfd/
	* bfd-in2.h: Regenerate.
	* reloc.c: Add new relocations.
	* libbfd.h (bfd_reloc_code_real_names): Add new relocations
	display names.
	* elf32-arm.c (elf32_arm_howto_table_1): Add HOWTO for new
	relocations.
	(elf32_arm_reloc_map): Add bfd/arm mapping for new relocations.
	(elf32_arm_final_link_relocate): Implement new relocations
	resolution.

	gas/
	* doc/c-arm.texi: Add documentation about new directives
	* config/tc-arm.c (group_reloc_table): Add mapping between gas
	syntax and new relocations.
	(do_t_add_sub): Keep new relocations for add operand.
	(do_t_mov_cmp): Keep new relocations for mov operand.
	(insns): Use 'shifter operand with possible group relocation'
	operand parse code for movs operand.
	(md_apply_fix): Implement mov and add encoding when new
	relocations on them.
	(tc_gen_reloc): Add new relocations.
	(arm_fix_adjustable): Since offset has a limited range ([0:255])
	we disable adjust_reloc_syms() for new relocations.

	gas/testsuite/
	* gas/arm/adds-thumb1-reloc-local.d: New
	* gas/arm/adds-thumb1-reloc-local.s: New
	* gas/arm/movs-thumb1-reloc-local.d: New
	* gas/arm/movs-thumb1-reloc-local.s: New

	include/
	* elf/arm.h: Add new arm relocations.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests_common): Add new relocations
	tests.
	* ld-arm/thumb1-adds.d: New
	* ld-arm/thumb1-adds.s: New
	* ld-arm/thumb1-movs.d: New
	* ld-arm/thumb1-movs.s: New
2015-12-17 11:14:37 +01:00
Mickael Guene 72d98d16ed [ARM] Add support for thumb1 pcrop relocations.
To support thumb1 execute-only code we need to support four new
relocations (R_ARM_THM_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G1_NC,
R_ARM_THM_ALU_ABS_G2_NC and  R_ARM_THM_ALU_ABS_G3_NC).
These relocations allow the static linker to finalize construction
of symbol address.
Typical sequence of code to get address of the symbol foo is then
the following :
	movs	r3, #:upper8_15:#foo
	lsls	r3, #8
	adds	r3, #:upper0_7:#foo
	lsls	r3, #8
	adds	r3, #:lower8_15:#foo
	lsls	r3, #8
	adds	r3, #:lower0_7:#foo
This will give following sequence of text and relocations after
assembly :
   4:	2300      	movs	r3, #0
			4: R_ARM_THM_ALU_ABS_G3_NC	foo
   6:	021b      	lsls	r3, r3, #8
   8:	3300      	adds	r3, #0
			8: R_ARM_THM_ALU_ABS_G2_NC	foo
   a:	021b      	lsls	r3, r3, #8
   c:	3300      	adds	r3, #0
			c: R_ARM_THM_ALU_ABS_G1_NC	foo
   e:	021b      	lsls	r3, r3, #8
  10:	3300      	adds	r3, #0
			10: R_ARM_THM_ALU_ABS_G0_NC	foo
2015-12-16 10:19:51 +01:00
H.J. Lu c5847ba726 ld -r doesn't need plugin for slim lto object
Plugin isn't required on slim lto object for relocatable link.

bfd/

	PR ld/19317
	* linker.c (_bfd_generic_link_add_one_symbol): Don't complain
	plugin needed to handle slim lto object for relocatable link.

ld/testsuite/

	PR ld/19317
	* ld-plugin/lto.exp (lto_no_fat): New.
	(lto_link_tests): Add a test for PR ld/19317.
	(lto_run_tests): Likewise.
	(run_ld_link_tests): Likewise.
2015-12-10 12:35:50 -08:00
Kwok Cheung Yeung 4a07dc8135 ld: Fix LTO for MinGW targets
When creating a dummy BFD for an IR file, the output BFD is used as
a template for the new BFD, when it needs to be the input BFD passed
into the function when not dealing with a BFD plugin.

On most targets this is not an issue as the input and output formats
are the same anyway, but on MinGW targets, there are two variant
formats used (pe-i386/pe-x86-64 and pei-i386/pei-x86-64) which are
similar but not interchangeable here.

	PR ld/18199
	* plugin.c (plugin_get_ir_dummy_bfd): Use srctemplate as the
	template when calling bfd_create if it does not use the BFD
	plugin target vector.
2015-12-10 16:12:33 +00:00
Jan Beulich 1e550d79b1 ld: relax alignment requirements of compressed .debug_* section checks
This fixes a failure of the gabinormal linking test on some distros
(where e.g. crt1.o has a .debug_aranges section with larger alignment).
2015-12-07 17:52:25 +01:00
H.J. Lu 02e2aef89b Optimize R_386_GOT32/R_386_GOT32X only if addend is 0
Linker can't optimize R_386_GOT32 and R_386_GOT32X relocations if addend
isn't 0.  It isn't valid to convert

movl	foo@GOT+1(%ecx), %eax

to

leal	foo@GOTOFF+1(%ecx), %eax

nor to convert

movq	foo@GOTPCREL+1(%rip), %rax

to

leaq	foo(%rip), %rax

for x86-64.  We should check if addend is 0 before optimizing R_386_GOT32
and R_386_GOT32X relocations.  Testcases are added for i386 and x86-64.

bfd/

	* elf32-i386.c (elf_i386_convert_load): Skip if addend isn't 0.
	(elf_i386_relocate_section): Skip R_386_GOT32X optimization if
	addend isn't 0.

ld/testsuite/

	* ld-i386/i386.exp: Run mov2a, mov2b and mov3.
	* ld-i386/mov2.s: New file.
	* ld-i386/mov2a.d: Likewise.
	* ld-i386/mov2b.d: Likewise.
	* ld-i386/mov3.d: Likewise.
	* ld-i386/mov3.s: Likewise.
	* ld-x86-64/mov2.s: Likewise.
	* ld-x86-64/mov2a.d: Likewise.
	* ld-x86-64/mov2b.d: Likewise.
	* ld-x86-64/mov2c.d: Likewise.
	* ld-x86-64/mov2d.d: Likewise.
	* ld-x86-64/x86-64.exp: Run mov2a, mov2b, mov2c and mov2d.
2015-12-04 09:03:04 -08:00
Alan Modra 26e3a0c9ba Make --enable-initfini-array the default
* configure.ac (--enable-initfini-array): Remove run test.  Default
	to "yes".  Change help string to --disable-initfini-array.
	* configure: Regenerate.
2015-12-02 19:24:34 +10:30
H.J. Lu ead3d5427a Properly check symbol defined by assignment in linker script
Symbol defined by a linker assignment may have type bfd_link_hash_new
or bfd_link_hash_undefined.  And h->def_regular is always set.
elf_i386_convert_load and elf_x86_64_convert_load should check
h->def_regular as well as bfd_link_hash_undefined and bfd_link_hash_new
to see if a symbol is defined by a linker script.

bfd/

	PR ld/19319
	* elf32-i386.c (elf_i386_convert_load): Check h->def_regular
	instead of bfd_link_hash_new.
	* elf64-x86-64.c (elf_x86_64_convert_load): Likewise.  Skip
	relocation overflow for bfd_link_hash_undefined and
	bfd_link_hash_new if h->def_regular is set.

ld/testsuite/

	PR ld/19319
	* ld-i386/i386.exp: Run pr19319 test.
	* ld-x86-64/x86-64.exp: Likewise.
	* ld-i386/pr19319.dd: New file.
	* ld-i386/pr19319a.S: Likewise.
	* ld-i386/pr19319b.S: Likewise.
	* ld-x86-64/pr19319.dd: Likewise.
	* ld-x86-64/pr19319a.S: Likewise.
	* ld-x86-64/pr19319b.S: Likewise.
2015-12-01 14:45:51 -08:00
Maciej W. Rozycki f21cd97985 MIPS/LD: Fix little-endian `mti' and `img' ELF emulations
Make the little-endian emulation the default for the `mips*el-mti-elf*'
and `mips*el-img-elf*' targets, fixing the issue of LD rejecting, in its
default configuration, object files produced by GAS also in its default
configuration.

	ld/
	* configure.tgt <mips*el-mti-elf*, mips*el-img-elf*>: Add
	targets.
2015-11-20 16:16:40 +00:00
Alan Modra b39910205f Account for .tbss alignment when adjusting start of relro
Another option might be to not bump "dot" for .tbss alignment in the
main section sizing loop, but that could leak some of the following
section into the TLS segment.  Leakage shouldn't matter since it will
be to bytes past the end of .tdata, but for now this is a safer
option.

	PR ld/19264
	* ldlang.c (lang_size_sections): Don't ignore .tbss when
	adjusting start of relro region.
2015-11-19 16:22:25 +10:30
Nick Clifton 3940d2c36a Fixes an invalid warning about memory region overflow on the ARM.
PR ld/19106
	* emultempl/armelf.em (_set_symbols): New function.  Enables
	relaxation for non-relocatable links.
	(LDEMUL_SET_SYMBOLS): Define.
2015-11-16 14:21:28 +00:00
Tristan Gingold d8bd95efd8 Bump version to 2.26.51
bfd/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* version.m4: Bump version to 2.26.51
	* configure: Regenerate.

binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

gprof/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.

opcodes/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* configure: Regenerate.
2015-11-14 16:24:39 -08:00
Tristan Gingold 7feec526b7 Add markers for release 2.26
binutils/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

gas/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.

ld/
2015-11-13  Tristan Gingold  <gingold@adacore.com>

	* NEWS: Add marker for 2.26.
2015-11-13 09:31:25 +01:00
Marcus Shawcroft 06d2788cef Revert "[LD][AARCH64]Add TLSIE relaxation support under large memory model."
This reverts commit 3ebe65c0ff.

Reverted due to PR19188
2015-11-12 15:16:40 +00:00
Peter Bergner a680de9a98 Add assembler, disassembler and linker support for power9.
include/opcode/
	* ppc.h (PPC_OPCODE_POWER9): New define.
	(PPC_OPCODE_VSX3): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
	Add PPC_OPCODE_VSX3 to the vsx entry.
	(powerpc_init_dialect): Set default dialect to power9.
        * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
        insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
        extract_l1 insert_xtq6, extract_xtq6): New static functions.
        (insert_esync): Test for illegal L operand value.
	(DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
	XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
	XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
	XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
	PPCVSX3): New defines.
	(powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
	fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
	<mcrxr>: Use XBFRARB_MASK.
	<addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
	bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
	cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
	cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
	lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
	lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
	modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
	rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
	stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
	subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
	vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
	vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
	vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
	vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
	vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
	vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
	vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
	xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
	xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
	xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
	xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
	xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
	xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
	xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
	xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
	xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
	xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
	xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
	xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
	xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
	<doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
	<tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.

include/elf/
	* ppc.h (R_PPC_REL16DX_HA): New reloction.
	* ppc64.h (R_PPC64_REL16DX_HA): Likewise.

bfd/
	* elf32-ppc.c (ppc_elf_howto_raw): Add R_PPC_REL16DX_HA.
	(ppc_elf_reloc_type_lookup): Handle R_PPC_REL16DX_HA.
	(ppc_elf_addr16_ha_reloc): Likewise.
	(ppc_elf_check_relocs): Likewise.
	(ppc_elf_relocate_section): Likewise.
	(is_insn_dq_form): Handle lxv and stxv instructions.
	* elf64-ppc.c (ppc64_elf_howto_raw): Add R_PPC64_REL16DX_HA.
	(ppc64_elf_reloc_type_lookup): Handle R_PPC64_REL16DX_HA.
	(ppc64_elf_ha_reloc): Likewise.
	(ppc64_elf_check_relocs): Likewise.
	(ppc64_elf_relocate_section): Likewise.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Likewise.
	* reloc.c (BFD_RELOC_PPC_REL16DX_HA): New.

elfcpp/
	* powerpc.h (R_POWERPC_REL16DX_HA): Define.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
	(md_apply_fix): Likewise.
	(ppc_handle_align): Handle power9's group ending nop.

gas/testsuite/
	* gas/ppc/altivec3.s: New test.
	* gas/ppc/altivec3.d: Likewise.
	* gas/ppc/vsx3.s: Likewise.
	* gas/ppc/vsx3.d: Likewise.
	* gas/ppc/power9.s: Likewise.
	* gas/ppc/power9.d: Likewise.
	* gas/ppc/ppc.exp: Run them.
	* gas/ppc/power8.s <lxvx, lxvd2x, stxvx, stxvd2x>: Add new tests.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/vsx.s: <lxvx, stxvx>: Rename invalid mnemonics ...
	<lxvd2x, stxvd2x>: ...to this.
	* gas/ppc/vsx.d: Likewise.

gold/
	* gold/powerpc.cc (Powerpc_relocate_functions::addr16_dq): New function.
	(Powerpc_relocate_functions::addr16dx_ha): Likewise.
	(Target_powerpc::Scan::local): Handle R_POWERPC_REL16DX_HA.
	(Target_powerpc::Scan::global): Likewise.
	(Target_powerpc::Relocate::relocate): Likewise.

ld/testsuite/
	* ld-powerpc/addpcis.d: New test.
	* ld-powerpc/addpcis.s: New test.
	* ld-powerpc/powerpc.exp: Run it.
2015-11-11 19:52:52 -06:00
Alan Modra 868ac09218 Regenerate ld/Makefile.in
* Makefile.in: Regenerate.
2015-11-05 13:48:25 +10:30
Alan Modra fe6052e1ee DATA_SEGMENT_ALIGN documentation is not consistent with behaviour
PR ld/19203
	* ld.texinfo (DATA_SEGMENT_ALIGN): Correct second expression.
2015-11-05 00:45:23 +10:30