The linker silently writes out a conditional branch to 0 if the
target symbol in R_AARCH64_CONDBR19 or R_AARCH64_TSTBR14 relocations is
undefined. Emit a PLT instead so that behaviour is the same for these
relocations as the llvm linker.
The special behaviour for undefined weak symbols, where conditional
branches to such symbols result in a branch unto themselves, has been
retained. This is because the weak-undefined.s test explicitly checks
for that, leading me to conclude that it's expected behaviour.
bfd * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Club
BFD_RELOC_AARCH64_BRANCH19 and BFD_RELOC_AARCH64_TSTBR14
cases with BFD_RELOC_AARCH64_JUMP26.
(elfNN_aarch64_check_relocs): Likewise.
ld * testsuite/ld-aarch64/aarch64-elf.exp: New test
emit-relocs-560.
* testsuite/ld-aarch64/emit-relocs-560.d: New file.
* testsuite/ld-aarch64/emit-relocs-560.s: New file.
In git commit 806470a219 I swapped the order of internal vs. external
relocs memory allocation in ecoff_slurp_reloc_table, the idea being
that the external reloc size can be sanity checked against file size.
However, that fails badly with bfd_alloc memory where releasing any
block also releases all more recently allocated blocks.
* ecoff.c (ecoff_slurp_reloc_table): Malloc external_relocs so
they can be freed without also freeing internal_relocs.
For now we only have one char pointer in RISC-V tdata, so it should be fine.
But once we need more elements in tdata, then we may get some uninitialize
or unexpected values. I do meet the same problem when extending the RISC-V
tdata.
bfd/
elfnn-riscv.c (elfNN_riscv_mkobject): New function. We need this
to initialize RISC-V tdata.
Now that ISA3.1 is out we can finish with the powerxx silliness.
bfd/
* elf64-ppc.c: Rename powerxx to power10 throughout.
gas/
* config/tc-ppc.c (md_assemble): Update for PPC_OPCODE_POWER10
renaming.
* testsuite/gas/ppc/prefix-align.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/gas/ppc/prefix-pcrel.d: Likewise.
* testsuite/gas/ppc/prefix-reloc.d: Likewise.
gold/
* powerpc.cc: Rename powerxx to power10 throughout.
include/
* elf/ppc64.h: Update comment.
* opcode/ppc.h (PPC_OPCODE_POWER10): Rename from PPC_OPCODE_POWERXX.
ld/
* testsuite/ld-powerpc/callstub-1.d: Use -mpower10/-Mpower10 in
place of -mfuture/-Mfuture.
* testsuite/ld-powerpc/notoc2.d: Likewise.
* testsuite/ld-powerpc/powerpc.exp: Likewise.
* testsuite/ld-powerpc/tlsgd.d: Likewise.
* testsuite/ld-powerpc/tlsie.d: Likewise.
* testsuite/ld-powerpc/tlsld.d: Likewise.
opcodes/
* ppc-dis.c (ppc_opts): Add "power10" entry.
(print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
* ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
PR 25961
* coffgen.c (coff_get_normalized_symtab): Check that buffer
contains required number of auxents before processing any auxent.
* coffswap.h (coff_swap_aux_in <C_FILE>): Only swap in extended
file name from auxents for PE.
* aout-cris.c (DEFAULT_ARCH): Delete define.
(MY_set_arch_mach): Likewise.
(SET_ARCH_MACH): Use bfd_set_arch_mach with an explicit architecture
of bfd_arch_cris.
(swap_ext_reloc_in): Add casts to r_index extraction. Mask valid bits
of r_type before the shift.
PR ld/25665
* bfd/elfnn-aarch64.c (group_sections): Copy implementation
from elf32-arm.c.
* testsuite/ld-aarch64/aarch64-elf.exp: Add new test.
* testsuite/ld-aarch64/farcall-group.s: New large group test.
* testsuite/ld-aarch64/farcall-group.d: Likewise.
PR 25900
* elfnn-riscv.c (_bfd_riscv_relax_section): Check root.type before
accessing root.u.def of symbols. Also check root.u.def.section
is non-NULL. Reverse tests so as to make the logic positive.
This allows backend merge_private_bfd_data to examine shared library
e_flags and/or .gnu.attributes. ARM and PowerPC have done so when
using ld.gold for a long time.
(The tic6x change below is dead code due to the earlier FIXME,
but this is probably one of the changes needed there.)
PR 25882
bfd/
* elf32-tic6x.c (elf32_tic6x_merge_attributes): Don't transfer
Tag_ABI_PIC or Tag_ABI_PID from dynamic objects to the output.
ld/
* ldlang.c (lang_check): Call bfd_merge_private_bfd_data for
shared libraries.
Code in the linker, present before the addition of .gnu.attributes
support, results in shared libraries not being considered by BFD when
merging e_flags and .gnu.attributes from input files to the output.
That doesn't seem correct to me, but I don't know enough about all the
various ABIs to change the behaviour with any confidence. So this
patch merely punts on dynamic objects in merge_private_bfd_data target
functions, with a FIXME for maintainer attention.
I haven't excluded shared libraries from being considered where the
target merge_private_bfd_data (a) already has code dealing with shared
libraries, or (b) where that function just sets the output to the most
constraining arch/mach combination and other fairly trivial merges, or
(c) when the target has no shared library linker support.
In (a) are: arc, arm, aarch64, riscv, sparc.
In (b) are: bpf, cris, csky, m32r, m68k, mn10300, nios2, tilegx,
tilepro, vax, visium, xtensa.
In (c) are: bpf, cr16, h8300, iq2000, m32c, m68hc11, m68hc12, mcore,
mep, msp430, mt, rl78, rx, v850.
PR 25882
* elf32-bfin.c (elf32_bfin_merge_private_bfd_data): Add FIXME.
* elf32-frv.c (frv_elf_merge_private_bfd_data): Likewise.
* elfxx-mips.c (_bfd_mips_elf_merge_private_bfd_data): Likewise.
* elf32-nds32.c (nds32_elf_merge_private_bfd_data): Likewise.
* elf32-score.c (s3_elf32_score_merge_private_bfd_data): Likewise.
* elf32-score7.c (s7_elf32_score_merge_private_bfd_data): Likewise.
* elf32-sh.c (sh_elf_merge_private_data): Likewise.
* elf32-tic6x.c (elf32_tic6x_merge_attributes): Likewise.
* elf64-ia64-vms.c (elf64_ia64_merge_private_bfd_data): Likewise.
* elfnn-ia64.c (elfNN_ia64_merge_private_bfd_data): Likewise.
EF_PPC_RELOCATABLE and similar flags, if present in an input shared
library, don't have any relevance as far as the output file is
concerned.
Currently, dynamic objects aren't seen in merge_private_bfd_data.
This patch is in preparation for a change to that.
PR 25882
* elf32-ppc.c (ppc_elf_merge_private_bfd_data): Ignore e_flags
from shared libraries.
Fields marked with XTENSA_NDIFF relocations are not negated, they only
have sign bits removed. Don't negate their values when relaxation is
performed. Don't add sign bits when the value is zero. Report overflow
when the result has negative sign but all significant bits are zero.
2020-04-29 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* elf32-xtensa.c (relax_section): Don't negate diff_value for
XTENSA_NDIFF relocations. Don't add sign bits whe diff_value
equals 0. Report overflow when the result has negative sign but
all significant bits are zero.
ld/
* testsuite/ld-xtensa/relax-diff1.d: New test definition.
* testsuite/ld-xtensa/relax-diff1.s: New test source.
* testsuite/ld-xtensa/relax-ndiff.d: New test definition.
* testsuite/ld-xtensa/relax-ndiff.s: New test source.
* testsuite/ld-xtensa/xtensa.exp: (relax-diff1)
(relax-ndiff): New tests.
The zero check was on the wrong operand. And, yes, the second operand
popped is supposed to be divided by the first operand popped.
* vms-alpha.c (_bfd_vms_slurp_etir): Correct divide by zero check.
Emit warning message.
The 64-bit version of binutils got support for the PE COFF BIG OBJ format a
couple of years ago. The BIG OBJ format is a slightly different COFF format
which extends the size of the number of section field in the header from a
uint16_t to a uint32_t and so greatly increases the number of sections allowed.
However the 32-bit version of bfd never got support for this. The GHC Haskell
compiler generates a great deal of symbols due to it's use of
-ffunction-sections and -fdata-sections.
This meant that we could not build the 32-bit version of the GHC Compiler for
many releases now as binutils didn't have this support.
This patch adds the support to the 32-bit port of binutils as well and also does
come cleanup in the code.
bfd/ChangeLog:
* coff-i386.c (COFF_WITH_PE_BIGOBJ): New.
* coff-x86_64.c (COFF_WITH_PE_BIGOBJ): New.
* config.bfd (targ_selvecs): Rename x86_64_pe_be_vec
to x86_64_pe_big_vec as it not a big-endian format.
(vec i386_pe_big_vec): New.
* configure.ac: Likewise.
* targets.c: Likewise.
* configure: Regenerate.
* pe-i386.c (TARGET_SYM_BIG, TARGET_NAME_BIG,
COFF_WITH_PE_BIGOBJ): New.
* pe-x86_64.c (TARGET_SYM_BIG, TARGET_NAME_BIG):
New.
(x86_64_pe_be_vec): Moved.
gas/ChangeLog:
* NEWS: Add news entry for big-obj.
* config/tc-i386.c (i386_target_format): Support new format.
* doc/c-i386.texi: Add i386 support.
* testsuite/gas/pe/big-obj.d: Rename test to not be x64 specific.
* testsuite/gas/pe/pe.exp (big-obj): Make test run on i386 as well.
ld/ChangeLog:
* pe-dll.c (pe_detail_list): Add pe-bigobj-i386.
When a coredump is generated, there are a few registers in
ARC HS that are put under a special section, namely ".reg-v2".
It is for backward compatibility reasons with older tools that
we have decided not to extend the generic ".reg" section.
This patch makes it possible to display the information better
regarding that section. Compare the output of "readelf" without
and with these changes:
$ readelf -n core # without the patch
...
LINUX 0x0000000c Unknown note type: (0x00000600)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
$ readelf -n core # with the patch
...
LINUX 0x0000000c NT_ARC_V2 (ARC HS accumulator/extra registers)
description data: 78 08 00 00 2f 6c 64 2d 75 43 6c 69
In another commit (soon to be submitted), GDB will makes use of these
changes to parse the extra section and its registers.
bfd/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* elf-bfd.h (elfcore_write_arc_v2): Add prototype.
* elf.c (elfcore_grok_arc_v2): New function.
(elfcore_grok_note): Call the new function to handle the corresponding
note.
(elfcore_write_arc_v2): New function.
(elfcore_write_register_note): Call the new function to handle the
corresponding pseudo-sections.
binutils/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* readelf.c (get_note_type): Handle NT_ARC_V2.
include/elf/ChangeLog
2020-03-26 Anton Kolesov <anton.kolesov@synopsys.com>
* common.h (NT_ARC_V2): New macro definitions.
Introduce new relaxations XTENSA_PDIFF{8,16,32} for positive differences
(subtracted symbol precedes diminished symbol) and XTENSA_NDIFF{8,16,32}
for negative differences (subtracted symbol follows diminished symbol).
Don't generate XTENSA_DIFF relocations in the assembler, generate
XTENSA_PDIFF or XTENSA_NDIFF based on relative symbol position.
Handle XTENSA_DIFF in BFD for compatibility with old object files.
Handle XTENSA_PDIFF and XTENSA_NDIFF in BFD, treating difference value
as unsigned.
2020-04-22 Max Filippov <jcmvbkbc@gmail.com>
bfd/
* bfd-in2.h: Regenerated.
* elf32-xtensa.c (elf_howto_table): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
(elf_xtensa_reloc_type_lookup, elf_xtensa_do_reloc)
(relax_section): Add cases for R_XTENSA_PDIFF{8,16,32} and
R_XTENSA_NDIFF{8,16,32}.
* libbfd.h (bfd_reloc_code_real_names): Add names for
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
* reloc.c: Add documentation for BFD_RELOC_XTENSA_PDIFF{8,16,32}
and BFD_RELOC_XTENSA_NDIFF{8,16,32}.
binutils/
* readelf.c (is_none_reloc): Recognize
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32}.
gas/
* config/tc-xtensa.c (md_apply_fix): Replace
BFD_RELOC_XTENSA_DIFF{8,16,32} generation with
BFD_RELOC_XTENSA_PDIFF{8,16,32} and
BFD_RELOC_XTENSA_NDIFF{8,16,32} generation.
* testsuite/gas/xtensa/loc.d: Replace BFD_RELOC_XTENSA_DIFF16
with BFD_RELOC_XTENSA_PDIFF16 in the expected output.
include/
* elf/xtensa.h (elf_xtensa_reloc_type): New entries for
R_XTENSA_PDIFF{8,16,32} and R_XTENSA_NDIFF{8,16,32}.
ld/
* testsuite/ld-xtensa/relax-loc.d: New test definition.
* testsuite/ld-xtensa/relax-loc.s: New test source.
* testsuite/ld-xtensa/xtensa.exp (relax-loc): New test.
