afb1dbe851
Preliminary tests for sim-alu module.
1997-10-17 03:57:53 +00:00
9d59cbb13c
Make decl of sds_load static
1997-10-16 19:06:25 +00:00
b7dd310d55
opcodes/mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
1997-10-16 16:03:22 +00:00
3cd99cc646
fix typo
1997-10-16 12:22:05 +00:00
04e4681226
Fix mangled patch
1997-10-16 12:19:16 +00:00
ea985d2472
Move register definitions and macros out of interp.c and into sim-main.h
1997-10-16 03:50:48 +00:00
085c1cb988
Checkpoint IGEN version of MIPS simulator.
1997-10-16 03:41:57 +00:00
284e759d1f
Rename generated file engine.c to oengine.c.
1997-10-16 03:39:13 +00:00
339fb14904
* gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1997-10-16 03:29:47 +00:00
8b70f83790
* gencode.c (build_instruction): For "FPSQRT", output correct number
...
of arguments to Recip.
1997-10-16 03:23:16 +00:00
eaa202ddd4
* gen-semantics.c (print_semantic_body): Use CIA not cia.ip. Escape
...
newlines at end of generated call to sim_engine_abort.
1997-10-16 03:19:41 +00:00
fc1213aa0b
* peicode.h (pe_mkobject_hook): Set DLL flag.
...
(pe_bfd_copy_private_bfd_data): Copy DLL flag.
1997-10-15 20:34:26 +00:00
899f620488
* sparc/tm-sparc.h (STORE_STRUCT_RETURN): Change to handle --enable-64-bit-bfd.
1997-10-15 19:08:18 +00:00
223f2ecd9a
(STORE_STRUCT_RETURN): Change to handle --enable-64-bit-bfd.
1997-10-15 19:07:30 +00:00
a12e621548
* scripttempl/pe.sc: Put .stab and .stabstr sections at end.
1997-10-15 18:53:18 +00:00
c086885a66
* peicode.h (coff_swap_scnhdr_out): Set IMAGE_SCN_MEM_DISCARDABLE
...
for .stab* sections. Replace strlen of constant strings with
number.
1997-10-15 18:17:40 +00:00
048c2f0179
* config/sparc/tm-sparc.h (FIX_CALL_DUMMY): Mask off displacement
...
to 30 bits in call insn to handle --enable-64-bit-bfd.
1997-10-15 17:31:07 +00:00
f08be001ae
* gas/ieee-fp/x930509a.s: Tweak slightly to work on the PA.
...
[ pseudo-ops and directives must not start in column zero on the PA. ]
1997-10-15 16:40:48 +00:00
e35cf6e4e9
* gas/hppa/unsorted/unsorted.exp: Update for recent disassembler
...
changes.
1997-10-15 16:37:03 +00:00
326ca4ee57
Bring over from r5900 branch.
1997-10-15 04:11:06 +00:00
08ce71f5c4
* read.c (get_line_sb): Accept any eol marker while scanning macros.
1997-10-15 03:56:30 +00:00
10b8f7f036
* config/tc-alpha.h (DIFF_EXPR_OK): Define.
...
* config/tc-i386.h (DIFF_EXPR_OK): Define.
* config/tc-alpha.c (md_apply_fix): Notice fx_pcrel and substitute
the correct relocation when it exists.
* config/tc-i386.c (md_apply_fix3): Likewise.
* config/tc-ppc.h: Correct typo in comment.
* config/tc-v850.h: Likewise.
1997-10-15 02:17:00 +00:00
81b3b32cda
Sanitize additional files.
1997-10-15 00:05:28 +00:00
5a9bddea84
Enable d10v simulator testsuite - two tests: Hello World and exit47.
1997-10-15 00:00:41 +00:00
fd89abc204
Handle core regions which start at a poorly aligned address.
1997-10-14 23:45:52 +00:00
0543ba6ec8
Add function to determine if a symbol is located at a given address.
1997-10-14 23:12:18 +00:00
3516c09c60
New dummy function for symbol_at_address_func field of disassemble_info
...
structure.
Add code to use this field in v850 disassembly.
1997-10-14 23:09:59 +00:00
ecf4429f18
Added new field to disassemble_info structure to provide a function which
...
determines if a symbol can be found at a given address.
1997-10-14 23:05:34 +00:00
d980a81fbd
* elf64-alpha.c (elf64_alpha_merge_ind_symbols): New function to
...
merge got and reloc entries from ind syms to their target.
(elf64_alpha_always_size_sections): Call it.
(elf64_alpha_check_relocs): Operate on the target of indirect symbols.
(elf64_alpha_can_merge_gots): Likewise.
(elf64_alpha_merge_gots): Likewise.
* elf64-alpha.c (elf64_alpha_relocate_section): Back out HJ's change,
as it is insufficient to handle the relocation changes as well.
1997-10-14 22:46:33 +00:00
78fa3a1408
* h8300.h: Bit ops with absolute addresses not in the 8 bit
...
area are not available in the base model (H8/300).
pr 13467.
1997-10-14 19:19:15 +00:00
7456a10d9b
* sim-alu.h (ALU64_HAD_OVERFLOW): Define.
...
(ALU64_SUB): Define.
* Make-common.in (all): Build SIM_EXTRA_ALL first.
(.gdbinit): Remove dependencies, generate once per build.
1997-10-14 09:39:05 +00:00
055ee2977f
Checkpoint IGEN version of MIPS simulator.
1997-10-14 09:34:08 +00:00
5ccb90201f
remote-sim.h: Clarify sim_read, sim_write MEM argument.
1997-10-14 09:33:18 +00:00
0c2c5f6141
Move global MIPS simulator variables into sim_cpu struct.
1997-10-14 09:26:03 +00:00
1b217de0f3
Correct type of address argument for sim_core_{read,write}
1997-10-14 09:24:57 +00:00
18c64df613
o Add support for configuring wordsize, fp hardware and target
...
endianness. Provide defaults for some tier-1 mips targets.
o Parameterize all functions with SIM_DESC.
1997-10-14 07:27:31 +00:00
6a587c4aae
* elf64-alpha.c (elf64_alpha_calc_dynrel_sizes): Allow for RELATIVE
...
relocs for symbols in shlibs that have been forced local.
(elf64_alpha_relocate_section): Output RELATIVEs in .got for same.
1997-10-14 06:12:50 +00:00
3a13dd8f03
* bfd/elf64-alpha.c (elf64_alpha_relocate_section): Use the
...
got_enties of the default symbol for the default versioned
symbol. Patch from hjl@gnu.ai.mit.edu , modified not to use
alloca in the loop.
1997-10-14 04:24:59 +00:00
d5cecca93c
Output line-ref to original igen source file when generating trace
...
statements.
Define NIA macro (dependant on gen-delayed-branch).
Verify opening/closing quote in input assembler strings.
1997-10-14 02:54:08 +00:00
c7eece073a
RELOC_22_PCREL only uses bottom 24 bits of PC.
1997-10-14 00:34:46 +00:00
a0a5f4e2bd
Allow assembler to make parallel instructions where there the seconds
...
(latter) outputs intersect with the first (earlier) inputs.
1997-10-13 23:17:22 +00:00
856f843eef
* ecoff.c (PAGE_SIZE): Double to 8k as a hack to allow some C++
...
templated programs to build with -g.
1997-10-13 22:28:35 +00:00
1155e06e3f
* simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
...
exception generation code to OP_6E01.
(OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception
generation code.
PR 13550
1997-10-13 18:26:52 +00:00
b83093ff79
* simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
...
(OP_6601): Ditto.
PR 13498
1997-10-11 16:50:05 +00:00
93f0cb6975
* simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
...
(OP_6601): Ditto.
1997-10-11 16:48:47 +00:00
de0e22c1bf
Added .tcomon section initialisation.
1997-10-11 01:02:07 +00:00
c280609300
Jim fixed the fixups for conditional and unconditional branches.
...
Added code to support the bss and common sections in thr ZDA and SDA areas.
1997-10-11 00:55:57 +00:00
5ff4668dea
Fixed bug extracting displacement from a JR instruction.
1997-10-10 23:41:43 +00:00
676d3f022c
Fixed bugs exposed by compiling NEC sample sources.
1997-10-10 23:01:17 +00:00
e01e18a8b3
* configure.in (sparc): Set DEFAULT_ARCH from correct target.
...
* configure: Regenerated.
1997-10-10 22:02:59 +00:00
Andrew Cagney
Michael Meissner
Gavin Romig-Koch
Ian Lance Taylor
David Edelsohn
Jeff Law
Richard Henderson
Nick Clifton
Fred Fish