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32 Commits

Author SHA1 Message Date
Nick Clifton a3976a7c56 Fixes problems building the V850 simulator introduced with the previous delta. 
* sim-main.h (reg64_t): New type.
	(v850_regs): Add selID_sregs field.
	(VR, SAT16, SAT32, ABS16, ABS32 ): New macros.
	* v850-dc: Add fields for v850e3v5 instructions.
	* v850.igen (cvtf.dl): Use correctly signed local value.
	(cvtf.dw, cvtf.sw, trncf.dul, trncf.dl, trncf.sul, trncf.sw):
	Likewise.
	* interp.c: Fix old style function declarations.
	* simops.c: Likewise.
 2015-02-27 09:53:03 +00:00
Nick Clifton 9ad55e9b25 Adds support for emulating V850 e3v5 instructions to the simulator. 
* v850.igen: Add more e3v5 support.
	(FMAF.S): New pattern.
	(FMSF.S): New pattern.
	(FNMAF.S): New pattern.
	(FNMSF.S): New pattern.
	(cnvq15q30): New pattern.
	(cnvq30q15): New pattern.
	(cnvq31q62): New pattern.
	(cnvq62q31): New pattern.
	(dup.h): New pattern.
	(dup.w): New pattern.
	(expq31): New pattern.
	(modadd): New pattern.
	(mov.dw): New pattern.
	(mov.h): New pattern.
	(mov.w): New pattern.
	(pki16i32): New pattern.
	(pki16ui8): New pattern.
	(pki32i16): New pattern.
	(pki64i32): New pattern.
	(pkq15q31): New pattern.
	(pkq30q31): New pattern.
	(pkq31q15): New pattern.
	(pkui8i16): New pattern.
	(vabs.h): New pattern.
	(vabs.w): New pattern.
	(vadd.dw): New placeholder pattern.
	(vadd.h): New placeholder pattern.
	(vadd.w): New placeholder pattern.
	(vadds.h): New placeholder pattern.
	(vadds.w): New placeholder pattern.
	(vaddsat.h): New placeholder pattern.
	(vaddsat.w): New placeholder pattern.
	(vand): New pattern.
	(vbiq.h): New placeholder pattern.
	(vbswap.dw): New placeholder pattern.
	(vbswap.h): New placeholder pattern.
	(vbswap.w): New placeholder pattern.
	(vcalc.h): New placeholder pattern.
	(vcalc.w): New placeholder pattern.
	(vcmov): New placeholder pattern.
 2015-02-24 17:58:50 +00:00
Nick Clifton fd7b2a545d * v850.igen (LDSR): Accept but ignore a selID parameter. 2013-05-13 10:52:52 +00:00
Nick Clifton 67d7515b0a * simops.c (v850_rotl): New function. 
(v850_bins): New function.
	* simops.h: Add prototypes fir v850_rotl and v850_bins.
	* v850-dc: Add entries for V850e3v5.
	* v850.igen: Add support for v850e3v5.
	(ld.dw, st.dw, rotl, bins): New patterns.
 2013-01-28 10:06:51 +00:00
Nick Clifton 853678261b * interp.c (sim_open): Add support for bfd_arch_v850_rh850 
architecture type.  Add support for bfd_mach_v850e2 and
	bfd_mach_v850e2v3 machine numbers.
        * v850.igen (dbtrap): Add support for SIM_OPEN_DEBUG.
        (cmpf.d): Correct order of operands.
        (cmpf.s): Likewise.
        (trncf.dul): New pattern.
        (trncf.duw): New pattern.
        (trncf.sul): New pattern.
        (trncf.suw): New pattern.
        * v850-dc: Correct bitfield selection for TRNCF.SW and CVTF.SW.
 2013-01-10 09:57:02 +00:00
Nick Clifton d99ff40fae * v850.igen (W,WWWW): Correct computation of register number. 
(JR32): Remove unnecessary comma.
	(cmovf.s): Register 0 is an invalid source register.
	(maddf.s): Remove bogus intermediary rounding.
	(nmaddf.s): Likewise.
	(trncf.sl): Remove bogus initial rounding.
	(trncf.dw): Likewise.
	(trncf.sl): Likewise.
	(trncf.sw): Likewise.
 2012-09-13 08:09:26 +00:00
Kevin Buettner 2aaed97917 Commit gdb and sim support for v850e2 and v850e2v3 on behalf of 
Rathish C <Rathish.C@kpitcummins.com>.
 2012-03-29 00:57:19 +00:00
DJ Delorie 98e460c30d * simops.c (OP_1C007E0): Compensate for 64 bit hosts. 
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
 2008-02-06 04:41:26 +00:00
DJ Delorie c5fbc25baf Index: ChangeLog 
* configure.ac (v850): V850 now has a testsuite.
	* configure (v850): Likewise.

Index: testsuite/ChangeLog

	* sim/v850/: New directory.
	* sim/v850/allinsns.exp: New.
	* sim/v850/bsh.cgs: New.
	* sim/v850/div.cgs: New.
	* sim/v850/divh.cgs: New.
	* sim/v850/divh_3.cgs: New.
	* sim/v850/divhu.cgs: New.
	* sim/v850/divu.cgs: New.
	* sim/v850/sar.cgs: New.
	* sim/v850/satadd.cgs: New.
	* sim/v850/satsub.cgs: New.
	* sim/v850/satsubi.cgs: New.
	* sim/v850/satsubr.cgs: New.
	* sim/v850/shl.cgs: New.
	* sim/v850/shr.cgs: New.
	* sim/v850/testutils.cgs: New.
	* sim/v850/testutils.inc: New.

Index: v850/ChangeLog

	* simops.c (OP_C0): Correct saturation logic.
	(OP_220): Likewise.
	(OP_A0): Likewise.
	(OP_660): Likewise.
	(OP_80): Likewise.

	* simops.c (OP_2A0): If the shift count is zero, clear the
	carry.
	(OP_A007E0): Likewise.
	(OP_2C0): Likewise.
	(OP_C007E0): Likewise.
	(OP_280): Likewise.
	(OP_8007E0): Likewise.

	* simops.c (OP_2C207E0): Correct PSW flags for special divu
	conditions.
	(OP_2C007E0): Likewise, for div.
	(OP_28207E0): Likewise, for divhu.
	(OP_28007E0): Likewise, for divh.  Also, sign-extend the correct
	operand.
	* v850.igen (divh): Likewise, for 2-op divh.

	* v850.igen (bsh): Fix carry logic.
 2008-02-06 00:40:05 +00:00
Nick Clifton c5ea1d538f Add support for v850e1 instructions 2003-09-05 17:46:52 +00:00
Nick Clifton ebc115b7bb * simops.c (OP_40): Delete. Move code to... 
* v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.
 2003-04-06 08:51:04 +00:00
Nick Clifton 5d6a173dca Remove v850ea references 2002-09-19 07:52:02 +00:00
Nick Clifton 896ad91016 Remove illegal instruciton pattern, since it is the same as the breakpoint 
pattern.
 2000-05-30 18:36:57 +00:00
Frank Ch. Eigler b9791fcdd6 * merge from internal tree 
2000-04-14  Gary Thomas  <gthomas@redhat.com>

	* v850.igen: Define 'br *' as illegal since this is the only
	way to provide a breakpoint on some v850 family processors.
 2000-05-08 23:07:39 +00:00
Frank Ch. Eigler de616bc738 * more compatibility with v850 hardware 
2000-03-24  Frank Ch. Eigler  <fche@redhat.com>

	* v850.igen (ilgop): New insn pattern for four-byte breakpoints.
 2000-03-25 00:17:21 +00:00
Stan Shebs c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs 071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Nick Clifton 22c39e1487 Reverrt BREAK value back to its old value 1997-12-05 17:27:34 +00:00
Nick Clifton b65b4d8b06 Fixed sanitization, 
Changed pattern for break insn.
 1997-12-04 01:29:25 +00:00
Andrew Cagney a276b6f057 Clean up tracing for Bcond & jmp insns. 
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
 1997-09-19 06:39:21 +00:00
Andrew Cagney bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
Andrew Cagney 60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
Andrew Cagney a72f8fb439 Clean up more tracing. 
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
 1997-09-17 08:14:23 +00:00
Andrew Cagney 6aead89a5f Fix tracing for: "ctret", "bsw", "hsw" 
Fix bugs in: "bsh", "callt", "stsr".
 1997-09-17 05:31:00 +00:00
Andrew Cagney fb1fd47514 Smooth some of ALU tracing's rough edges. 
Fix switch insn.
 1997-09-16 14:00:15 +00:00
Andrew Cagney c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits. 
For v850eq, include PSW[US] in bits that can be modified.
 1997-09-16 04:49:24 +00:00
Andrew Cagney 721478d51b Add v850e version of breakpoint instruction. 1997-09-16 02:15:55 +00:00
Andrew Cagney 4dda50b052 For instructions moved into v850.igen was computing (wrong) NIA when 
this wasn't needed.
 1997-09-15 23:09:26 +00:00
Andrew Cagney bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
Andrew Cagney 658303f7d4 For v850eq start up with US bit set. 
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
 1997-09-15 08:18:20 +00:00
Andrew Cagney 410230cf6d Check reserved bits before executing instructions. 
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
 1997-09-12 05:56:38 +00:00
Andrew Cagney 5d37a07bc5 Add multi-sim support to v850/v850e/v850eq simulators. 1997-09-08 17:42:48 +00:00