093e9a32d3
* simops.c: Handle "break" instruction.
1996-12-16 22:31:37 +00:00
16d2e2b670
* simops.c: Fix restoring the PC for "ret" and "retf" instructions.
1996-12-16 17:08:10 +00:00
191c9d73de
* gencode.c (write_opcodes): Also write out the format of the
...
opcode.
* mn10300_sim.h (simops): Add "format" field.
* interp.c (sim_resume): Deal with endianness issues here.
1996-12-11 16:58:33 +00:00
95d18eb74d
* simops.c (REG0_4): Define.
...
Use REG0_4 for indexed loads/stores.
Fixes bugs exposed after minor codegen improvements in the compiler.
1996-12-10 22:10:07 +00:00
2e8f4133d7
* simops.c (REG0_16): Fix typo.
1996-12-07 16:54:57 +00:00
5084d8e513
Add missing semicolons in last change.
1996-12-07 00:36:50 +00:00
b2f7a7e5b3
* simops.c: Call abort for any instruction that's not currently
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simulated.
1996-12-06 21:49:27 +00:00
9f4a551e11
* simops.c: Define accessor macros to extract register
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values from instructions. Use them consistently.
1996-12-06 21:47:21 +00:00
7c52bf32f2
* interp.c: Delete unused global variable "OP".
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(sim_resume): Remove unused variable "opcode".
* simops.c: Fix some uninitialized variable problems, add
parens to fix various -Wall warnings.
Fixing assorted -Wall problems.
1996-12-06 21:33:48 +00:00
fc038f5656
Opps. Forgot something in last change.
1996-12-06 21:20:17 +00:00
d252301029
* gencode.c (write_header): Add "insn" and "extension" arguments
...
to the OP_* declarations.
(write_template): Similarly for function templates.
* interp.c (insn, extension): Remove global variables. Instead
pass them as arguments to the OP_* functions.
* mn10300_sim.h: Remove decls for "insn" and "extension".
* simops.c (OP_*): Accept "insn" and "extension" as arguments
instead of using globals.
Starting to clean things up.
1996-12-06 21:19:37 +00:00
e5a7a53799
* simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
...
Fixes remaining hangs while running c-torture execution tests.
Only 12 c-torture execution failures left:
* 920625-1.c fails all 6 execution tests.
* 960521-1.c fails all 6 execution tests.
1996-12-06 07:57:21 +00:00
4d8ced6cb1
* simops.c: Fix thinkos in last change to "inc dn".
1996-12-06 05:30:24 +00:00
61ecca95c0
* simops.c: "add imm,sp" does not effect the condition codes.
...
"inc dn" does effect the condition codes.
Just something I noticed.
1996-12-04 18:02:00 +00:00
e4e1302293
* simops.c: Treat both operands as signed values for
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"div" instruction.
Fixes another dozen c-torture execution failures.
1996-12-04 05:00:49 +00:00
20e1ab85bf
* simops.c: Fix simulation of division instructions.
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Fix typos/thinkos in several "cmp" and "sub" instructions.
Another couple dozen c-torture failures fixed.
1996-12-04 00:42:01 +00:00
216e65571a
* simomps.c: Fix carry bit handling in "sub" and "cmp"
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instructions.
Another dozen execution failures fixed.
1996-12-02 20:12:08 +00:00
fcfaf40d78
* simops.c: Fix "mov imm8,an" and "mov imm16,dn".
...
Fixes 80 or so c-torture execution failures. 400 to go.
1996-12-02 19:35:55 +00:00
b7b89deb44
* simops.c: Fix overflow computation for many instructions.
...
Fixes several hangs in the c-torture execution tests. Also fixes about
40 failures.
1996-12-02 08:35:20 +00:00
af388638ae
* simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
...
Along with some compiler, bfd, assembler changes this fixes 90 or so
c-torture execution failures.
1996-12-02 07:38:10 +00:00
c8f0171f5f
* simops.c: Fix "mov am, dn".
...
Fixes more c-torture problems.
1996-12-02 04:23:37 +00:00
6db7fc49d2
* simops.c: Fix more bugs in "add imm,an" and
...
"add imm,dn".
Fixes a half-dozen (of several hundred :( c-torture failures.
1996-12-01 23:10:04 +00:00
6e7a01c144
* simops.c: Fix bugs in "movm" and "add imm,an".
...
main(){write (0, "hello world\n", 13);} works!
1996-11-27 23:20:24 +00:00
3bb3fe44e0
* simops.c: Don't lose the upper 24 bits of the return
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pointer in "call" and "calls" instructions. Rough cut
at emulated system calls.
1996-11-27 18:36:54 +00:00
de0dce7c5c
* simops.c: Implement the remaining 5, 6 and 7 byte instructions.
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Everything except the extended instructions, the loop instructions,
trap, rti, and rtm.
1996-11-27 17:56:10 +00:00
ecb4b5a357
* simops.c Implement remaining 4 byte instructions.
1996-11-27 17:19:44 +00:00
2e35551c74
* simops.c Implement remaining 3 byte instructions.
...
Moving right along...
1996-11-27 16:51:30 +00:00
f5f13c1d73
* simops.c: Implement remaining 2 byte instructions. Call
...
abort for instructions we're not implementing now.
1996-11-27 16:25:03 +00:00
707641f658
* simops.c: Implement lots of random instructions.
...
Implments most instructions with first nibble 0x0 - 0xe and
those with the first byte 0xf0 - 0xf2.
1996-11-27 07:20:36 +00:00
1f3bea2169
* simops.c: Implement "movm" and "bCC" insns.
...
Function calls and conditional branches work!
1996-11-27 05:29:49 +00:00
92284aaa35
* mn10300_sim.h (_state): Add another register (MDR).
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(REG_MDR): Define.
* simops.c: Implement "cmp", "calls", "rets", "jmp" and
a few additional random insns.
We can now function calls. We get out of crt0 into main now, then lose
when calls are nested (because don't handle movm yet).
1996-11-27 00:53:25 +00:00
73e6529893
* mn10300_sim.h (PSW_*): Define for CC status tracking.
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(REG_D0, REG_A0, REG_SP): Define.
* simops.c: Implement "add", "addc" and a few other random
instructions.
Starting to simulate instructions for the mn10300. Executes some of
the crt0 code now!
1996-11-26 22:58:24 +00:00
b5f831ac51
* gencode.c, interp.c: Snapshot current simulator code.
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(crude) hashing works, along with dispatch to the OP_* functions.
1996-11-26 20:40:19 +00:00
05ccbdfdd2
* Makefile.in, config.in, configure, configure.in: New files.
...
* gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
Skeleton mn10300 simulator
1996-11-25 19:52:08 +00:00
Jeff Law