Commit Graph

255 Commits

Author SHA1 Message Date
Nick Clifton ca9a79a174 Add support for relaxation of bit manipulation instructions. 2004-01-12 15:02:22 +00:00
Nick Clifton 875a0b1471 (BITOP): Dissallow operations on @aa:16 and @aa:32 except for the H8S. 2004-01-09 17:47:17 +00:00
Alan Modra c9e214e571 Split ChangeLog files. 2004-01-02 11:16:21 +00:00
Maciej W. Rozycki 1abe91b1db * config/tc-mips.c (macro): Handle new macros: "lca" and "dlca"
for loading addresses using CALL relocations.
Don't emit CALL relocations when a base register is used.

* gas/mips/lca-svr4pic.d: New test for the "lca" macro.
* gas/mips/lca-xgot.d: Likewise.
* gas/mips/lca.s: Source for the new tests.
* gas/mips/mips.exp: Run the new tests.

* opcode/mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB.

* mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and
"dlca".
2003-11-18 21:22:57 +00:00
Nick Clifton 3e60263266 Add ColfFire v4 support 2003-10-21 13:28:59 +00:00
Hans-Peter Nilsson 906e88d4fb * mmix.h (JMP_INSN_BYTE): Define. 2003-10-19 01:16:56 +00:00
Chris Demetriou 5f74bc130d [ bfd/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* archures.c (bfd_mach_mipsisa64r2): New define.
	* bfd-in2.h: Regenerate.
	* aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2.
	* cpu-mips.c (I_mipsisa64r2): New enum value.
	(arch_info_struct): Add entry for I_mipsisa64r2.
	* elfxx-mips.c (_bfd_elf_mips_mach)
	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2.
	(mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case.
	(mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2.

[ binutils/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2.

[ gas/Changelog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs.
	* configure: Regenerate.
	* config/tc-mips.c (imm2_expr): New variable.
	(md_assemble, mips16_ip): Initialize imm2_expr.
	(ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2.
	(macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands.
	(macro): Handle M_DEXT and M_DINS.
	(validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands.
	(mips_ip): Likewise.
	(OPTION_MIPS64R2): New define.
	(md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2).
	OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2.
	(md_parse_option): Handle OPTION_MIPS64R2.
	(s_mipsset): Handle setting "mips64r2" ISA.
	(mips_cpu_info_table): Add mips64r2.
	(md_show_usage): Document -mips64r2 option.
	* doc/as.texinfo: Docuemnt -mips64r2 option.
	* doc/c-mips.texi: Likewise.

[ gas/testsuite/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0-names-mips64r2.d: New file.
	* gas/mips/cp0sel-names-mips64r2.d: New file.
	* gas/mips/elf_arch_mips64r2.d: New file.
	* gas/mips/hwr-names-mips64r2.d: New file.
	* gas/mips/mips32r2-ill-fp64.l: New file.
	* gas/mips/mips32r2-ill-fp64.s: New file.
	* gas/mips/mips64r2-ill.l: New file.
	* gas/mips/mips64r2-ill.s: New file.
	* gas/mips/mips64r2.d: New file.
	* gas/mips/mips64r2.s: New file.
	* gas/mips/mips.exp: Define "mips64r2" arch, and run new tests.

[ include/elf/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h (E_MIPS_ARCH_64R2): New define.

[ include/opcode/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Document +E, +F, +G, +H, and +I operand types.
	Update documentation of I, +B and +C operand types.
	(INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines.
	(M_DEXT, M_DINS): New enum values.

[ ld/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* ldmain.c (get_emulation): Ignore "-mips64r2".

[ ld/testsuite/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
	with MIPS64r2.

[ opcodes/ChangeLog ]
2003-09-30  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_arch_choices): Add entry for "mips64r2"
	(print_insn_args): Add handing for +E, +F, +G, and +H.
	* mips-opc.c (I65): New define for MIPS64r2.
	(mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins",
	"dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh",
	and "dshd" for MIPS64r2.  Adjust "dror", "dror32", and "drorv" to
	be supported on MIPS64r2.
2003-09-30 16:17:15 +00:00
Nick Clifton 8ad30312ff Add binutils support for v850e1 processor 2003-09-04 11:04:38 +00:00
Alan Modra 68d23d2157 * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
PPC_OPCODE_* defines.
2003-08-19 07:08:20 +00:00
Jason Eckhardt be6389fdef include/opcode/ChangeLog:
2003-08-16  Jason Eckhardt  <jle@rice.edu>

        * i860.h (fmov.ds): Expand as famov.ds.
        (fmov.sd): Expand as famov.sd.
        (pfmov.ds): Expand as pfamov.ds.

gas/testsuite/ChangeLog:
2003-08-16  Jason Eckhardt  <jle@rice.edu>

        * gas/i860/pseudo-ops01.{s,d}: New files.
        * gas/i860/i860.exp: Execute the new test above.
        * gas/i860/README.i860: Mention that pseudo-ops need more testing
        and remove the align fill defect from the list.
2003-08-17 03:16:23 +00:00
Michael Meissner 10e05405ac Convert cgen to C-90 2003-08-08 21:21:24 +00:00
Alan Modra 8cf3f35467 Convert to C90. 2003-08-07 02:25:50 +00:00
Michael Snyder 7951f401ae 2003-07-18 Michael Snyder <msnyder@redhat.com>
* include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting.
2003-07-29 21:05:31 +00:00
Richard Sandiford 5a7ea74950 include/opcode/
* mips.h (CPU_RM7000): New macro.
	(OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns.

bfd/
	* archures.c (bfd_mach_mips7000): New.
	* bfd-in2.h: Regenerated.
	* cpu-mips.c (arch_info_struct): Add an entry for mips:7000.
	* elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips7000.
	(mips_mach_extensions): Add an entry for it.

opcodes/
	* mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries.

gas/
	* config/tc-mips.c (hilo_interlocks): True for CPU_RM7000.
	(mips_cpu_info_table): Add rm7000 and rm9000 entries.

gas/testsuite/
	* gas/mips/rm7000.[sd]: New test.
	* gas/mips/mips.exp: Run it.
2003-07-15 07:50:39 +00:00
Alexandre Oliva 7ba1864d6b 2000-04-01 Alexandre Oliva <aoliva@cygnus.com>
* mn10300.h (AM33_2): Renamed from AM33.
2000-03-31  Alexandre Oliva  <aoliva@cygnus.com>
* mn10300.h (AM332, FMT_D3): Defined.
(MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise.
(MN10300_OPERAND_FPCR): Likewise.
2003-07-10 02:49:07 +00:00
Martin Schwidefsky c72a8f697c * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. 2003-07-01 14:46:57 +00:00
Richard Sandiford 2d0d09ca83 include/opcode/
* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
	(IMM8U, IMM8U_NS): Define.
	(h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.

gas/
	* config/tc-h8300.c (get_specific): Allow ':8' to be used for
	unsigned 8-bit operands.

gas/testsuite/
	* gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy.
2003-06-25 15:31:59 +00:00
Richard Sandiford 8d1e520a64 * include/opcode/h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd
and mov.l ERs,@(dd:32,ERd) entries.
2003-06-25 15:19:40 +00:00
H.J. Lu ca164297eb gas/
2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
	Instructions.

	* gas/config/tc-i386.h (CpuPNI): New.
	(CpuUnknownFlags): Add CpuPNI.

gas/testsuite/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add prescott.

	* gas/i386/prescott.d: New file.
	* gas/i386/prescott.s: Likewise.

include/opcode/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Precott New Instructions.

opcodes/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
	Intel Precott New Instructions.
	(PREGRP27): New. Added for "addsubpd" and "addsubps".
	(PREGRP28): New. Added for "haddpd" and "haddps".
	(PREGRP29): New. Added for "hsubpd" and "hsubps".
	(PREGRP30): New. Added for "movsldup" and "movddup".
	(PREGRP31): New. Added for "movshdup" and "movhpd".
	(PREGRP32): New. Added for "lddqu".
	(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
	Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
	entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
	entry 0xd0. Use PREGRP32 for entry 0xf0.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(grps): Use PNI_Fixup in the "sidtQ" entry.
	(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
	PREGRP31 and PREGRP32.
	(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
	Use "fisttpll" in entry 1 in opcode 0xdd.
	Use "fisttp" in entry 1 in opcode 0xdf.
2003-06-23 20:15:34 +00:00
Michael Snyder 50649e423e Fix typo. 2003-06-19 02:56:24 +00:00
Alan Modra adadcc0cc9 Add "attn", "lq" and "stq" power4 insns. 2003-06-10 07:44:11 +00:00
Richard Sandiford 2a93846b50 include/opcode/
* h8300.h (IMM4_NS, IMM8_NS): New.
	(h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries.
	Likewise IMM8 for mov.w and mov.l.  Likewise IMM16U for mov.l.

gas/testsuite
	* gas/h8300/h8sx_mov_imm.[sd]: New test.
	* gas/h8300/h8300.exp: Run it.
2003-06-10 07:33:46 +00:00
Michael Snyder 66f2268e0d 2003-06-03 Michael Snyder <msnyder@redhat.com>
* h8sx.h (enum h8_model): Add AV_H8S to distinguish from H8H.
	(ldc): Split ccr ops from exr ops (which are only available
	on H8S or H8SX).
	(stc): Ditto.
	(andc, orc, xorc): Ditto.
	(ldmac, stmac, clrmac, mac): Change access to AV_H8S.
2003-06-05 18:47:12 +00:00
Michael Snyder 5f250e29bf 2003-06-03 Michael Snyder <msnyder@redhat.com>
and Bernd Schmidt   <bernds@redhat.com>
	and Alexandre Oliva <aoliva@redhat.com>
	* h8300.h: Add support for h8300sx instruction set.
2003-06-03 21:23:21 +00:00
Jason Eckhardt 14218d5f24 2003-05-23 Jason Eckhardt <jle@rice.edu>
gas:
        * config/tc-i860.c (target_xp): Declare variable.
        (OPTION_XP): Declare macro.
        (md_longopts): Add option -mxp.
        (md_parse_option): Set target_xp.
        (md_show_usage): Add -mxp usage.
        (i860_process_insn): Recognize XP registers bear, ccr, p0-p3.
        (md_assemble): Don't try expansions if XP_ONLY is set.
        * doc/c-i860.texi: Document -mxp option.

gas/testsuite:
        * gas/i860/xp.s: New file.
        * gas/i860/xp.d: New file.

include/opcode:
        * i860.h (expand_type): Add XP_ONLY.
        (scyc.b): New XP instruction.
        (ldio.l): Likewise.
        (ldio.s): Likewise.
        (ldio.b): Likewise.
        (ldint.l): Likewise.
        (ldint.s): Likewise.
        (ldint.b): Likewise.
        (stio.l): Likewise.
        (stio.s): Likewise.
        (stio.b): Likewise.
        (pfld.q): Likewise.

opcodes:
        * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3.
        (print_insn_i860): Grab 4 bits of the control register field
        instead of 3.
2003-05-24 04:22:23 +00:00
Jason Eckhardt 941bbe7882 2003-05-20 Jason Eckhardt <jle@rice.edu>
opcode/i860.h (flush): Set lower 3 bits properly and use 'L'
        for the immediate operand type instead of 'i'.
2003-05-21 05:06:49 +00:00
Jason Eckhardt ca464f3718 2003-05-20 Jason Eckhardt <jle@rice.edu>
opcode/i860.h (fzchks): Both S and R bits must be set.
        (pfzchks): Likewise.
        (faddp): Likewise.
        (pfaddp): Likewise.
        (fix.ss): Remove (invalid instruction).
        (pfix.ss): Likewise.
        (ftrunc.ss): Likewise.
        (pftrunc.ss): Likewise.
2003-05-21 02:06:40 +00:00
Jason Eckhardt b645cb1726 2003-05-18 Jason Eckhardt <jle@rice.edu>
gas:
        * config/tc-i860.c (i860_process_insn): Initialize fc after
        each opcode mismatch.

include/opcode:
        * i860.h (form, pform): Add missing .dd suffix.

opcodes:
        * i860-dis.c (print_insn_i860): Instruction shrd has a dual bit,
        print it.

bfd:
        * elf32-i860.c (elf32_i860_relocate_highadj): Simplify calculation.
2003-05-18 21:24:33 +00:00
Stephane Carrez 87a45149d4 * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 2003-05-13 19:28:14 +00:00
Michael Snyder a68f3a3f68 2003-04-07 Michael Snyder <msnyder@redhat.com>
* h8300.h (ldc/stc): Fix up src/dst swaps.
2003-04-13 16:50:31 +00:00
Alan Modra 27abff5434 * mips.h: Correct comment typo. 2003-04-09 00:12:24 +00:00
Svein Seldal be33c5dd4d Namespace cleanup for the tic4x target. Replace s/c4x/tic4x/ and s/c3x/tic3x/. 2003 copyright update 2003-04-04 08:15:15 +00:00
Martin Schwidefsky 1bd490c46b * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val.
(S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH.
	(s390_opcode): Remove architecture. Add modes and min_cpu.
2003-03-21 13:26:21 +00:00
Nick Clifton c8cc2f3250 (O_SYS_CMDLINE): New pseudo opcode for command line processing. 2003-03-17 10:34:29 +00:00
Nick Clifton d1c1f9109a (ldmac, stmac): Replace MACREG with MS32 and MD32. 2003-02-21 11:36:59 +00:00
Dave Anglin 974a8e9cbf * hppa.h (ldwa, ldda): Add ordered opcodes. 2003-01-31 21:24:32 +00:00
Alan Modra f0abc2a11f include/elf/ChangeLog
* sh.h: Split out various bits to bfd/elf32-sh64.h.

include/opcode/ChangeLog
	* m68hc11.h (cpu6812s): Define.

bfd/ChangeLog
	* elf-bfd.h (struct bfd_elf_section_data): Remove tdata.  Change
	dynindx to an int.  Rearrange for better packing.
	* elf.c (_bfd_elf_new_section_hook): Don't alloc if already done.
	* elf32-mips.c (bfd_elf32_new_section_hook): Define.
	* elf32-sh64.h: New.  Split out from include/elf/sh.h.
	(struct _sh64_elf_section_data): New struct.
	(sh64_elf_section_data): Don't dereference sh64_info (was tdata).
	* elf32-sh64-com.c: Include elf32-sh64.h.
	* elf32-sh64.c: Likewise.
	(sh64_elf_new_section_hook): New function.
	(bfd_elf32_new_section_hook): Define.
	(sh64_elf_fake_sections): Adjust for sh64_elf_section_data change.
	(sh64_bfd_elf_copy_private_section_data): Likewise.
	(sh64_elf_final_write_processing): Likewise.
	* elf32-sparc.c (struct elf32_sparc_section_data): New.
	(elf32_sparc_new_section_hook): New function.
	(SET_SEC_DO_RELAX, SEC_DO_RELAX): Delete.
	(sec_do_relax): Define.
	(elf32_sparc_relax_section): Adjust to use sec_do_relax.
	(elf32_sparc_relocate_section): Likewise.
	* elf64-mips.c (bfd_elf64_new_section_hook): Define.
	* elf64-mmix.c (struct _mmix_elf_section_data): New.
	(mmix_elf_section_data): Define.  Use throughout file.
	(mmix_elf_new_section_hook): New function.
	(bfd_elf64_new_section_hook): Define.
	* elf64-ppc.c (struct _ppc64_elf_section_data): New.
	(ppc64_elf_section_data): Define.  Use throughout.
	(ppc64_elf_new_section_hook): New function.
	(bfd_elf64_new_section_hook): Define.
	* elf64-sparc.c (struct sparc64_elf_section_data): New.
	(sparc64_elf_new_section_hook): New function.
	(SET_SEC_DO_RELAX, SEC_DO_RELAX): Delete.
	(sec_do_relax): Define.
	(sparc64_elf_relax_section): Adjust to use sec_do_relax.
	(sparc64_elf_relocate_section): Likewise.
	(bfd_elf64_new_section_hook): Define.
	* elfn32-mips.c (bfd_elf32_new_section_hook): Define.
	* elfxx-mips.c (struct _mips_elf_section_data): New.
	(mips_elf_section_data): Define.  Use throughout.
	(_bfd_mips_elf_new_section_hook): New function.
	(mips_elf_create_got_section): Don't alloc used_by_bfd.
	* elfxx-mips.h (_bfd_mips_elf_new_section_hook): Declare.
	* elfxx-target.h (bfd_elfNN_new_section_hook): Add #ifndef.
	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

opcodes/ChangeLog
	* sh64-dis.c: Include elf32-sh64.h.
	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

gas/ChangeLog
	* config/tc-sh64.c (shmedia_frob_section_type): Adjust for changed
	sh64_elf_section_data.
	* config/tc-sh64.h: Include elf32-sh64.h.
	* config/tc-m68hc11.c: Don't include stdio.h.
	(md_show_usage): Fix missing continuation.
	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.

ld/ChangeLog
	* emultempl/sh64elf.em: Include elf32-sh64.h.
	(sh64_elf_${EMULATION_NAME}_before_allocation): Adjust for changed
	sh64_elf_section_data.
	(sh64_elf_${EMULATION_NAME}_after_allocation): Likewise.
2003-01-23 11:51:35 +00:00
Chris Demetriou 626d0adf84 2003-01-07 Chris Demetriou <cgd@broadcom.com>
* mips.h: Fix missing space in comment.
        (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5)
        (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right
        by four bits.
2003-01-08 07:36:47 +00:00
Chris Demetriou 071742cf97 [ gas/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * config/tc-mips.c: Update copyright years to include 2003.
        (mips_ip): Fix indentation of "+A", "+B", and "+C" handling.
        Additionally, clean up their code slightly and clean up their
        comments some more.


        * doc/c-mips.texi: Add MIPS32r2 to ".set mipsN" documentation.

[ gas/testsuite/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/elf_arch_mips32r2.d: Fix file description comment.

[ include/opcode/ChangeLog ]
2003-01-02  Chris Demetriou  <cgd@broadcom.com>

        * mips.h: Update copyright years to include 2002 (which had
        been missed previously) and 2003.  Make comments about "+A",
        "+B", and "+C" operand types more descriptive.
2003-01-02 20:03:09 +00:00
Chris Demetriou bbcc08074f [ gas/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (validate_mips_insn, mips_ip): Recognize
	the "+D" operand, which will be used only by the disassembler.

[ gas/testsuite/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0sel-names-mips32.d: New test.
	* gas/mips/cp0sel-names-mips32r2.d: New test.
	* gas/mips/cp0sel-names-mips64.d: New test.
	* gas/mips/cp0sel-names-numeric.d: New test.
	* gas/mips/cp0sel-names-sb1.d: New test.
	* gas/mips/cp0sel-names.s: New test source file.
	* gas/mips/mips.exp: Run new tests.

[ include/opcode/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Note that the "+D" operand type name is now used.

[ opcodes/ChangeLog ]
2002-12-31  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0sel_name): New structure.
	(mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2)
	(mips_cp0sel_names_sb1): New arrays.
	(mips_arch_choice): New structure members "cp0sel_names" and
	"cp0sel_names_len".
	(mips_arch_choices): Add references to new cp0sel_names arrays
	as appropriate, and make all existing entries reference
	appropriate mips_XXX_names_numeric arrays rather than simply
	using NULL.
	(mips_cp0sel_names, mips_cp0sel_names_len): New variables.
	(lookup_mips_cp0sel_name): New function.
	(set_default_mips_dis_options): Set mips_cp0sel_names and
	mips_cp0sel_names_len as appropriate.  Remove now-unnecessary
	checks for NULL register name arrays.
	(parse_mips_dis_option): Likewise.
	(print_insn_arg): Handle "+D" operand type.
	* mips-opc.c (mips_builtin_opcodes): Add new "+D" variants
	of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register
	names symbolically.
2002-12-31 08:11:18 +00:00
Chris Demetriou af7ee8bfa9 [ bfd/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case.
	* archures.c (bfd_mach_mipsisa32r2): New define.
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_mipsisa32r2): New enum value.
	(arch_info_struct): Add entry for I_mipsisa32r2.
	* elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach)
	(_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2.
	(_bfd_mips_elf_final_write_processing): Add
	bfd_mach_mipsisa32r2 case.
	(_bfd_mips_elf_merge_private_bfd_data): Handle merging of
	binaries marked as using MIPS32 Release 2.

[ binutils/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register)
	changes in MIPS -M options.

[ gas/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* configure.in: Recognize mipsisa32r2, mipsisa32r2el, and
	CPU variants.
	* configure: Regenerate.
	* config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines.
	(macro_build): Handle "K" operand.
	(macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where
	CPU_HAS_DROR and CPU_HAS_ROR are currently used.
	(mips_ip): New variable "lastpos", and implement "+A", "+B",
	and "+C" operands for MIPS32 Release 2 ins/ext instructions.
	Implement "K" operand for MIPS32 Release 2 rdhwr instruction.
	(validate_mips_insn): Implement "+" as a way to extend the
	allowed operands, and implement "K", "+A", "+B", and "+C"
	operands.
	(OPTION_MIPS32R2): New define.
	(md_longopts): Add entry for OPTION_MIPS32R2.
	(OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2.
	(md_parse_option): Handle OPTION_MIPS32R2.
	(s_mipsset): Reimplement handling of ".set mipsN" options
	and add support for ".set mips32r2".
	(mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2).
	(md_show_usage): Document "-mips32r2" option.
	* doc/as.texinfo: Document "-mips32r2" option.
	* doc/c-mips.texi: Likewise.

[ gas/testsuite/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/cp0-names-mips32r2.d: New test.
	* gas/mips/hwr-names-mips32r2.d: New test.
	* gas/mips/hwr-names-numeric.d: New test.
	* gas/mips/hwr-names.s: New test source file.
	* gas/mips/mips32r2.d: New test.
	* gas/mips/mips32r2.s: New test source file.
	* gas/mips/mips32r2-ill.l: New test.
	* gas/mips/mips32r2-ill.s: New test source file.
	* gas/mips/mips.exp: Add mips32r2 architecture data array
	entry.  Run new tests mentioned above.

[ include/elf/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h (E_MIPS_ARCH_32R2): New define.

[ include/opcode/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips.h: Document "+" as the start of two-character operand
	type names, and add new "K", "+A", "+B", and "+C" operand types.
	(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
	(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
	defines.

[ opcodes/ChangeLog ]
2002-12-30  Chris Demetriou  <cgd@broadcom.com>

	* mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric)
	(mips_hwr_names_mips3264r2): New arrays.
	(mips_arch_choice): New "hwr_names" member.
	(mips_arch_choices): Adjust for structure change, and add a new
	entry for "mips32r2" ISA.
	(mips_hwr_names): New variable.
	(set_default_mips_dis_options): Set mips_hwr_names.
	(parse_mips_dis_option): New "hwr-names" option which sets
	mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names.
	(print_insn_arg): Change return type to "int"
	and use that to indicate number of characters consumed.
	Add support for "+" operand extension character, "+A", "+B",
	"+C", and "K" operands.
	(print_insn_mips): Adjust for changes to print_insn_arg.
	(print_mips_disassembler_options): Adjust for "hwr-names"
	addition and "reg-names" change.
	* mips-opc (I33): New define (shorthand for INSN_ISA32R2).
	(mips_builtin_opcodes): Note that "nop" and "ssnop" are special
	forms of "sll".  Add new MIPS32 Release 2 instructions: ehb,
	di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
	rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh.
	Note that hardware rotate instructions (ror, rorv) can be
	used on MIPS32 Release 2, and add the official mnemonics
	for them (rotr, rotrv) and the similar "rotl" mnemonic for
	left-rotate.
2002-12-31 07:29:29 +00:00
Nick Clifton 2469cfa284 Add support for msp430. 2002-12-30 19:25:13 +00:00
Nick Clifton 3badd4651b Added some more pseudo opcodes for system call processing. 2002-12-30 10:50:32 +00:00
Chris Demetriou 640c0ccdc9 [ binutils/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * doc/binutils.texi (objdump): Document MIPS -M options.

[ gas/testsuite/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * gas/mips/cp0-names-mips32.d: New file.
        * gas/mips/cp0-names-mips64.d: New file.
        * gas/mips/cp0-names-numeric.d: New file.
        * gas/mips/cp0-names-sb1.d: New file.
        * gas/mips/cp0-names.s: New file.
        * gas/mips/fpr-names-32.d: New file.
        * gas/mips/fpr-names-64.d: New file.
        * gas/mips/fpr-names-n32.d: New file.
        * gas/mips/fpr-names-numeric.d: New file.
        * gas/mips/fpr-names.s: New file.
        * gas/mips/gpr-names-32.d: New file.
        * gas/mips/gpr-names-64.d: New file.
        * gas/mips/gpr-names-n32.d: New file.
        * gas/mips/gpr-names-numeric.d: New file.
        * gas/mips/gpr-names.s: New file.
        * gas/mips/mips.exp: Run new tests.

[ include/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * dis-asm.h (print_mips_disassembler_options): Prototype.

[ include/opcode/ChangeLog ]
2002-12-19  Chris Demetriou  <cgd@broadcom.com>

        * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
        (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
        (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
        (OP_OP_SDC2, OP_OP_SDC3): Define.

[ opcodes/ChangeLog ]
2002-12-27  Chris Demetriou  <cgd@broadcom.com>

        * disassemble.c (disassembler_usage): Add invocation of
        print_mips_disassembler_options.
        * mips-dis.c (print_mips_disassembler_options)
        (set_default_mips_dis_options, parse_mips_dis_option)
        (parse_mips_dis_options, choose_abi_by_name, choose_arch_by_name)
        (choose_arch_by_number): New functions.
        (mips_abi_choice, mips_arch_choice): New structures.
        (mips32_reg_names, mips64_reg_names, reg_names): Remove.
        (mips_gpr_names_numeric, mips_gpr_names_oldabi)
        (mips_gpr_names_newabi, mips_fpr_names_numeric)
        (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
        (mips_cp0_names_numeric, mips_cp0_names_mips3264)
        (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
        (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
        (mips_cp0_names): New variables.
        (print_insn_args): Use new variables to print GPR, FPR, and CP0
        register names.
        (mips_isa_type): Remove.
        (print_insn_mips): Remove ISA and CPU setup since it is now done...
        (_print_insn_mips): Here.  Remove register setup code, and
        call set_default_mips_dis_options and parse_mips_dis_options
        instead.
        (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
2002-12-27 08:00:31 +00:00
Alan Modra 3f2a9fb79d * hppa.h (completer_chars): #if 0 out. 2002-12-16 09:57:03 +00:00
Alan Modra 9bd1915f75 * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and
"default_args".
	(struct not_wot): Constify "args".
	(struct not): Constify "name".
	(numopcodes): Delete.
	(endop): Delete.
2002-12-16 09:53:48 +00:00
Alan Modra 0e073f4ce8 * pj.h (pj_opc_info_t): Add union.
* pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change.

	* config/tc-pj.c (little, big, parse_exp_save_ilp): Prototype.
	(c_to_r, ipush_code, fake_opcode, alias): Likewise.
	(fake_opcode): Adjust for pj_opc_int_t change.
	(md_begin): Likewise.
	(md_assemble): Likewise.
	(ipush_code): Correct parse_exp_save_ilp call.  Test pending_reloc
	instead of non-existent third arg of parse_exp_save_ilp.
	(md_parse_option): Correct "little" and "big" calls.
2002-12-12 21:52:06 +00:00
Jim Wilson c10d9d8fc3 Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
	* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
	* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
	instruction.
	(emit_one_bundle): Handle "hint" instruction.
	(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
	* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
	* gas/ia64/opc-b.s: Ditto.
	* gas/ia64/opc-f.d: Ditto.
	* gas/ia64/opc-f.s: Ditto.
	* gas/ia64/opc-i.d: Ditto.
	* gas/ia64/opc-i.s: Ditto.
	* gas/ia64/opc-m.d: Ditto.
	* gas/ia64/opc-m.s: Ditto.
	* gas/ia64/opc-x.d: Ditto.
	* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
	* ia64.h: Fix copyright message.
	(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
	* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
	* ia64-opc-b.c: Add "hint.b" instruction.
	* ia64-opc-f.c: Add "hint.f" instruction.
	* ia64-opc-i.c: Add "hint.i" instruction.
	* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
	"cmp8xchg16" instructions.
	* ia64-opc-x.c: Add "hint.x" instruction.
	* ia64-opc.h (AR_CSD): New macro.
	* ia64-ic.tbl: Update according to SDM2.1.
	* ia64-raw.tbl: Ditto.
	* ia64-waw.tbl: Ditto.
	* ia64-gen.c (in_iclass): Handle "hint" like "nop".
	(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
	AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
	* ia64-asmtab.c: Regenerate.
2002-12-05 02:08:02 +00:00
Richard Henderson a823923bf6 include/opcode/
* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.
bfd/
        * cpu-ia64-opc.c (elf64_ia64_operands): Add ldxmov entry.
opcodes/
        * ia64-opc-m.c: Add ld8.mov.
        * ia64-asmtab.c: Regenerate.
gas/
        * config/tc-ia64.c (operand_match): Add IA64_OPND_LDXMOV case.
gas/testsuite/
        * gas/ia64/ldxmov-1.[ds]: New.
        * gas/ia64/ldxmov-2.[ls]: New.
        * gas/ia64/ia64.exp: Run them.
2002-12-03 18:15:48 +00:00
Alan Modra 4fdf0a751a * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union.
Constify "leaf" and "multi".
2002-12-02 21:51:52 +00:00