o bfd_read and bfd_write lose an unnecessary param and become
bfd_bread and bfd_bwrite.
o bfd_*alloc now all take a bfd_size_type arg, and will error if
size_t is too small. eg. 32 bit host, 64 bit bfd, verrry big files
or bugs in linker scripts etc.
o file_ptr becomes a bfd_signed_vma. Besides matching sizes with
various other types involved in handling sections, this should make
it easier for bfd to support a 64 bit off_t on 32 bit hosts that
provide it.
o I've made the H_GET_* and H_PUT_* macros (which invoke bfd_h_{get,put}_*)
generally available. They now cast their args to bfd_vma and
bfd_byte * as appropriate, which removes a swag of casts from the
source.
o Bug fixes to bfd_get8, aix386_core_vec, elf32_h8_relax_section, and
aout-encap.c.
o Zillions of formatting and -Wconversion fixes.
* config.bfd (mips*el*-*-linux-gnu*): Use traditional little
endian MIPS ELF target.
* config.bfd (mips*-*-linux-gnu*): Use traditional big endian
MIPS ELF target.
* configure.in (bfd_elf64_tradbigmips_vec): New. Traditional
64bit big endian MIPS ELF target.
(bfd_elf64_tradlittlemips_vec): New. Traditional 64bit little
endian MIPS ELF target.
* configure: Regenerated.
* elf32-mips.c (IRIX_COMPAT): Handle traditional 64bit and
little endian targets.
(mips_elf_sym_is_global): Handle traditional targets.
* elf64-mips.c (bfd_elf64_tradbigmips_vec): New. Traditional
64bit big endian MIPS ELF target.
(bfd_elf64_tradlittlemips_vec): New. Traditional 64bit little
endian MIPS ELF target.
* targets.c: (_bfd_target_vector): Add bfd_elf64_tradbigmips_vec
and bfd_elf64_tradlittlemips_vec.
underscore on symbols. Make sure to only link same kind.
* elf32-cris.c (cris_elf_object_p,
cris_elf_final_write_processing, cris_elf_print_private_bfd_data,
cris_elf_merge_private_bfd_data): New.
(elf_backend_object_p, elf_backend_final_write_processing,
bfd_elf32_bfd_print_private_bfd_data,
bfd_elf32_bfd_merge_private_bfd_data): Define.
<Target vector definition>: Include elf32-target.h twice with
different macro settings:
(TARGET_LITTLE_SYM): First as bfd_elf32_cris_vec, then as
bfd_elf32_us_cris_vec.
(TARGET_LITTLE_NAME): First as "elf32-cris", then "elf32-us-cris".
(elf_symbol_leading_char): First as 0, then '_'.
(INCLUDED_TARGET_FILE): Define for second include of elf32-target.h.
* config.bfd (cris-*-*): Add bfd_elf32_us_cris_vec to targ_selvecs.
* configure.in (bfd_elf32_cris_vec, cris_aout_vec): New vector.
* configure: Regenerate.
* targets.c: Declare bfd_elf32_us_cris_vec.
* po/bfd.pot: Regenerate.
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
* config.bfd: Change targ_defvec and targ_selvecs for mips*-*-sysv4*
to add a new target for traditional mips i.e
bfd_elf32_tradbigmips_vec and bfd_elf32_tradlittlemips_vec.
* configure.in: Likewise.
* configure: Rebuild.
* targets.c (bfd_elf32_tradbigmips_vec): Declare and put in
bfd_target_vector.
(bfd_elf32_tradlittlemips_vec): Likewise.
* elfxx-target.h: Add macro INCLUDED_TARGET_FILE which is more a test
to see that elfNN_bed does not get redefined even if the target file
is included twice for a chip. See elf32-mips.c.
bfd:
* Makefile.am (coff64-rs6000.lo): New rule.
* Makefile.in: Regenerate.
* coff-rs6000.c (xcoff_mkobject, xcoff_copy_private_bfd_data,
xcoff_is_local_label_name, xcoff_rtype2howto,
xcoff_reloc_type_lookup, xcoff_slurp_armap, xcoff_archive_p,
xcoff_read_ar_hdr, xcoff_openr_next_archived_file, xcoff_write_armap,
xcoff_write_archive_contents): No longer static, and prefix with _bfd_.
(NO_COFF_SYMBOLS): Define.
(xcoff64_swap_sym_in, xcoff64_swap_sym_out, xcoff64_swap_aux_in,
xcoff64_swap_aux_out): New functions; handle xcoff symbol tables
internally.
(MINUS_ONE): New macro.
(xcoff_howto_tabl, xcoff_reloc_type_lookup): Add 64 bit POS
relocation.
(coff_SWAP_sym_in, coff_SWAP_sym_out, coff_SWAP_aux_in,
coff_SWAP_aux_out): Map to the new functions.
* coff64-rs6000.c: New file.
* libcoff.h (bfd_coff_backend_data): Add new fields
_bfd_coff_force_symnames_in_strings and
_bfd_coff_debug_string_prefix_length.
(bfd_coff_force_symnames_in_strings,
bfd_coff_debug_string_prefix_length): New macros for above fields.
* coffcode.h (coff_set_arch_mach_hook): Handle XCOFF64 magic.
Set machine to 620 for XCOFF64. Use bfd_coff_swap_sym_in instead
of using coff_swap_sym_in directly.
(FORCE_SYMNAMES_IN_STRINGS): New macro, defined for XCOFF64.
(coff_set_flags) Set magic for XCOFF64.
(coff_compute_section_file_positions): Add symbol name length to
string section length if bfd_coff_debug_string_prefix_length is
true.
(coff_write_object_contents): Don't do reloc overflow for XCOFF64.
(coff_slurp_line_table): Use bfd_coff_swap_lineno_in instead of
using coff_swap_lineno_in directly.
(bfd_coff_backend_data): Add _bfd_coff_force_symnames_in_strings
and _bfd_coff_debug_string_prefix_length fields.
* coffgen.c (coff_fix_symbol_name, coff_write_symbols): Force
symbol names into strings table when
bfd_coff_force_symnames_in_strings is true.
* coffswap.h (MAX_SCNHDR_NRELOC, MAX_SCNHDR_NLNNO, GET_RELOC_VADDR,
SET_RELOC_VADDR): New macros.
(coff_swap_reloc_in, coff_swap_reloc_out): Use above macros.
(coff_swap_aux_in, coff_swap_aux_out): Remove RS6000COFF_C
code.
(coff_swap_aouthdr_in, coff_swap_aouthdr_out): Handle XCOFF64
changes within RS6000COFF_C specific code.
(coff_swap_scnhdr_out): Use PUT_SCNHDR_NLNNO, PUT_SCNHDR_NRELOC,
MAX_SCNHDR_NRELOC, and MAX_SCNHDR_NLNNO.
* reloc.c (bfd_perform_relocation, bfd_install_relocation):
Extend existing hack on target name.
* xcofflink.c (XCOFF_XVECP): Extend existing hack on
target name.
* coff-tic54x.c (ticof): Keep up to date with new fields
in bfd_coff_backend_data.
* config.bfd: Add bfd_powerpc_64_arch to targ_arch and define
targ_selvecs to include rs6000coff64_vec for rs6000.
* configure.in: Add rs6000coff64_vec case.
* cpu-powerpc.c: New bfd_arch_info_type.
gas:
* as.c (parse_args): Allow md_parse_option to override -a listing
option.
* config/obj-coff.c (add_lineno): Change type of offset parameter
from "int" to "bfd_vma."
* config/tc-ppc.c (md_pseudo_table): Add "llong" and "machine."
(ppc_mach, ppc_subseg_align, ppc_target_format): New.
(ppc_change_csect): Align correctly for XCOFF64.
(ppc_machine): New function, which discards "ppc_machine" line.
(ppc_tc): Cons for 8 when code is 64 bit.
(md_apply_fix3): Don't check operand->insert. Handle 64 bit
relocations.
(md_parse_option): Handle -a64 and -a32.
(ppc_xcoff64): New.
* config/tc-ppc.h (TARGET_MACH): Define.
(TARGET_FORMAT): Move to function.
(SUB_SEGMENT_ALIGN): Use ppc_subseg_align.
include:
* include/coff/rs6k64.h: New file.
opcodes:
* configure.in: Add bfd_powerpc_64_arch.
* disassemble.c (disassembler): Use print_insn_big_powerpc for
64 bit code.
Change LD for ELF so that archive elements whoes archive map contains a
reference to a common symbol will get linkled in.
Add new field to bfd_target structure and initialise it for all bfd targets.
* targets.c (cisco_core_vec): Replaced with two new vecs ...
(cisco_core_big_vec): Add new bigendian vec.
(cisco_core_little_vec): Add new little endian vec.
* cisco-core.c (CRASH_INFO): Fixed offset replaced with ...
(crash_info_locs): Add array of possible offsets.
(MASK_ADDR): Mask to apply to crash info offset.
(crashinfo_external): Add textbase, database, bssbase and
turn into a typedef.
(cisco_core_file_validate): Renamed from cisco_core_file_p.
Many small changes to account for additional hardware versions.
Pick a reasonable size for ".reg" section. Add a ".crash"
section to allow access to crashinfo_external struct.
(cisco_core_file_p): New version of this function that
iterates over crash_info_locs, calling cisco_core_file_validate.
(cisco_core_vec): Old big endian only vec replaced with ...
(cisco_core_big_vec): Add big endian version.
(cisco_core_little_vec): Add little endian version.
* configure.in (cisco_core_vec): Split to two new vectors ...
(cisco_core_big_vec): New target vector.
(cisco_core_little_vec): New target vector.
* configure: Regenerate.
* config.bfd (targ): For m68*-*-aout* targ, change cisco_core_vec
to cisco_core_big_vec in targ_selvecs.
Hans-Peter Nilsson
Nick Clifton
Alan Modra
Joern Rennecke
Jakub Jelinek
H.J. Lu
Timothy Wall
Andreas Jaeger
Kazu Hirata
Jim Wilson
Alexandre Oliva
Jason Eckhardt
Ulf Carlsson
Nicholas Duffek
Clinton Popetz
Jeff Law
Ian Lance Taylor
Richard Henderson