* configure.in: Add bits for i860-stardent-{sysv4, elf}*.
* configure: Regenerated.
* config/obj-elf.c (obj_elf_type): Recognize a fifth type
of operand to the .type directive (.e.g, "type").
* configure.in: Add bits for i860-stardent-{sysv4, elf}*.
* configure: Regenerated.
* config/obj-elf.c (obj_elf_type): Recognize a fifth type
of operand to the .type directive (.e.g, "type").
* i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* configure.in: New bits for bfd_i860_arch.
* configure: Regenerated.
* opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* dis-asm.h (print_insn_i860): Add prototype.
* cpu-i860.c: Added comments.
* elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* configure: Regenerated.
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
* gdb.base/recurse.exp: Run tests for all targets.
* gdb.base/so-impl-ld.exp: Added wildcard to handle the
gnu-oldld case on ARM.
* gdb.base/watchpoint.exp (test_stepping): Clear xfail
for ARM targets.
* sh-tdep.c (sh_gdbarch_init): For sh4 initialize
register_convert_to_raw, register_convert_to_virtual,
register_convertible.
(sh_sh4_register_convertible): New function.
(sh_sh4_register_convert_to_virtual): New function.
(sh_sh4_register_convert_to_raw): New function.
Include floatformat.h.
(GCC_FOR_TARGET): Use it.
(CC_FOR_TARGET, CXX_FOR_TARGET, CHILL_FOR_TARGET): Now defined...
* configure.in: ... here.
(FLAGS_FOR_TARGET): Define. Add ld build dir to -L path.
(libstdcxx_flags): Define and append to CXX_FOR_TARGET.
to allow elf32.em to be used by ports that require
some minor variations or a few extra functions.
Implement for hppaelf and armelf.
Fix header file include order in m68kcoff.em
* elflink.h (elf_merge_symbol): Take one more argument,
dt_needed, to indicate if the symbol comes from a DT_NEEDED
entry. Don't overide the existing weak definition if dt_needed
is true.
(elf_link_add_object_symbols): Pass dt_needed to
elf_merge_symbol ().
* sim-events.c (sim_events_remain_time): New function returning
the time that remains before the event is raised.
* hw-events.c (hw_event_remain_time): Likewise.
* sim-events.h (sim_events_remain_time): Declare.
* hw-events.h (hw_event_remain_time): Declare.
* sim-hw.c: Use <errno.h> instead of <sys/errno.h>
(OPTION_HW_LIST): New option --hw-list to list the devices.
(hw_option_handler): List the device tree with 'sim_hw_print'.
* sim-bits.h (_MSB_16, _LSB_16): Define for 16-bit targets.
(MASK, LSBIT, MSBIT): Likewise and use _MSB_16 and _LSB_16.
(EXTENDED): Define for 16-bit word size.
* sim-bits.c (LSEXTRACTED, MSEXTRACTED, LSINSERTED,
MSINSERTED, LSSEXT, MSSEXT): Implement for 16-bit word size.
* sim-types.h: Added support for 16-bit targets.
* configure.tgt: Recognize the 68hc11.
* m68hc11-tdep.c: New file for 68hc11 target.
* config/m68hc11/m68hc11.mt: New file for 68hc11 port.
* configure.tgt: When 68hc11, set gdb_multi_arch.
__DJGPP__. Use P_WAIT instead of constant in the spawnv* call.
Cast program to 'char *' in errmsg_arg assignment.
(PWAIT_ERROR): Define.
(pwait): Use PWAIT_ERROR. Adjust DJGPP's status code to conform
to DJGPP's WIF* macros.
* sh-tdep.c (sh_sh4_register_name, sh_sh4_register_byte,
sh_sh4_register_raw_size, sh_sh4_register_virtual_type,
sh_fetch_pseudo_register, sh_store_pseudo_register,
sh_do_pseudo_register, sh_gdbarch_init): Fix names for pseudoregs,
they should be numbered as drx fvy where x and y are multiples of
2 and 4 respectively.
* config/sh/tm-sh.h: Fix names of pseudo regs.
