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binutils-gdb/include/elf
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James Bowman 81b42bcab1 FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts. 
Part 2 adds a relaxation pass, which actually implements the code compression scheme.

bfd	* archures.c: Add bfd_mach_ft32b.
	* cpu-ft32.c: Add arch_info_struct.
	* elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1,
	DIFF32. (ft32_elf_relocate_section): Add clauses
	for R_FT32_SC0, SC1, DIFF32.  (ft32_reloc_shortable,
	elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value,
	elf32_ft32_adjust_reloc_if_spans_insn,
	elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target,
	ft32_elf_relax_section): New function.
	* reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

gas	* config/tc-ft32.c (md_assemble): add relaxation reloc
	BFD_RELOC_FT32_RELAX.  (md_longopts): Add "norelax" and
	"no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32.
	(relaxable_section, ft32_validate_fix_sub, ft32_force_relocation,
	ft32_allow_local_subtract): New function.
	* config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION.
	* testsuite/gas/ft32/insnsc.s: New test exercising all FT32B
	shortcodes.

include	* elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
2017-11-01 15:33:24 +00:00
..
aarch64.h
Rename R_AARCH64_TLSDESC_LD64_LO12_NC to R_AARCH64_TLSDESC_LD64_LO12 and R_AARCH64_TLSDESC_ADD_LO12_NC to R_AARCH64_TLSDESC_ADD_LO12.
2017-03-13 09:58:04 +00:00
alpha.h
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2017-01-02 14:08:56 +10:30
arc-cpu.def
[ARC] Add arc-cpu.def with processor definitions
2017-05-30 16:52:28 +03:00
arc-reloc.def
[ARC] Add JLI support.
2017-07-19 09:56:55 +02:00
arc.h
[ARC] Object attributes.
2017-05-10 14:42:22 +02:00
arm.h
[ARM] Add support for ARMv8-R in assembler and readelf
2017-06-24 10:37:47 +01:00
avr.h
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bfin.h
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ChangeLog-0415
binutils ChangeLog rotation
2016-01-01 22:59:17 +10:30
ChangeLog-9103
…
common.h
Handle FreeBSD-specific AT_EHDRFLAGS and AT_HWCAP auxiliary vector types.
2017-10-05 09:50:01 -07:00
cr16.h
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cr16c.h
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cris.h
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crx.h
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d10v.h
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d30v.h
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dlx.h
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dwarf.h
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epiphany.h
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external.h
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fr30.h
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frv.h
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ft32.h
FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts.
2017-11-01 15:33:24 +00:00
h8.h
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2017-01-02 14:08:56 +10:30
hppa.h
Fix spelling typos.
2017-07-18 16:58:14 +01:00
i370.h
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i386.h
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i860.h
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i960.h
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ia64.h
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internal.h
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ip2k.h
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iq2000.h
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lm32.h
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m32c.h
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m32r.h
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m68hc11.h
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m68k.h
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mcore.h
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mep.h
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metag.h
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microblaze.h
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2017-01-02 14:08:56 +10:30
mips.h
MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support
2017-06-28 02:07:36 +01:00
mmix.h
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mn10200.h
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mn10300.h
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moxie.h
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msp430.h
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mt.h
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nds32.h
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nios2.h
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or1k.h
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pj.h
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ppc64.h
PPC64_OPT_LOCALENTRY
2017-06-01 22:47:32 +09:30
ppc.h
Missing relocation R_PPC_VLE_ADDR20 and add VLE flag to details in readelf
2017-09-05 08:42:27 +09:30
pru.h
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reloc-macros.h
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riscv.h
RISC-V: Use pc-relative relocation for FDE initial location
2017-06-26 18:26:40 -07:00
rl78.h
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rx.h
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s390.h
S/390: Add support for pgste marker
2017-06-23 08:00:46 +02:00
score.h
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sh.h
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sparc.h
binutils: support for the SPARC M8 processor
2017-05-19 09:27:08 -07:00
spu.h
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2017-01-02 14:08:56 +10:30
tic6x-attrs.h
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tic6x.h
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tilegx.h
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tilepro.h
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v850.h
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vax.h
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visium.h
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vxworks.h
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2017-01-02 14:08:56 +10:30
wasm32.h
Add support for the WebAssembly file format and the wasm32 ELF conversion to gas and the binutils.
2017-03-30 10:57:21 +01:00
x86-64.h
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xc16x.h
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xgate.h
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xstormy16.h
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xtensa.h
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