c4x.md, [...]: Follow spelling conventions.
* config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c, config/fr30/fr30.md, config/i386/i386.h, config/iq2000/iq2000.h, config/iq2000/predicates.md, config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h, config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h, config/pdp11/pdp11.c, config/pdp11/pdp11.h, config/rs6000/altivec.md, config/rs6000/rs6000.c, config/s390/s390-modes.def, config/sparc/netbsd-elf.h, config/sparc/sparc.c, config/sparc/sparc.h, config/sparc/sparc.md, config/spu/constraints.md, config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling conventions. From-SVN: r122151
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
a50aa82741
commit
a7b376eeb6
@ -6,6 +6,19 @@
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config/arc/arc.h, config/arm/arm.c, config/arm/arm.md,
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config/arm/lib1funcs.asm: Follow spelling conventions.
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* config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c,
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config/fr30/fr30.md, config/i386/i386.h,
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config/iq2000/iq2000.h, config/iq2000/predicates.md,
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config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h,
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config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h,
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config/pdp11/pdp11.c, config/pdp11/pdp11.h,
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config/rs6000/altivec.md, config/rs6000/rs6000.c,
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config/s390/s390-modes.def, config/sparc/netbsd-elf.h,
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config/sparc/sparc.c, config/sparc/sparc.h,
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config/sparc/sparc.md, config/spu/constraints.md,
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config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling
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conventions.
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2007-02-20 Alan Modra <amodra@bigpond.net.au>
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PR target/29943
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@ -29,7 +29,7 @@
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; for QImode and Pmode, whether Pmode was QImode or PQImode.
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; For addresses we wouldn't have to have a clobber of the CC
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; associated with each insn and we could use MPYI in address
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; calculations without having to synthesize a proper 32 bit multiply.
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; calculations without having to synthesize a proper 32-bit multiply.
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; Additional C30/C40 instructions not coded:
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; CALLcond, IACK, IDLE, LDE, LDFI, LDII, LDM, NORM, RETIcond
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@ -123,7 +123,7 @@
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; L unsigned 16-bit
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; M unsigned 8-bit (C4x only)
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; N ones complement of unsigned 16-bit
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; O 16 bit high constant
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; O 16-bit high constant
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; Q ARx + 9-bit signed disp
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; R ARx + 5-bit unsigned disp (C4x only)
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; S ARx + 0, 1, IRx disp
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@ -1632,7 +1632,7 @@ cris_rtx_costs (rtx x, int code, int outer_code, int *total)
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/* Eight or 16 bits are a word and cycle more expensive. */
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else if (val <= 32767 && val >= -32768)
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*total = 2;
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/* A 32 bit constant (or very seldom, unsigned 16 bits) costs
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/* A 32-bit constant (or very seldom, unsigned 16 bits) costs
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another word. FIXME: This isn't linear to 16 bits. */
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else
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*total = 4;
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@ -546,12 +546,12 @@ crx_function_arg_regno_p (int n)
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* The following addressing modes are supported on CRX:
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*
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* Relocations --> const | symbol_ref | label_ref
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* Absolute address --> 32 bit absolute
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* Post increment --> reg + 12 bit disp.
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* Post modify --> reg + 12 bit disp.
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* Register relative --> reg | 32 bit disp. + reg | 4 bit + reg
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* Scaled index --> reg + reg | 22 bit disp. + reg + reg |
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* 22 disp. + reg + reg + (2 | 4 | 8) */
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* Absolute address --> 32-bit absolute
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* Post increment --> reg + 12-bit disp.
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* Post modify --> reg + 12-bit disp.
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* Register relative --> reg | 32-bit disp. + reg | 4 bit + reg
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* Scaled index --> reg + reg | 22-bit disp. + reg + reg |
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* 22-disp. + reg + reg + (2 | 4 | 8) */
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static int crx_addr_reg_p (rtx addr_reg)
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{
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@ -746,7 +746,7 @@
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;;}}}
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;;{{{ Multiplication
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;; Signed multiplication producing 64 bit results from 32 bit inputs
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;; Signed multiplication producing 64-bit results from 32-bit inputs
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(define_insn "mulsidi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
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@ -757,7 +757,7 @@
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[(set_attr "length" "6")]
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)
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;; Unsigned multiplication producing 64 bit results from 32 bit inputs
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;; Unsigned multiplication producing 64-bit results from 32-bit inputs
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(define_insn "umulsidi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
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@ -768,7 +768,7 @@
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[(set_attr "length" "6")]
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)
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;; Signed multiplication producing 32 bit result from 16 bit inputs
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;; Signed multiplication producing 32-bit result from 16-bit inputs
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(define_insn "mulhisi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
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@ -779,7 +779,7 @@
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[(set_attr "length" "4")]
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)
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;; Unsigned multiplication producing 32 bit result from 16 bit inputs
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;; Unsigned multiplication producing 32-bit result from 16-bit inputs
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(define_insn "umulhisi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r"))
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@ -790,7 +790,7 @@
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[(set_attr "length" "4")]
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)
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;; Signed multiplication producing 32 bit result from 32 bit inputs
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;; Signed multiplication producing 32-bit result from 32-bit inputs
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mult:SI (match_operand:SI 1 "register_operand" "%r")
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@ -884,7 +884,7 @@
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;;}}}
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;;{{{ Logical Operations
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;; Logical AND, 32 bit integers
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;; Logical AND, 32-bit integers
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(and:SI (match_operand:SI 1 "register_operand" "%r")
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@ -894,7 +894,7 @@
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"and %1, %0"
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)
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;; Inclusive OR, 32 bit integers
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;; Inclusive OR, 32-bit integers
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(define_insn "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(ior:SI (match_operand:SI 1 "register_operand" "%r")
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@ -904,7 +904,7 @@
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"or %1, %0"
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)
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;; Exclusive OR, 32 bit integers
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;; Exclusive OR, 32-bit integers
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(xor:SI (match_operand:SI 1 "register_operand" "%r")
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@ -914,7 +914,7 @@
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"eor %1, %0"
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)
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;; One's complement, 32 bit integers
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;; One's complement, 32-bit integers
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(define_expand "one_cmplsi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(not:SI (match_operand:SI 1 "register_operand" "")))]
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@ -1152,7 +1152,7 @@
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;; far away the destination is.
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;; The calculation for the instruction length is derived as follows:
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;; The branch instruction has a 9 bit signed displacement so we have
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;; The branch instruction has a 9-bit signed displacement so we have
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;; this inequality for the displacement:
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;;
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;; -256 <= pc < 256
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@ -1955,7 +1955,7 @@ do { \
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/* How to refer to registers in assembler output.
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This sequence is indexed by compiler's hard-register-number (see above). */
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/* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
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/* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
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For non floating point regs, the following are the HImode names.
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For float regs, the stack top is sometimes referred to as "%st(0)"
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@ -252,12 +252,12 @@ enum reg_class
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/* For IQ2000:
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`I' is used for the range of constants an arithmetic insn can
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actually contain (16 bits signed integers).
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actually contain (16-bits signed integers).
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`J' is used for the range which is just zero (i.e., $r0).
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`K' is used for the range of constants a logical insn can actually
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contain (16 bit zero-extended integers).
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contain (16-bit zero-extended integers).
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`L' is used for the range of constants that be loaded with lui
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(i.e., the bottom 16 bits are zero).
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@ -267,7 +267,7 @@ enum reg_class
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`N' is used for constants 0xffffnnnn or 0xnnnnffff
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`O' is a 5 bit zero-extended integer. */
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`O' is a 5-bit zero-extended integer. */
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
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@ -18,7 +18,7 @@
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA.
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;; Return 1 if OP can be used as an operand where a register or 16 bit
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;; Return 1 if OP can be used as an operand where a register or 16-bit
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;; unsigned integer is needed.
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(define_predicate "uns_arith_operand"
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@ -30,7 +30,7 @@
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return register_operand (op, mode);
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})
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;; Return 1 if OP can be used as an operand where a 16 bit integer is
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;; Return 1 if OP can be used as an operand where a 16-bit integer is
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;; needed.
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(define_predicate "arith_operand"
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@ -50,7 +50,7 @@
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return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
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})
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;; Return 1 if OP is a 32 bit integer which is too big to be loaded
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;; Return 1 if OP is a 32-bit integer which is too big to be loaded
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;; with one instruction.
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(define_predicate "large_int"
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@ -411,7 +411,7 @@ LSYM(small_divisor)
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#if defined(pa64)
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/* Clear the upper 32 bits of the arg1 register. We are working with */
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/* small divisors (and 32 bit integers) We must not be mislead */
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/* small divisors (and 32-bit integers) We must not be mislead */
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/* by "1" bits left in the upper 32 bits. */
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depd %r0,31,32,%r25
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#endif
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@ -626,7 +626,7 @@ LSYM(special_divisor)
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#if defined(pa64)
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/* Clear the upper 32 bits of the arg1 register. We are working with
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small divisors (and 32 bit unsigned integers) We must not be mislead
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small divisors (and 32-bit unsigned integers) We must not be mislead
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by "1" bits left in the upper 32 bits. */
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depd %r0,31,32,%r25
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#endif
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@ -576,7 +576,7 @@ adddi3_operand (rtx op, enum machine_mode mode)
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}
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/* True iff zdepi can be used to generate this CONST_INT.
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zdepi first sign extends a 5 bit signed number to a given field
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zdepi first sign extends a 5-bit signed number to a given field
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length, then places this field anywhere in a zero. */
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int
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zdepi_cint_p (unsigned HOST_WIDE_INT x)
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@ -487,10 +487,10 @@ extern struct rtx_def *hppa_pic_save_rtx (void);
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C is the letter, and VALUE is a constant value.
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Return 1 if VALUE is in the range specified by C.
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`I' is used for the 11 bit constants.
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`J' is used for the 14 bit constants.
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`I' is used for the 11-bit constants.
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`J' is used for the 14-bit constants.
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`K' is used for values that can be moved with a zdepi insn.
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`L' is used for the 5 bit constants.
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`L' is used for the 5-bit constants.
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`M' is used for 0.
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`N' is used for values with the least significant 11 bits equal to zero
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and when sign extended from 32 to 64 bits the
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@ -1321,7 +1321,7 @@ extern int may_call_alloca;
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function's constant-pool, because such addresses can actually be
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output as REG+SMALLINT.
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Note we only allow 5 bit immediates for access to a constant address;
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Note we only allow 5-bit immediates for access to a constant address;
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doing so avoids losing for loading/storing a FP register at an address
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which will not fit in 5 bits. */
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@ -4638,7 +4638,7 @@
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"!TARGET_64BIT"
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"*
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{
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/* Don't output a 64 bit constant, since we can't trust the assembler to
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/* Don't output a 64-bit constant, since we can't trust the assembler to
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handle it correctly. */
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if (GET_CODE (operands[2]) == CONST_DOUBLE)
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operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
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@ -15,7 +15,7 @@
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HP-PA 1.1 has 32 fullword registers and 32 floating point
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registers. However, the floating point registers behave
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differently: the left and right halves of registers are addressable
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as 32 bit registers. So, we will set things up like the 68k which
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as 32-bit registers. So, we will set things up like the 68k which
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has different fp units: define separate register sets for the 1.0
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and 1.1 fp units. */
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@ -31,7 +31,7 @@ Boston, MA 02110-1301, USA. */
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HP-PA 2.0w has 32 fullword registers and 32 floating point
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registers. However, the floating point registers behave
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differently: the left and right halves of registers are addressable
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as 32 bit registers.
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as 32-bit registers.
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Due to limitations within GCC itself, we do not expose the left/right
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half addressability when in wide mode. This is not a major performance
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@ -584,7 +584,7 @@ output_move_double (rtx *operands)
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operands[1] = GEN_INT (INTVAL(operands[1]) & 0xff);
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}
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else
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/* immediate 32 bit values not allowed */
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/* immediate 32-bit values not allowed */
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gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE);
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}
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else
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@ -97,7 +97,7 @@ Boston, MA 02110-1301, USA. */
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#define UNITS_PER_WORD 2
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/* This machine doesn't use IEEE floats. */
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/* Because the pdp11 (at least Unix) convention for 32 bit ints is
|
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/* Because the pdp11 (at least Unix) convention for 32-bit ints is
|
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big endian, opposite for what you need for float, the vax float
|
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conversion routines aren't actually used directly. But the underlying
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format is indeed the vax/pdp11 float format. */
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@ -286,10 +286,10 @@ extern const struct real_format pdp11_d_format;
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/* The pdp has a couple of classes:
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MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication
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(even numbered do 32 bit multiply)
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MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication
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(even numbered do 32-bit multiply)
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LMUL_REGS long multiply registers (even numbered regs )
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(don't need them, all 32 bit regs are even numbered!)
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(don't need them, all 32-bit regs are even numbered!)
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GENERAL_REGS is all cpu
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LOAD_FPU_REGS is the first four cpu regs, they are easier to load
|
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NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
|
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@ -587,7 +587,7 @@
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DONE;
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}")
|
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;; 32 bit integer multiplication
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;; 32-bit integer multiplication
|
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;; A_high = Operand_0 & 0xFFFF0000 >> 16
|
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;; A_low = Operand_0 & 0xFFFF
|
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;; B_high = Operand_1 & 0xFFFF0000 >> 16
|
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@ -3530,7 +3530,7 @@ rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
|
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}
|
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else
|
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{
|
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/* IE, or 64 bit offset LE. */
|
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/* IE, or 64-bit offset LE. */
|
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tmp2 = gen_reg_rtx (Pmode);
|
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if (TARGET_64BIT)
|
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insn = gen_tls_got_tprel_64 (tmp2, got, addr);
|
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@ -9271,22 +9271,22 @@ rs6000_common_init_builtins (void)
|
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&& mode3 == V4SImode)
|
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type = v4sf_ftype_v4sf_v4sf_v4si;
|
||||
|
||||
/* vchar, vchar, vchar, 4 bit literal. */
|
||||
/* vchar, vchar, vchar, 4-bit literal. */
|
||||
else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
|
||||
&& mode3 == QImode)
|
||||
type = v16qi_ftype_v16qi_v16qi_int;
|
||||
|
||||
/* vshort, vshort, vshort, 4 bit literal. */
|
||||
/* vshort, vshort, vshort, 4-bit literal. */
|
||||
else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
|
||||
&& mode3 == QImode)
|
||||
type = v8hi_ftype_v8hi_v8hi_int;
|
||||
|
||||
/* vint, vint, vint, 4 bit literal. */
|
||||
/* vint, vint, vint, 4-bit literal. */
|
||||
else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
|
||||
&& mode3 == QImode)
|
||||
type = v4si_ftype_v4si_v4si_int;
|
||||
|
||||
/* vfloat, vfloat, vfloat, 4 bit literal. */
|
||||
/* vfloat, vfloat, vfloat, 4-bit literal. */
|
||||
else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
|
||||
&& mode3 == QImode)
|
||||
type = v4sf_ftype_v4sf_v4sf_int;
|
||||
@ -9390,23 +9390,23 @@ rs6000_common_init_builtins (void)
|
||||
else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
|
||||
type = v4si_ftype_v8hi_v4si;
|
||||
|
||||
/* vint, vint, 5 bit literal. */
|
||||
/* vint, vint, 5-bit literal. */
|
||||
else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
|
||||
type = v4si_ftype_v4si_int;
|
||||
|
||||
/* vshort, vshort, 5 bit literal. */
|
||||
/* vshort, vshort, 5-bit literal. */
|
||||
else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
|
||||
type = v8hi_ftype_v8hi_int;
|
||||
|
||||
/* vchar, vchar, 5 bit literal. */
|
||||
/* vchar, vchar, 5-bit literal. */
|
||||
else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
|
||||
type = v16qi_ftype_v16qi_int;
|
||||
|
||||
/* vfloat, vint, 5 bit literal. */
|
||||
/* vfloat, vint, 5-bit literal. */
|
||||
else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
|
||||
type = v4sf_ftype_v4si_int;
|
||||
|
||||
/* vint, vfloat, 5 bit literal. */
|
||||
/* vint, vfloat, 5-bit literal. */
|
||||
else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
|
||||
type = v4si_ftype_v4sf_int;
|
||||
|
||||
|
||||
@ -119,7 +119,7 @@ information necessary for CCT1 and CCT2 modes.):
|
||||
|
||||
CCSR, CCUR
|
||||
|
||||
There are several instructions comparing 32 bit with 64 bit unsigned/signed
|
||||
There are several instructions comparing 32 bit with 64-bit unsigned/signed
|
||||
values. Such instructions can be considered to have a builtin zero/sign_extend.
|
||||
The problem is that in the RTL (to be canonical) the zero/sign extended operand
|
||||
has to be the first one but the machine instructions like it the other way
|
||||
|
||||
@ -85,7 +85,7 @@ Boston, MA 02110-1301, USA. */
|
||||
#define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME);
|
||||
|
||||
/* Below here exists the merged NetBSD/sparc & NetBSD/sparc64 compiler
|
||||
description, allowing one to build 32 bit or 64 bit applications
|
||||
description, allowing one to build 32-bit or 64-bit applications
|
||||
on either. We define the sparc & sparc64 versions of things,
|
||||
occasionally a neutral version (should be the same as "netbsd-elf.h")
|
||||
and then based on SPARC_BI_ARCH, DEFAULT_ARCH32_P, and TARGET_CPU_DEFAULT,
|
||||
|
||||
@ -3493,7 +3493,7 @@ mem_min_alignment (rtx mem, int desired)
|
||||
hard register number, and one indexed by mode. */
|
||||
|
||||
/* The purpose of sparc_mode_class is to shrink the range of modes so that
|
||||
they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
|
||||
they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
|
||||
mapped into one sparc_mode_class mode. */
|
||||
|
||||
enum sparc_mode_class {
|
||||
|
||||
@ -500,7 +500,7 @@ extern enum cmodel sparc_cmodel;
|
||||
/* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
|
||||
TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
|
||||
to get high 32 bits. False in V8+ or V9 because multiply stores
|
||||
a 64 bit result in a register. */
|
||||
a 64-bit result in a register. */
|
||||
|
||||
#define TARGET_HARD_MUL32 \
|
||||
((TARGET_V8 || TARGET_SPARCLITE \
|
||||
@ -708,7 +708,7 @@ if (TARGET_ARCH64 \
|
||||
even those that are not normally considered general registers.
|
||||
|
||||
SPARC has 32 integer registers and 32 floating point registers.
|
||||
64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
|
||||
64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
|
||||
accessible. We still account for them to simplify register computations
|
||||
(e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
|
||||
32+32+32+4 == 100.
|
||||
|
||||
@ -1237,7 +1237,7 @@
|
||||
"TARGET_V9
|
||||
&& REGNO (operands[1]) == SPARC_ICC_REG
|
||||
&& (GET_MODE (operands[1]) == CCXmode
|
||||
/* 32 bit LTU/GEU are better implemented using addx/subx. */
|
||||
/* 32-bit LTU/GEU are better implemented using addx/subx. */
|
||||
|| (GET_CODE (operands[2]) != LTU && GET_CODE (operands[2]) != GEU))"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(set (match_dup 0)
|
||||
@ -4592,7 +4592,7 @@
|
||||
|
||||
;; Integer multiply/divide instructions.
|
||||
|
||||
;; The 32 bit multiply/divide instructions are deprecated on v9, but at
|
||||
;; The 32-bit multiply/divide instructions are deprecated on v9, but at
|
||||
;; least in UltraSPARC I, II and IIi it is a win tick-wise.
|
||||
|
||||
(define_insn "mulsi3"
|
||||
@ -4699,8 +4699,8 @@
|
||||
}
|
||||
})
|
||||
|
||||
;; V9 puts the 64 bit product in a 64 bit register. Only out or global
|
||||
;; registers can hold 64 bit values in the V8plus environment.
|
||||
;; V9 puts the 64-bit product in a 64-bit register. Only out or global
|
||||
;; registers can hold 64-bit values in the V8plus environment.
|
||||
;; XXX
|
||||
(define_insn "mulsidi3_v8plus"
|
||||
[(set (match_operand:DI 0 "register_operand" "=h,r")
|
||||
|
||||
@ -25,23 +25,23 @@
|
||||
;; another treats it as 64 bit, and the third sign extends it to 128 bit.
|
||||
|
||||
(define_constraint "A"
|
||||
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value."
|
||||
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32-bit value."
|
||||
(ior (and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "immediate_load_p (op, SImode)"))
|
||||
(match_code "symbol_ref,label_ref,high,const")))
|
||||
|
||||
(define_constraint "B"
|
||||
"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32 bit value."
|
||||
"An immediate for arithmetic instructions (e.g., ai, ceqi). const_int is treated as a 32-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "arith_immediate_p (op, SImode, -0x200, 0x1ff)")))
|
||||
|
||||
(define_constraint "C"
|
||||
"An immediate for and/xor/or instructions. const_int is treated as a 32 bit value."
|
||||
"An immediate for and/xor/or instructions. const_int is treated as a 32-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "logical_immediate_p (op, SImode)")))
|
||||
|
||||
(define_constraint "D"
|
||||
"An immediate for iohl instruction. const_int is treated as a 32 bit value."
|
||||
"An immediate for iohl instruction. const_int is treated as a 32-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "iohl_immediate_p (op, SImode)")))
|
||||
|
||||
@ -51,7 +51,7 @@
|
||||
(match_test "immediate_load_p (op, TImode)")))
|
||||
|
||||
(define_constraint "W"
|
||||
"An immediate for shift and rotate instructions. const_int is treated as a 32 bit value."
|
||||
"An immediate for shift and rotate instructions. const_int is treated as a 32-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "arith_immediate_p (op, SImode, -0x40, 0x3f)")))
|
||||
|
||||
@ -66,17 +66,17 @@
|
||||
(match_test "iohl_immediate_p (op, TImode)")))
|
||||
|
||||
(define_constraint "a"
|
||||
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value."
|
||||
"An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64-bit value."
|
||||
(and (match_code "const_int")
|
||||
(match_test "immediate_load_p (op, DImode)")))
|
||||
|
||||
(define_constraint "c"
|
||||
"An immediate for and/xor/or instructions. const_int is treated as a 64 bit value."
|
||||
"An immediate for and/xor/or instructions. const_int is treated as a 64-bit value."
|
||||
(and (match_code "const_int")
|
||||
(match_test "logical_immediate_p (op, DImode)")))
|
||||
|
||||
(define_constraint "d"
|
||||
"An immediate for iohl instruction. const_int is treated as a 64 bit value."
|
||||
"An immediate for iohl instruction. const_int is treated as a 64-bit value."
|
||||
(and (match_code "const_int")
|
||||
(match_test "iohl_immediate_p (op, DImode)")))
|
||||
|
||||
@ -86,12 +86,12 @@
|
||||
(match_test "fsmbi_const_p (op)")))
|
||||
|
||||
(define_constraint "j"
|
||||
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32 bit value."
|
||||
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 32-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "cpat_const_p (op, SImode)")))
|
||||
|
||||
(define_constraint "k"
|
||||
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64 bit value."
|
||||
"An immediate which can be loaded with one of the cbd/chd/cwd/cdd instructions. const_int is treated as a 64-bit value."
|
||||
(and (match_code "const_int,const_double,const_vector")
|
||||
(match_test "cpat_const_p (op, DImode)")))
|
||||
|
||||
@ -119,7 +119,7 @@
|
||||
(match_test "ival >= -0x200 && ival <= 0x1ff")))
|
||||
|
||||
(define_constraint "M"
|
||||
"A signed 16 bit immediate for @code{stop}."
|
||||
"A signed 16-bit immediate for @code{stop}."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= -0x8000ll && ival <= 0x7fffll")))
|
||||
|
||||
|
||||
@ -1969,7 +1969,7 @@ insert_branch_hints (void)
|
||||
because they are only at the end of a block and are
|
||||
considered when we are deciding whether to propagate
|
||||
- we're getting too far away from the branch. The hbr insns
|
||||
only have a signed 10 bit offset
|
||||
only have a signed 10-bit offset
|
||||
We go back as far as possible so the branch will be considered
|
||||
for propagation when we get to the beginning of the block. */
|
||||
next = 0;
|
||||
@ -2280,7 +2280,7 @@ legitimate_const (rtx x, int aligned)
|
||||
{
|
||||
/* We can never know if the resulting address fits in 18 bits and can be
|
||||
loaded with ila. Instead we should use the HI and LO relocations to
|
||||
load a 32 bit address. */
|
||||
load a 32-bit address. */
|
||||
rtx sym, cst;
|
||||
|
||||
gcc_assert (GET_CODE (x) == CONST);
|
||||
@ -2588,11 +2588,11 @@ arith_immediate_p (rtx op, enum machine_mode mode,
|
||||
}
|
||||
|
||||
/* We accept:
|
||||
- any 32 bit constant (SImode, SFmode)
|
||||
- any 32-bit constant (SImode, SFmode)
|
||||
- any constant that can be generated with fsmbi (any mode)
|
||||
- a 64 bit constant where the high and low bits are identical
|
||||
- a 64-bit constant where the high and low bits are identical
|
||||
(DImode, DFmode)
|
||||
- a 128 bit constant where the four 32 bit words match. */
|
||||
- a 128-bit constant where the four 32-bit words match. */
|
||||
int
|
||||
spu_legitimate_constant_p (rtx x)
|
||||
{
|
||||
|
||||
@ -300,7 +300,7 @@
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 16 bit Integer arithmetic
|
||||
;; :: 16-bit Integer arithmetic
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
@ -449,7 +449,7 @@
|
||||
"mul"
|
||||
[(set_attr "psw_operand" "nop")])
|
||||
|
||||
;; Unsigned multiplication producing 64 bit results from 32 bit inputs
|
||||
;; Unsigned multiplication producing 64-bit results from 32-bit inputs
|
||||
; The constraint on operand 0 is 't' because it is actually two regs
|
||||
; long, and both regs must match the constraint.
|
||||
(define_insn "umulhisi3"
|
||||
@ -522,7 +522,7 @@
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 16 bit Integer Shifts and Rotates
|
||||
;; :: 16-bit Integer Shifts and Rotates
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
@ -556,11 +556,11 @@
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 16 Bit Integer Logical operations
|
||||
;; :: 16-Bit Integer Logical operations
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
;; Logical AND, 16 bit integers
|
||||
;; Logical AND, 16-bit integers
|
||||
(define_insn "andhi3"
|
||||
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
||||
(and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
||||
@ -590,7 +590,7 @@
|
||||
}
|
||||
")
|
||||
|
||||
;; Inclusive OR, 16 bit integers
|
||||
;; Inclusive OR, 16-bit integers
|
||||
(define_insn "iorhi3"
|
||||
[(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
|
||||
(ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
|
||||
@ -620,7 +620,7 @@
|
||||
}
|
||||
")
|
||||
|
||||
;; Exclusive OR, 16 bit integers
|
||||
;; Exclusive OR, 16-bit integers
|
||||
(define_insn "xorhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=T,r,r")
|
||||
(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
|
||||
@ -632,7 +632,7 @@
|
||||
xor %0,%2"
|
||||
[(set_attr "length" "2,2,4")])
|
||||
|
||||
;; One's complement, 16 bit integers
|
||||
;; One's complement, 16-bit integers
|
||||
(define_insn "one_cmplhi2"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r")
|
||||
(not:HI (match_operand:HI 1 "register_operand" "0")))]
|
||||
@ -642,7 +642,7 @@
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 32 bit Integer arithmetic
|
||||
;; :: 32-bit Integer arithmetic
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
@ -695,7 +695,7 @@
|
||||
|
||||
;; ::::::::::::::::::::
|
||||
;; ::
|
||||
;; :: 32 bit Integer Shifts and Rotates
|
||||
;; :: 32-bit Integer Shifts and Rotates
|
||||
;; ::
|
||||
;; ::::::::::::::::::::
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user