When warn_if_not_aligned_p is true, a warning will be issued on function
declaration later. There is no need to warn function alignment when
warn_if_not_aligned_p is true.
* c-attribs.c (common_handle_aligned_attribute): Don't warn
function alignment if warn_if_not_aligned_p is true.
From-SVN: r252036
This patch adds -static-pie to GCC driver to create static PIE. A static
position independent executable (PIE) is similar to static executable,
but can be loaded at any address without a dynamic linker. All linker
input files must be compiled with -fpie or -fPIE and linker must support
--no-dynamic-linker to avoid linking with dynamic linker. "-z text" is
also needed to prevent dynamic relocations in read-only segments.
PR driver/81498
* common.opt (-static-pie): New alias.
(shared): Negate static-pie.
(-no-pie): Update help text.
(-pie): Likewise.
(static-pie): New option.
* config/gnu-user.h (GNU_USER_TARGET_STARTFILE_SPEC): Add
-static-pie support.
(GNU_USER_TARGET_ENDFILE_SPEC): Likewise.
(LINK_EH_SPEC): Likewise.
(LINK_GCC_C_SEQUENCE_SPEC): Likewise.
* config/i386/gnu-user.h (GNU_USER_TARGET_LINK_SPEC): Likewise.
* config/i386/gnu-user64.h (GNU_USER_TARGET_LINK_SPEC): Likewise.
* gcc.c (LINK_COMMAND_SPEC): Likewise.
(init_gcc_specs): Likewise.
(init_spec): Likewise.
(display_help): Update help message for -pie.
* doc/invoke.texi: Update -pie, -no-pie and -static. Document
-static-pie.
From-SVN: r252034
Remove the remaining uses of '*' from the movsi/di/ti patterns.
Using '*' in alternatives is typically incorrect at it tells the register
allocator to ignore those alternatives. So remove these from all the
integer move patterns. This removes unnecessary int to float moves, for
example gcc.target/aarch64/pr62178.c no longer generates a redundant fmov
since the w = m variant is now allowed.
gcc/
* config/aarch64/aarch64.md (movsi_aarch64): Remove all '*'.
(movdi_aarch64): Likewise.
(movti_aarch64): Likewise.
From-SVN: r252033
PR target/80204
* config/darwin-driver.c (darwin_find_version_from_kernel): Eliminate
calculation of the minor version, always output as 0.
From-SVN: r252029
PR target/82112
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin): For
ALTIVEC_BUILTIN_VEC_LD if arg1 has array type call default_conversion
on it early, rather than manual conversion late. For
ALTIVEC_BUILTIN_VEC_ST if arg2 has array type call default_conversion
instead of performing manual conversion.
* gcc.target/powerpc/pr82112.c: New test.
* g++.dg/ext/altivec-18.C: New test.
From-SVN: r252028
There seems to be a partial misconception in the AArch64 backend that
load1/load2 referred to the number of registers to load, rather than the
number of words to load. This patch fixes that using the new "number of
byte" types added in the previous patch.
That means using the load_16 and store_16 types that were defined in the
previous patch for the first time in the AArch64 backend. To ensure
continuity for scheduling models, I've just split this out from load_8.
Please update your models if this is very wrong!
---
gcc/
* config/aarch64/aarch64.md (movdi_aarch64): Set load/store
types correctly.
(movti_aarch64): Likewise.
(movdf_aarch64): Likewise.
(movtf_aarch64): Likewise.
(load_pairdi): Likewise.
(store_pairdi): Likewise.
(load_pairdf): Likewise.
(store_pairdf): Likewise.
(loadwb_pair<GPI:mode>_<P:mode>): Likewise.
(storewb_pair<GPI:mode>_<P:mode>): Likewise.
(ldr_got_small_<mode>): Likewise.
(ldr_got_small_28k_<mode>): Likewise.
(ldr_got_tiny): Likewise.
* config/aarch64/iterators.md (ldst_sz): New.
(ldpstp_sz): Likewise.
* config/aarch64/thunderx.md (thunderx_storepair): Split store_8
to store_16.
(thunderx_load): Split load_8 to load_16.
* config/aarch64/thunderx2t99.md (thunderx2t99_loadpair): Split
load_8 to load_16.
(thunderx2t99_storepair_basic): Split store_8 to store_16.
* config/arm/xgene1.md (xgene1_load_pair): Split load_8 to load_16.
(xgene1_store_pair): Split store_8 to store_16.
* config/aarch64/falkor.md (falkor_ld_3_ld): Split load_8 to load_16.
(falkor_st_0_st_sd): Split store_8 to store_16.
From-SVN: r252026
In the AArch64 backend and scheduling models there is some confusion as to
what the load1/load2 etc. scheduling types refer to. This leads to us using
load1/load2 in two contexts - for a variety of 32-bit, 64-bit and 128-bit
loads in AArch32 and 128-bit loads in AArch64. That leads to an undesirable
confusion in scheduling.
Fixing it is easy, but mechanical and boring. Essentially,
s/load1/load_4/
s/load2/load_8/
s/load3/load_12/
s/load4/load_16/
s/store1/store_4/
s/store2/store_8/
s/store3/store_12/
s/store4/store_16/
Across all sorts of pipeline models, and the two backends.
I have intentionally not modified any of the patterns which now look obviously
incorrect. I'll be doing a second pass over the AArch64 back-end in patch
2/2 which will fix these bugs.
---
gcc/
* config/arm/types.md (type): Rename load1/2/3/4 to load_4/8/12/16
and store1/2/3/4 to store_4/8/12/16.
* config/aarch64/aarch64.md: Update for rename.
* config/arm/arm.md: Likewise.: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/thumb2.md: Likewise.
* config/arm/vfp.md: Likewise.
* config/arm/arm-generic.md: Likewise.
* config/arm/arm1020e.md: Likewise.
* config/arm/arm1026ejs.md: Likewise.
* config/arm/arm1136jfs.md: Likewise.
* config/arm/arm926ejs.md: Likewise.
* config/arm/cortex-a15.md: Likewise.
* config/arm/cortex-a17.md: Likewise.
* config/arm/cortex-a5.md: Likewise.
* config/arm/cortex-a53.md: Likewise.
* config/arm/cortex-a57.md: Likewise.
* config/arm/cortex-a7.md: Likewise.
* config/arm/cortex-a8.md: Likewise.
* config/arm/cortex-a9.md: Likewise.
* config/arm/cortex-m4.md: Likewise.
* config/arm/cortex-m7.md: Likewise.
* config/arm/cortex-r4.md: Likewise.
* config/arm/exynos-m1.md: Likewise.
* config/arm/fa526.md: Likewise.
* config/arm/fa606te.md: Likewise.
* config/arm/fa626te.md: Likewise.
* config/arm/fa726te.md: Likewise.
* config/arm/fmp626.md: Likewise.
* config/arm/iwmmxt.md: Likewise.
* config/arm/ldmstm.md: Likewise.
* config/arm/marvell-pj4.md: Likewise.
* config/arm/xgene1.md: Likewise.
* config/aarch64/thunderx.md: Likewise.
* config/aarch64/thunderx2t99.md: Likewise.
* config/aarch64/falkor.md: Likewise.
From-SVN: r252025
2017-09-12 Martin Liska <mliska@suse.cz>
* attribs.c (private_lookup_attribute): New function.
* attribs.h (private_lookup_attribute): Declared here.
(lookup_attribute): Called from this place.
From-SVN: r252022
2017-09-12 Richard Biener <rguenther@suse.de>
PR tree-optimization/82157
* tree-ssa-pre.c (remove_dead_inserted_code): Do not remove
stmts with side-effects.
* gcc.dg/torture/pr82157.c: New testcase.
From-SVN: r252020
PR libstdc++/79433
* doc/xml/manual/status_cxx2017.xml: Update feature-test macros.
* doc/html/*: Regenerate.
* include/Makefile.am: Remove <bits/c++17_warning.h>.
* include/Makefile.in: Regenerate.
* include/bits/c++17_warning.h: Remove.
* include/bits/string_view.tcc: Do not include <bits/c++17_warning.h>
for pre-C++17 modes.
* include/std/any: Likewise.
(__cpp_lib_any): Define.
* include/std/mutex (__cpp_lib_scoped_lock): Adjust value as per new
SD-6 draft.
* include/std/numeric (__cpp_lib_gcd_lcm): Define as per new SD-6
draft.
* include/std/optional: Do not include <bits/c++17_warning.h>.
(__cpp_lib_optional): Define.
* include/std/shared_mutex: Do not include <bits/c++14_warning.h>.
* include/std/string_view: Do not include <bits/c++17_warning.h>.
(__cpp_lib_string_view): Define.
* include/std/variant: Do not include <bits/c++17_warning.h>.
(__cpp_lib_variant): Define.
* testsuite/20_util/optional/cons/value_neg.cc: Adjust dg-error line
numbers.
* testsuite/26_numerics/gcd/1.cc: Test for __cpp_lib_gcd_lcm.
* testsuite/26_numerics/gcd/gcd_neg.cc: Adjust dg-error line
numbers.
* testsuite/26_numerics/lcm/1.cc: Test for __cpp_lib_gcd_lcm.
* testsuite/26_numerics/lcm/lcm_neg.cc: Adjust dg-error line
numbers.
* testsuite/30_threads/scoped_lock/requirements/typedefs.cc: Adjust
expected value of __cpp_lib_scoped_lock.
From-SVN: r252018
This patch converts some places that use HARD_REGNO_NREGS to use
hard_regno_nregs, in places where the initialisation has obviously
already taken place.
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/arm/arm.h (THUMB_SECONDARY_INPUT_RELOAD_CLASS): Use
hard_regno_nregs instead of HARD_REGNO_NREGS.
(THUMB_SECONDARY_OUTPUT_RELOAD_CLASS): Likewise.
* config/c6x/c6x.c (c6x_expand_prologue): Likewise.
(c6x_expand_epilogue): Likewise.
* config/frv/frv.c (frv_alloc_temp_reg): Likewise.
(frv_read_iacc_argument): Likewise.
* config/sh/sh.c: Include regs.h.
(sh_print_operand): Use hard_regno_nregs instead of HARD_REGNO_NREGS.
(regs_used): Likewise.
(output_stack_adjust): Likewise.
* config/xtensa/xtensa.c (xtensa_copy_incoming_a7): Likewise.
* expmed.c: Include regs.h.
(store_bit_field_1): Use hard_regno_nregs instead of HARD_REGNO_NREGS.
* ree.c: Include regs.h.
(combine_reaching_defs): Use hard_regno_nregs instead of
HARD_REGNO_NREGS.
(add_removable_extension): Likewise.
From-SVN: r252015
An upcoming patch will convert hard_regno_nregs into an inline
function, which in turn allows hard_regno_nregs to be used as the
name of a targetm field. This patch rewrites a use that can use
in_hard_reg_set_p instead.
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* ira-costs.c (record_operand_costs): Use in_hard_reg_set_p
instead of hard_regno_nregs.
From-SVN: r252013
An upcoming patch will convert hard_regno_nregs into an inline
function, which in turn allows hard_regno_nregs to be used as the
name of a targetm field. This patch rewrites uses that can use
end_hard_regno instead.
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Use
end_hard_regno instead of hard_regno_nregs.
* config/s390/s390.c (s390_reg_clobbered_rtx): Likewise.
* config/sparc/sparc.h (ASM_DECLARE_REGISTER_GLOBAL): Likewise.
* config/visium/visium.c (visium_hard_regno_mode_ok): Likewise.
* ira-color.c (improve_allocation): Likewise.
* lra-assigns.c (find_hard_regno_for_1): Likewise.
* lra-lives.c (mark_regno_live): Likewise.
(mark_regno_dead): Likewise.
* lra-remat.c (operand_to_remat): Likewise.
* lra.c (collect_non_operand_hard_regs): Likewise.
* postreload.c (reload_combine_note_store): Likewise.
(move2add_valid_value_p): Likewise.
* reload.c (regno_clobbered_p): Likewise.
From-SVN: r252012
An upcoming patch will convert hard_regno_nregs into an inline
function, which in turn allows hard_regno_nregs to be used as the
name of a targetm field. This patch rewrites uses that are more
easily (and efficiently) written as END_REGNO.
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
* config/frv/frv.c (FOR_EACH_REGNO): Use END_REGNO instead of
hard_regno_nregs.
* config/v850/v850.c (v850_reorg): Likewise.
* reload.c (refers_to_regno_for_reload_p): Likewise.
(find_equiv_reg): Likewise.
* reload1.c (reload_reg_reaches_end_p): Likewise.
From-SVN: r252011
2017-09-12 Richard Sandiford <richard.sandiford@linaro.org>
gcc/
PR rtl-optimization/82185
* expmed.c (emit_store_flag_int): Only test tem if it has been
initialized.
From-SVN: r252008
* name-lookup.c (get_class_binding): Rename TYPE arg to KLASS for
consistency.
(restort_data): Move later.
(method_name_cmp, resort_method_name_cmp): Simplify.
(resort_type_method_vec): Reformat.
From-SVN: r252004
PR target/82112
* c-common.c (sync_resolve_size): Instead of c_dialect_cxx ()
assertion check that in the condition.
(get_atomic_generic_size): Likewise. Before testing if parameter
has pointer type, if it has array type, call for C++
default_conversion to perform array-to-pointer conversion.
* c-c++-common/pr82112.c: New test.
* gcc.dg/pr82112.c: New test.
From-SVN: r252003
2017-09-12 Richard Biener <rguenther@suse.de>
* tree-vect-generic.c (expand_vector_operations_1): Do nothing
for operations we cannot scalarize.
From-SVN: r252002
2017-09-12 Bob Duff <duff@adacore.com>
* sem_warn.adb: Minor comment.
2017-09-12 Bob Duff <duff@adacore.com>
* libgnat/a-cbdlli.adb, libgnat/a-cbhama.adb,
libgnat/a-cbmutr.adb, libgnat/a-cborma.adb: Rename New_Item to
be Default_Initialized_Item, and apply pragma Unmodified to it,
to suppress the warning.
2017-09-12 Eric Botcazou <ebotcazou@adacore.com>
* exp_aggr.adb (Aggr_Assignment_OK_For_Backend): Add early return
for access types.
2017-09-12 Yannick Moy <moy@adacore.com>
* gnat1drv.adb (Adjust_Global_Switches): Consider Refined_Global
together with Global when ignoring one in CodePeer mode.
2017-09-12 Javier Miranda <miranda@adacore.com>
* sem_ch3.adb (Analyze_Declarations): In nested
package declarations that have a private part enable missing check
of the RM rule 13.1.1(11/3): usage names in aspect definitions are
resolved at the end of the immediately enclosing declaration list.
From-SVN: r252001
2017-09-12 Bob Duff <duff@adacore.com>
* sem_ch6.adb (Analyze_Expression_Function): Initialize Def_Id to
Empty.
2017-09-12 Georges-Axel Jaloyan <jaloyan@adacore.com>
* debug.adb: Reserving flag -gnatdF for safe pointer checking.
* gnat1drv.adb (gnat1drv): Adding the call to the analysis on
dF flag.
* sem_spark.adb, sem_spark.ads: Implementation of the analysis,
in preparation for the evolution of the SPARK language that
includes a pointer analysis for checking non-aliasing of access
types. The Check_Safe_Pointers function is the entry point, and
will traverse the AST and raise compile-time errors everytime
it detects non-begign aliasing. Detailed comments are present
in the sem_spark.ads file.
* sem_util.adb, sem_util.ads (First_Global, Next_Global): New
functions to iterate over the list of globals of a subprogram.
* libgnat/system.ads: Add restriction No_Finalization.
* gcc-interface/Make-lang.in: Add new file sem_spark.adb and
dependency on g-dynhta.adb.
From-SVN: r252000
2017-09-12 Bob Duff <duff@adacore.com>
* sem_ch6.adb (Analyze_Expression_Function): Call
Check_Dynamically_Tagged_Expression.
* sem_util.adb (Check_Dynamically_Tagged_Expression): Remove
"and then Is_Tagged_Type (Typ)" because there is an earlier
"Assert (Is_Tagged_Type (Typ))".
From-SVN: r251999
* tree-ssa-threadbackward.c (fsm_find_thread_path): Make GC
vectors heap vectors. Clean up comments.
Make visited_bbs a reference.
(profitable_jump_thread_path): Make GC
vectors heap vectors. Clean up comments.
Misc cleanups.
(convert_and_register_jump_thread_path): Make GC vectors heap
vectors.
(check_subpath_and_update_thread_path): Same. Clean up comments.
Make visited_bbs a reference.
(handle_phi): Abstract common code to to
register_jump_thread_path_if_profitable.
Rename VAR_BB to DEF_BB.
Update comments.
Make GC vectors heap vectors.
Make visited_bbs a reference.
(handle_assignment): Same.
(register_jump_thread_path_if_profitable): New.
(fsm_find_control_statement_thread_paths): Rename VAR_BB to
DEF_BB.
Make GC vectors heap vectors. Clean up comments.
Make visited_bbs a reference.
(find_jump_threads_backwards): Make visited_bbs live in the stack.
* tree-ssa-threadupdate.c (delete_jump_thread_path): Fix typo in
comment.
From-SVN: r251998
2017-09-11 Max Filippov <jcmvbkbc@gmail.com>
gcc/
* config/xtensa/xtensa.c (xtensa_mem_offset): Check that both
words of E_DImode object are reachable by xtensa_uimm8x4 access.
From-SVN: r251986
PR libstdc++/71500
* include/bits/regex_executor.tcc: Support icase in regex_tratis<...>
for back reference matches.
* testsuite/28_regex/regression.cc: Test case.
From-SVN: r251982
2017-09-11 Arnaud Charlet <charlet@adacore.com>
* doc/gnat_ugn/the_gnat_compilation_model.rst: Fix sphinx warning.
* doc/gnat_ugn/platform_specific_information.rst: Remove doc
for no longer supported platforms.
* doc/gnat_ugn/gnat_and_program_execution.rst: Added detailed
description of the semantics for dimensionality analysis.
* gnat_ugn.texi: Regenerated.
2017-09-11 Eric Botcazou <ebotcazou@adacore.com>
* freeze.adb (Has_Incomplete_Compoent): Delete.
(Freeze_Profile):
Do not inhibit the freezing of the profile of an expression
function here.
(Freeze_Subprogram): Do not re-create extra formals.
* sem_ch6.adb (Analyze_Expression_Function): Always
pre-analyze the expression if the function is not a completion.
(Analyze_Subprogram_Body_Helper): For the body generated
from an expression function that is not a completion, do
not freeze the profile and temporary mask the types declared
outside the expression that are not yet frozen.
* sem_res.adb (Rewrite_Renamed_Operator): Also bail out if invoked
during the pre-analysis of an expression function.
From-SVN: r251978
H.J. Lu
Steve Ellcey
Wilco Dijkstra
Simon Wright
Jakub Jelinek
Carl Love
James Greenhalgh
Martin Liska
Nathan Sidwell
Richard Biener
Jonathan Wakely
Richard Sandiford
Simon Atanasyan
Arnaud Charlet
Bob Duff
Aldy Hernandez
Eric Botcazou
GCC Administrator
Max Filippov
Tim Shen
Vidya Praveen
Kyrylo Tkachov