Commit Graph

179728 Commits

Author SHA1 Message Date
Alan Modra 2dd7b93778 [RS6000] Adjust gcc asm for power10
Generate assembly with .localentry,1 functions using @notoc calls.
This patch makes libgcc.a asm look the same as power10 pcrel as far as
toc/notoc is concerned.

Otherwise calling between functions that advertise as using the TOC
and those that don't, will require linker call stubs in statically
linked code.

gcc/
	* config/rs6000/ppc-asm.h: Support __PCREL__ code.
libgcc/
	* config/rs6000/morestack.S,
	* config/rs6000/tramp.S: Support __PCREL__ code.
libitm/
	* config/powerpc/sjlj.S: Support __PCREL__ code.
2020-10-01 10:34:48 +09:30
Alan Modra c6be439b37 [RS6000] -mno-minimal-toc vs. power10 pcrelative
We've had this hack in the libgcc config to build libgcc with
-mcmodel=small for powerpc64 for a long time.  It wouldn't be a bad
thing if someone who knows the multilib machinery well could arrange
for -mcmodel=small to be passed just for ppc64 when building for
earlier than power10.  But for now, make -mno-minimal-toc do nothing
when pcrel.  Which will do the right thing for any project that has
copied libgcc's trick.

We want this if configuring using --with-cpu=power10 to build a
power10 pcrel libgcc.  --mcmodel=small turns off pcrel.

gcc/
	* config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
	set -mcmodel=small for -mno-minimal-toc when pcrel.
libgcc/
	* config/rs6000/t-linux: Document purpose of -mno-minimal-toc.
2020-10-01 10:34:48 +09:30
Marek Polacek cf7dae0173 c++: CTAD and explicit deduction guides for copy-list-init [PR90210]
This PR points out that we accept

  template<typename T> struct tuple { tuple(T); }; // #1
  template<typename T> explicit tuple(T t) -> tuple<T>; // #2
  tuple t = { 1 };

despite the 'explicit' deduction guide in a copy-list-initialization
context.  That's because in deduction_guides_for we first find the
user-defined deduction guide (#2), and then ctor_deduction_guides_for
creates artificial deduction guides: one from the tuple(T) constructor and
a copy guide.  So we end up with these three guides:

  (1) template<class T> tuple(T) -> tuple<T> [DECL_NONCONVERTING_P]
  (2) template<class T> tuple(tuple<T>) -> tuple<T>
  (3) template<class T> tuple(T) -> tuple<T>

Then, in do_class_deduction, we prune this set, and get rid of (1).
Then overload resolution selects (3) and we succeed.

But [over.match.list]p1 says "In copy-list-initialization, if an explicit
constructor is chosen, the initialization is ill-formed."  It also goes
on to say that this differs from other situations where only converting
constructors are considered for copy-initialization.  Therefore for
list-initialization we consider explicit constructors and complain if one
is chosen.  E.g. convert_like_internal/ck_user can give an error.

So my logic runs that we should not prune the deduction_guides_for guides
in a copy-list-initialization context, and only complain if we actually
choose an explicit deduction guide.  This matches clang++/EDG/msvc++.

gcc/cp/ChangeLog:

	PR c++/90210
	* pt.c (do_class_deduction): Don't prune explicit deduction guides
	in copy-list-initialization.  In copy-list-initialization, if an
	explicit deduction guide was selected, give an error.

gcc/testsuite/ChangeLog:

	PR c++/90210
	* g++.dg/cpp1z/class-deduction73.C: New test.
2020-09-30 20:56:42 -04:00
GCC Administrator 660bfe61d4 Daily bump. 2020-10-01 00:16:30 +00:00
Jonathan Wakely d1ac0f0dfb libstdc++: Fix test_and_acquire / set_and_release for EABI guard variables
The default definitions of _GLIBCXX_GUARD_TEST_AND_ACQUIRE and
_GLIBCXX_GUARD_SET_AND_RELEASE in libsupc++/guard.cc only work for the
generic (IA64) ABI, because they test/set the first byte of the guard
variable. For EABI we need to use the least significant bit, which means
using the first byte is wrong for big endian targets.

This has been wrong since r224411, but previously it only caused poor
performance. The _GLIBCXX_GUARD_TEST_AND_ACQUIRE at the very start of
__cxa_guard_acquire would always return false even if the initialization
was actually complete. Before my r11-3484 change the atomic compare
exchange would have loaded the correct value, and then returned 0 as
expected when the initialization is complete. After my change, in the
single-threaded case there is no redundant check for init being
complete, because I foolishly assumed that the check at the start of the
function actually worked.

The default definition of _GLIBCXX_GUARD_SET_AND_RELEASE is also wrong
for big endian EABI, but appears to work because it sets the wrong bit
but then the buggy TEST_AND_ACQUIRE tests that wrong bit as well. Also,
the buggy SET_AND_RELEASE macro is only used for targets with threads
enabled but no futex syscalls.

This should fix the regressions introduced by my patch, by defining
custom versions of the TEST_AND_ACQUIRE and SET_AND_RELEASE macros that
are correct for EABI.

libstdc++-v3/ChangeLog:

	* config/cpu/arm/cxxabi_tweaks.h (_GLIBCXX_GUARD_TEST_AND_ACQUIRE):
	(_GLIBCXX_GUARD_SET_AND_RELEASE): Define for EABI.
2020-09-30 21:14:43 +01:00
Martin Sebor 7dbc7ad524 Avoid assuming a VLA access specification string contains a closing bracket (PR middle-end/97189).
Resolves:
PR middle-end/97189 - ICE on redeclaration of a function with VLA argument and attribute access

gcc/ChangeLog:

	PR middle-end/97189
	* attribs.c (attr_access::array_as_string): Avoid assuming a VLA
	access specification string contains a closing bracket.

gcc/c-family/ChangeLog:

	PR middle-end/97189
	* c-attribs.c (append_access_attr): Use the function declaration
	location for a warning about an attribute access argument.

gcc/testsuite/ChangeLog:

	PR middle-end/97189
	* gcc.dg/attr-access-2.c: Adjust caret location.
	* gcc.dg/Wvla-parameter-6.c: New test.
	* gcc.dg/Wvla-parameter-7.c: New test.
2020-09-30 12:59:53 -06:00
Martin Sebor e808f3fdfa PR c/97206 - ICE in composite_type on declarations of a similar array types
gcc/ChangeLog:

	PR c/97206
	* attribs.c (attr_access::array_as_string): Avoid modifying a shared
	type in place and use build_type_attribute_qual_variant instead.

gcc/testsuite/ChangeLog:

	PR c/97206
	* gcc.dg/Warray-parameter-7.c: New test.
	* gcc.dg/Warray-parameter-8.c: New test.
	* gcc.dg/Wvla-parameter-5.c: New test.
2020-09-30 12:59:53 -06:00
Jonathan Wakely 73ae6eb572 libstdc++: Use __is_same instead of __is_same_as
PR 92271 added __is_same as another spelling of __is_same_as. Since
Clang also spells it __is_same, let's just use that consistently.

It appears that Intel icc sets __GNUC__ to 10, but only supports
__is_same_as. If we only use __is_same for __GNUC__ >= 11 then we won't
break icc again (it looks like we broke previous versions of icc when we
started using __is_same_as).

libstdc++-v3/ChangeLog:

	* include/bits/c++config (_GLIBCXX_HAVE_BUILTIN_IS_SAME):
	Define for GCC 11 or when !__is_identifier(__is_same).
	(_GLIBCXX_BUILTIN_IS_SAME_AS): Remove.
	* include/std/type_traits (is_same, is_same_v): Replace uses
	of _GLIBCXX_BUILTIN_IS_SAME_AS.
2020-09-30 18:41:12 +01:00
Andrew Stubbs 091ddcc1b2 libgomp: Enforce 1-thread limit in subteams
Accelerators with fixed thread-counts will break if nested teams are expected
to have multiple threads each.

libgomp/ChangeLog:

2020-09-29  Andrew Stubbs  <ams@codesourcery.com>

	* parallel.c (gomp_resolve_num_threads): Ignore nest_var on nvptx
	and amdgcn targets.
2020-09-30 17:37:31 +01:00
Jan Hubicka ecd700c1bc Fix some fnspec strings in trans-decl.c
* trans-decl.c (gfc_build_intrinsic_function_decls): Add traling dots
	to spec strings so they match the number of parameters; do not use
	R and W for non-pointer parameters. Drop pointless specifier on
	caf_stop_numeric and caf_get_team.
2020-09-30 18:00:42 +02:00
Jan Hubicka 1814c828a0 Add trailing dots so length of spec string matches number of arguments.
2020-09-30  Jan Hubicka  <hubicka@ucw.cz>

	* trans-io.c (gfc_build_io_library_fndecls): Add trailing dots so
	length of spec string matches number of arguments.
2020-09-30 17:23:55 +02:00
H.J. Lu 373b99dc40 Add a testcase for PR target/96827
Add a testcase for PR target/96827 which was fixed by r11-3559:

commit 97b798d80b
Author: Joel Hutton <joel.hutton@arm.com>
Date:   Wed Sep 30 15:08:13 2020 +0100

    [SLP][VECT] Add check to fix 96837

	PR target/96827
	* gcc.target/i386/pr96827.c: New test.
2020-09-30 08:13:21 -07:00
Christophe Lyon ef11f5b37b arm: [testsuite] Skip thumb2-cond-cmp tests on Cortex-M [PR94595]
Since r204778 (g571880a0a4c512195aa7d41929ba6795190887b2), we favor
branches over IT blocks on Cortex-M. As a result, instead of
generating two nested IT blocks in thumb2-cond-cmp-[1234].c, we
generate either a single IT block, or use branches depending on
conditions tested by the program.

Since this was a deliberate change and the tests still pass as
expected on Cortex-A, this patch skips them when targetting
Cortex-M. The avoids the failures on Cortex M3, M4, and M33.  This
patch makes the testcases unsupported on Cortex-M7 although they pass
in this case because this CPU has different branch costs.

I tried to relax the scan-assembler directives using eg. cmpne|subne
or cmpgt|ble but that seemed fragile.

2020-09-07  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	PR target/94595
	* gcc.target/arm/thumb2-cond-cmp-1.c: Skip if arm_cortex_m.
	* gcc.target/arm/thumb2-cond-cmp-2.c: Skip if arm_cortex_m.
	* gcc.target/arm/thumb2-cond-cmp-3.c: Skip if arm_cortex_m.
	* gcc.target/arm/thumb2-cond-cmp-4.c: Skip if arm_cortex_m.
2020-09-30 14:55:45 +00:00
Richard Biener 9ff2bcd9df amend SLP reduction testcases
This amends SLP reduction testcases that currently trigger
vect_attempt_slp_rearrange_stmts eliding load permutations to
verify this is actually happening.

2020-09-30  Richard Biener  <rguenther@suse.de>

	* gcc.dg/vect/pr37027.c: Amend.
	* gcc.dg/vect/pr67790.c: Likewise.
	* gcc.dg/vect/pr92324-4.c: Likewise.
	* gcc.dg/vect/pr92558.c: Likewise.
	* gcc.dg/vect/pr95495.c: Likewise.
	* gcc.dg/vect/slp-reduc-1.c: Likewise.
	* gcc.dg/vect/slp-reduc-2.c: Likewise.
	* gcc.dg/vect/slp-reduc-3.c: Likewise.
	* gcc.dg/vect/slp-reduc-4.c: Likewise.
	* gcc.dg/vect/slp-reduc-5.c: Likewise.
	* gcc.dg/vect/slp-reduc-7.c: Likewise.
	* gcc.dg/vect/vect-reduc-in-order-4.c: Likewise.
2020-09-30 16:54:37 +02:00
Przemyslaw Wirkus 60e4b3cade arm: add support for Cortex-A78 and Cortex-A78AE
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.

	[0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
	[1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae

OK for master branch ?

kind regards
Przemyslaw Wirkus

gcc/ChangeLog:

	* config/arm/arm-cpus.in: Add Cortex-A78 and Cortex-A78AE cores.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* doc/invoke.texi: Update docs.
2020-09-30 15:39:24 +01:00
Przemyslaw Wirkus b6860cb96d aarch64: add support for Cortex-A78 and Cortex-A78AE
This patch introduces support for Cortex-A78 [0] and Cortex-A78AE [1]
cpus.

    [0]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78
    [1]: https://www.arm.com/products/silicon-ip-cpu/cortex-a/cortex-a78ae

OK for master branch ?

kind regards
Przemyslaw Wirkus

gcc/ChangeLog:

	* config/aarch64/aarch64-cores.def: Add Cortex-A78 and Cortex-A78AE cores.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* doc/invoke.texi: Add -mtune=cortex-a78 and -mtune=cortex-a78ae.
2020-09-30 15:38:49 +01:00
Srinath Parvathaneni 6bd4ce64eb [GCC][PATCH] arm: Fix MVE intrinsics polymorphic variants wrongly generating __ARM_undef type (pr96795).
Hello,

This patch fixes (PR96795) MVE intrinsic polymorphic variants vaddq, vaddq_m, vaddq_x, vcmpeqq_m,
vcmpeqq, vcmpgeq_m, vcmpgeq, vcmpgtq_m, vcmpgtq, vcmpleq_m, vcmpleq, vcmpltq_m, vcmpltq,
vcmpneq_m, vcmpneq, vfmaq_m, vfmaq, vfmasq_m, vfmasq, vmaxnmavq, vmaxnmavq_p, vmaxnmvq,
vmaxnmvq_p, vminnmavq, vminnmavq_p, vminnmvq, vminnmvq_p, vmulq_m, vmulq, vmulq_x, vsetq_lane,
vsubq_m, vsubq and vsubq_x which are incorrectly generating __ARM_undef and mismatching the passed
floating point scalar arguments.

Bootstrapped on arm-none-linux-gnueabihf and regression tested on arm-none-eabi and found no regressions.

Ok for master? Ok for GCC-10 branch?

Regards,
Srinath.

gcc/ChangeLog:

2020-09-30  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	PR target/96795
	* config/arm/arm_mve.h (__ARM_mve_coerce2): Define.
	(__arm_vaddq): Correct the scalar argument.
	(__arm_vaddq_m): Likewise.
	(__arm_vaddq_x): Likewise.
	(__arm_vcmpeqq_m): Likewise.
	(__arm_vcmpeqq): Likewise.
	(__arm_vcmpgeq_m): Likewise.
	(__arm_vcmpgeq): Likewise.
	(__arm_vcmpgtq_m): Likewise.
	(__arm_vcmpgtq): Likewise.
	(__arm_vcmpleq_m): Likewise.
	(__arm_vcmpleq): Likewise.
	(__arm_vcmpltq_m): Likewise.
	(__arm_vcmpltq): Likewise.
	(__arm_vcmpneq_m): Likewise.
	(__arm_vcmpneq): Likewise.
	(__arm_vfmaq_m): Likewise.
	(__arm_vfmaq): Likewise.
	(__arm_vfmasq_m): Likewise.
	(__arm_vfmasq): Likewise.
	(__arm_vmaxnmavq): Likewise.
	(__arm_vmaxnmavq_p): Likewise.
	(__arm_vmaxnmvq): Likewise.
	(__arm_vmaxnmvq_p): Likewise.
	(__arm_vminnmavq): Likewise.
	(__arm_vminnmavq_p): Likewise.
	(__arm_vminnmvq): Likewise.
	(__arm_vminnmvq_p): Likewise.
	(__arm_vmulq_m): Likewise.
	(__arm_vmulq): Likewise.
	(__arm_vmulq_x): Likewise.
	(__arm_vsetq_lane): Likewise.
	(__arm_vsubq_m): Likewise.
	(__arm_vsubq): Likewise.
	(__arm_vsubq_x): Likewise.

gcc/testsuite/ChangeLog:

	PR target/96795
	* gcc.target/arm/mve/intrinsics/mve_fp_vaddq_n.c: New Test.
	* gcc.target/arm/mve/intrinsics/mve_vaddq_n.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vaddq_x_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpleq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpltq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmpneq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmaq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vfmasq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmavq_p_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vminnmvq_p_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vmulq_x_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsetq_lane_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsetq_lane_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_m_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_n_f32-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f16-1.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vsubq_x_n_f32-1.c: Likewise.
2020-09-30 15:20:14 +01:00
Joel Hutton 97b798d80b [SLP][VECT] Add check to fix 96837
The following patch adds a simple check to prevent slp stmts from
vector constructors being rearranged. vect_attempt_slp_rearrange_stmts
tries to rearrange to avoid a load permutation.

This fixes PR target/96837
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96827

gcc/ChangeLog:

2020-09-29  Joel Hutton  <joel.hutton@arm.com>

	PR target/96837
	* tree-vect-slp.c (vect_analyze_slp): Do not call
	vect_attempt_slp_rearrange_stmts for vector constructors.

gcc/testsuite/ChangeLog:

2020-09-29  Joel Hutton  <joel.hutton@arm.com>

	PR target/96837
	* gcc.dg/vect/bb-slp-49.c: New test.
2020-09-30 15:16:29 +01:00
Tamar Christina aa248b8db9 middle-end: Refactor refcnt to use SLP_TREE_REF_COUNT for consistency
This is a small refactoring which introduces SLP_TREE_REF_COUNT and replaces
the uses of refcnt with it.  This for consistency between the other properties.

A similar patch was pre-approved last year but since there are more use now I am
sending it for review anyway.

gcc/ChangeLog:

	* tree-vectorizer.h (SLP_TREE_REF_COUNT): New.
	* tree-vect-slp.c (_slp_tree::_slp_tree, _slp_tree::~_slp_tree,
	vect_free_slp_tree, vect_build_slp_tree, vect_print_slp_tree,
	slp_copy_subtree, vect_attempt_slp_rearrange_stmts): Use it.
2020-09-30 14:47:20 +01:00
Nathan Sidwell 734eed6853 c++: Kill DECL_HIDDEN_FRIEND_P
Now hiddenness is managed by name-lookup, we no longer need DECL_HIDDEN_FRIEND_P.
This removes it.  Mainly by deleting its bookkeeping, but there are a couple of uses

1) two name lookups look at it to see if they found a hidden thing.
In one we have the OVERLOAD, so can record OVL_HIDDEN_P.  In the other
we're repeating a lookup that failed, but asking for hidden things --
so if that succeeds we know the thing was hidden.  (FWIW CWG recently
discussed whether template specializations and instantiations should
see such hidden templates anyway, there is compiler divergence.)

2) We had a confusing setting of KOENIG_P when building a
non-dependent call.  We don't repeat that lookup at instantiation time
anyway.

	gcc/cp/
	* cp-tree.h (struct lang_decl_fn): Remove hidden_friend_p.
	(DECL_HIDDEN_FRIEND_P): Delete.
	* call.c (add_function_candidate): Drop assert about anticipated
	decl.
	(build_new_op_1): Drop koenig lookup flagging for hidden friend.
	* decl.c (duplicate_decls): Drop HIDDEN_FRIEND_P updating.
	* name-lookup.c (do_pushdecl): Likewise.
	(set_decl_namespace): Discover hiddenness from OVL_HIDDEN_P.
	* pt.c (check_explicit_specialization): Record found_hidden
	explicitly.
2020-09-30 06:44:19 -07:00
Tobias Burnus 65167982ef Fortran: add contiguous check for ptr assignment, fix non-contig check (PR97242)
gcc/fortran/ChangeLog:

	PR fortran/97242
	* expr.c (gfc_is_not_contiguous): Fix check.
	(gfc_check_pointer_assign): Use it.

gcc/testsuite/ChangeLog:

	PR fortran/97242
	* gfortran.dg/contiguous_11.f90: New test.
	* gfortran.dg/contiguous_4.f90: Update.
	* gfortran.dg/contiguous_7.f90: Update.
2020-09-30 15:01:13 +02:00
Tobias Burnus 8b0a63e47c OpenMP: Add implicit declare target for nested procedures
gcc/ChangeLog:

	* omp-offload.c (omp_discover_implicit_declare_target): Also
	handled nested functions.

libgomp/ChangeLog:

	* testsuite/libgomp.fortran/declare-target-3.f90: New test.
2020-09-30 14:59:27 +02:00
Paul Thomas fcc4891d7f This patch fixes PR97045 - unlimited polymorphic array element selectors.
2020-30-09  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
	PR fortran/97045
	* trans-array.c (gfc_conv_array_ref): Make sure that the class
	decl is passed to build_array_ref in the case of unlimited
	polymorphic entities.
	* trans-expr.c (gfc_conv_derived_to_class): Ensure that array
	refs do not preceed the _len component. Free the _len expr.
	* trans-stmt.c (trans_associate_var): Reset 'need_len_assign'
	for polymorphic scalars.
	* trans.c (gfc_build_array_ref): When the vptr size is used for
	span, multiply by the _len field of unlimited polymorphic
	entities, when non-zero.

gcc/testsuite/
	PR fortran/97045
	* gfortran.dg/select_type_50.f90 : New test.
2020-09-30 13:44:39 +01:00
Tom de Vries bae974e637 [nvptx] Add type arg to TARGET_LIBC_HAS_FUNCTION
GCC has a target hook TARGET_LIBC_HAS_FUNCTION, which tells the compiler
which functions it can expect to be present in libc.

The default target hook does not include the sincos functions.

The nvptx port of newlib does include sincos and sincosf, but not sincosl.

The target hook TARGET_LIBC_HAS_FUNCTION does not distinguish between sincos,
sincosf and sincosl, so if we enable it for the sincos functions, then for
test.c:
...
long double x, a, b;
int main (void) {
  x = 0.5;
  a = sinl (x);
  b = cosl (x);
  printf ("a: %f\n", (double)a);
  printf ("b: %f\n", (double)b);
  return 0;
}
...
we introduce a regression:
...
$ gcc test.c -lm -O2
unresolved symbol sincosl
collect2: error: ld returned 1 exit status
...

Add a type argument to target hook TARGET_LIBC_HAS_FUNCTION_TYPE, and use it
in nvptx_libc_has_function_type to enable sincos and sincosf, but not sincosl.

Build and reg-tested on x86_64-linux.

Build and tested on nvptx.

gcc/ChangeLog:

2020-09-28  Tobias Burnus  <tobias@codesourcery.com>
	    Tom de Vries  <tdevries@suse.de>

	* builtins.c (expand_builtin_cexpi, fold_builtin_sincos): Update
	targetm.libc_has_function call.
	* builtins.def (DEF_C94_BUILTIN, DEF_C99_BUILTIN, DEF_C11_BUILTIN):
	(DEF_C2X_BUILTIN, DEF_C99_COMPL_BUILTIN, DEF_C99_C90RES_BUILTIN):
	Same.
	* config/darwin-protos.h (darwin_libc_has_function): Update prototype.
	* config/darwin.c (darwin_libc_has_function): Add arg.
	* config/linux-protos.h (linux_libc_has_function): Update prototype.
	* config/linux.c (linux_libc_has_function): Add arg.
	* config/i386/i386.c (ix86_libc_has_function): Update
	targetm.libc_has_function call.
	* config/nvptx/nvptx.c (nvptx_libc_has_function): New function.
	(TARGET_LIBC_HAS_FUNCTION): Redefine to nvptx_libc_has_function.
	* convert.c (convert_to_integer_1): Update targetm.libc_has_function
	call.
	* match.pd: Same.
	* target.def (libc_has_function): Add arg.
	* doc/tm.texi: Regenerate.
	* targhooks.c (default_libc_has_function, gnu_libc_has_function)
	(no_c99_libc_has_function): Add arg.
	* targhooks.h (default_libc_has_function, no_c99_libc_has_function)
	(gnu_libc_has_function): Update prototype.
	* tree-ssa-math-opts.c (pass_cse_sincos::execute): Update
	targetm.libc_has_function call.

gcc/fortran/ChangeLog:

2020-09-30  Tom de Vries  <tdevries@suse.de>

	* f95-lang.c (gfc_init_builtin_functions):  Update
	targetm.libc_has_function call.
2020-09-30 14:36:56 +02:00
H.J. Lu 46183c96d2 x86: Use SET operation in MOVDIRI and MOVDIR64B
Since MOVDIRI and MOVDIR64B write to memory, similar to UNSPEC_MOVNT,
use SET operation in MOVDIRI and MOVDIR64B patterns with UNSPEC instead
of UNSPECV.

gcc/

	PR target/97184
	* config/i386/i386.md (UNSPECV_MOVDIRI): Renamed to ...
	(UNSPEC_MOVDIRI): This.
	(UNSPECV_MOVDIR64B): Renamed to ...
	(UNSPEC_MOVDIR64B): This.
	(movdiri<mode>): Use SET operation.
	(@movdir64b_<mode>): Likewise.

gcc/testsuite/

	PR target/97184
	* gcc.target/i386/movdir64b.c: New test.
	* gcc.target/i386/movdiri32.c: Likewise.
	* gcc.target/i386/movdiri64.c: Likewise.
	* lib/target-supports.exp (check_effective_target_movdir): New.
2020-09-30 05:34:37 -07:00
Tom de Vries 4c0eb14bc8 [testsuite] Re-enable pr94600-{1,3}.c tests for arm
Before commit 7e43716200 "[testsuite] Require non_strict_align in
pr94600-{1,3}.c", some tests were failing for nvptx, because volatile stores
were expected, but memcpy's were found instead.

This was traced back to this bit in compute_record_mode:
...
  /* If structure's known alignment is less than what the scalar
     mode would need, and it matters, then stick with BLKmode.  */
  if (mode != BLKmode
      && STRICT_ALIGNMENT
      && ! (TYPE_ALIGN (type) >= BIGGEST_ALIGNMENT
            || TYPE_ALIGN (type) >= GET_MODE_ALIGNMENT (mode)))
    {
      /* If this is the only reason this type is BLKmode, then
         don't force containing types to be BLKmode.  */
      TYPE_NO_FORCE_BLK (type) = 1;
      mode = BLKmode;
    }
...
which got triggered for nvptx, but not for x86_64.

The commit disabled the tests for non_strict_align effective target, but
that had the effect for the arm target that those tests were disabled, even
though they were passing before.

Further investigation in compute_record_mode shows that the if-condition
evaluates to false for arm because, because TYPE_ALIGN (type) == 32, while
it's 8 for nvptx.  This again can be explained by the
PCC_BITFIELD_TYPE_MATTERS setting, which is 1 for arm, but 0 for nvptx.

Re-enable the test for arm by using effective target
(non_strict_align || pcc_bitfield_type_matters).

Tested on arm-eabi and nvptx.

gcc/testsuite/ChangeLog:

2020-09-30  Tom de Vries  <tdevries@suse.de>

	* gcc.dg/pr94600-1.c: Use effective target
	(non_strict_align || pcc_bitfield_type_matters).
	* gcc.dg/pr94600-3.c: Same.
2020-09-30 14:19:08 +02:00
Florian Weimer 92e652d8c2 i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on ISA flags
gcc/
	* config/i386/i386-c.c (ix86_target_macros_internal): Define
	__LAHF_SAHF__ and __MOVBE__ based on ISA flags.
2020-09-30 14:15:12 +02:00
Jakub Jelinek 7d13102991 testsuite: Fix up amx* dg-do run tests with older binutils
These tests were missing dg-requires-effective-targets to ensure they
are UNSUPPORTED if the assembler doesn't have AMX support.

2020-09-30  Jakub Jelinek  <jakub@redhat.com>

	* gcc.target/i386/amxint8-dpbssd-2.c: Require effective targets
	amx_tile and amx_int8.
	* gcc.target/i386/amxint8-dpbsud-2.c: Likewise.
	* gcc.target/i386/amxint8-dpbusd-2.c: Likewise.
	* gcc.target/i386/amxint8-dpbuud-2.c: Likewise.
	* gcc.target/i386/amxbf16-dpbf16ps-2.c: Require effective targets
	amx_tile and amx_bf16.
	* gcc.target/i386/amxtile-2.c: Require effective target amx_tile.
2020-09-30 13:21:04 +02:00
Kyrylo Tkachov 2d8fbebdb1 PR target/97150 AArch64: 2nd parameter of unsigned Neon scalar shift intrinsics should be signed
In this PR the second argument to the intrinsics should be signed but we
use an unsigned one erroneously.
The corresponding builtins are already using the correct types so it's
just a matter of correcting the signatures in arm_neon.h

gcc/
	PR target/97150
	* config/aarch64/arm_neon.h (vqrshlb_u8): Make second argument
	signed.
	(vqrshlh_u16): Likewise.
	(vqrshls_u32): Likewise.
	(vqrshld_u64): Likewise.
	(vqshlb_u8): Likewise.
	(vqshlh_u16): Likewise.
	(vqshls_u32): Likewise.
	(vqshld_u64): Likewise.
	(vshld_u64): Likewise.

gcc/testsuite/
	PR target/97150
	* gcc.target/aarch64/pr97150.c: New test.
2020-09-30 12:02:21 +01:00
Kyrylo Tkachov 135b043196 PR target/96313 AArch64: vqmovun* return types should be unsigned
In this PR we have the wrong return type for some intrinsics. It should
be unsigned, but we implement it as signed.
Fix this by adjusting the type qualifiers used when creating the
builtins and fixing the type in the arm_neon.h intrinsic.
With the adjustment in qualifiers we now don't need to cast the result
when returning.

Bootstrapped and tested on aarch64-none-linux-gnu.

gcc/
	PR target/96313
	* config/aarch64/aarch64-simd-builtins.def (sqmovun): Use UNOPUS
	qualifiers.
	* config/aarch64/arm_neon.h (vqmovun_s16): Adjust builtin call.
	Remove unnecessary result cast.
	(vqmovun_s32): Likewise.
	(vqmovun_s64): Likewise.
	(vqmovunh_s16): Likewise.  Fix return type.
	(vqmovuns_s32): Likewise.
	(vqmovund_s64): Likewise.

gcc/testsuite/
	PR target/96313
	* gcc.target/aarch64/pr96313.c: New test.
	* gcc.target/aarch64/scalar_intrinsics.c (test_vqmovunh_s16):
	Adjust return type.
	(test_vqmovuns_s32): Likewise.
	(test_vqmovund_s64): Likewise.
2020-09-30 12:02:21 +01:00
Richard Sandiford d4f9e81976 aarch64: Tweak movti and movtf patterns
movti lacked an way of zeroing an FPR, meaning that we'd do:

        mov     x0, 0
        mov     x1, 0
        fmov    d0, x0
        fmov    v0.d[1], x1

instead of just:

        movi    v0.2d, #0

movtf had the opposite problem for GPRs: we'd generate:

        movi    v0.2d, #0
        fmov    x0, d0
        fmov    x1, v0.d[1]

instead of just:

        mov     x0, 0
        mov     x1, 0

Also, there was an unnecessary earlyclobber on the GPR<-GPR movtf
alternative (but not the movti one).  The splitter handles overlap
correctly.

The TF splitter used aarch64_reg_or_imm, but the _imm part only
accepts integer constants, not floating-point ones.  The patch
changes it to nonmemory_operand instead.

gcc/
	* config/aarch64/aarch64.c (aarch64_split_128bit_move_p): Add a
	function comment.  Tighten check for FP moves.
	* config/aarch64/aarch64.md (*movti_aarch64): Add a w<-Z alternative.
	(*movtf_aarch64): Handle r<-Y like r<-r.  Remove unnecessary
	earlyclobber.  Change splitter predicate from aarch64_reg_or_imm
	to nonmemory_operand.

gcc/testsuite/
	* gcc.target/aarch64/movtf_1.c: New test.
	* gcc.target/aarch64/movti_1.c: Likewise.
2020-09-30 11:52:06 +01:00
Alex Coplan f63023fafb arm: Fix ICEs in no-literal-pool.c on MVE [PR97251]
This patch fixes ICEs when compiling
gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c with
-mfp16-format=ieee -mfloat-abi=hard -march=armv8.1-m.main+mve
-mpure-code.

The existing conditions in the movsf/movdf expanders (as well as the
no_literal_pool patterns) were too restrictive, requiring
TARGET_HARD_FLOAT instead of TARGET_VFP_BASE, which caused unrecognised
insns when compiling this testcase with integer MVE and -mpure-code.

gcc/ChangeLog:

	PR target/97251
	* config/arm/arm.md (movsf): Relax TARGET_HARD_FLOAT to
	TARGET_VFP_BASE.
	(movdf): Likewise.
	* config/arm/vfp.md (no_literal_pool_df_immediate): Likewise.
	(no_literal_pool_sf_immediate): Likewise.
2020-09-30 09:02:47 +01:00
Alan Modra de2c1d00f2 gcc/configure typo fix
* configure.ac (--with-long-double-format): Typo fix.
	* configure: Regenerate.
2020-09-30 12:36:52 +09:30
Alan Modra ac001f5ce6 Re: rs6000: Use parameterized names for tablejump
* config/rs6000/rs6000.md (@tablejump<mode>_normal): Don't use
	non-existent operands[].
	(@tablejump<mode>_nospec): Likewise.
2020-09-30 12:36:52 +09:30
GCC Administrator 93bca37c0a Daily bump. 2020-09-30 00:16:29 +00:00
Segher Boessenkool 58614b10ed rs6000: Use parameterized names for tablejump
We have too many tablejump patterns.  Using parameterized names
simplifies the code a bit.

2020-09-29  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (tablejump): Simplify.
	(tablejumpsi): Merge this ...
	(tablejumpdi): ... and this ...
	(@tablejump<mode>_normal): ... into this.
	(tablejumpsi_nospec): Merge this ...
	(tablejumpdi_nospec): ... and this ...
	(@tablejump<mode>_nospec): ... into this.
	(*tablejump<mode>_internal1): Delete, rename to ...
	(@tablejump<mode>_insn_normal): ... this.
	(*tablejump<mode>_internal1_nospec): Delete, rename to ...
	(@tablejump<mode>_insn_nospec): ... this.
2020-09-30 00:13:47 +00:00
Martin Sebor 873f8c1e6d Correct and improve -Wnonnull for calls to functions with VLA arguments (PR middle-end/97188).
Resolves:
PR middle-end/97188 - ICE passing a null VLA to a function expecting at least one element

gcc/ChangeLog:

	PR middle-end/97188
	* calls.c (maybe_warn_rdwr_sizes): Simplify warning messages.
	Correct handling of VLA argumments.

gcc/testsuite/ChangeLog:

	PR middle-end/97188
	* gcc.dg/Wstringop-overflow-23.c: Adjust text of expected warnings.
	* gcc.dg/Wnonnull-4.c: New test.
2020-09-29 17:13:55 -06:00
Marek Polacek 969baf03ac c++: Implement -Wrange-loop-construct [PR94695]
This new warning can be used to prevent expensive copies inside range-based
for-loops, for instance:

  struct S { char arr[128]; };
  void fn () {
    S arr[5];
    for (const auto x : arr) {  }
  }

where auto deduces to S and then we copy the big S in every iteration.
Using "const auto &x" would not incur such a copy.  With this patch the
compiler will warn:

q.C:4:19: warning: loop variable 'x' creates a copy from type 'const S' [-Wrange-loop-construct]
    4 |   for (const auto x : arr) {  }
      |                   ^
q.C:4:19: note: use reference type 'const S&' to prevent copying
    4 |   for (const auto x : arr) {  }
      |                   ^
      |                   &

As per Clang, this warning is suppressed for trivially copyable types
whose size does not exceed 64B.  The tricky part of the patch was how
to figure out if using a reference would have prevented a copy.  To
that point, I'm using the new function called ref_conv_binds_directly_p.

This warning is enabled by -Wall.  Further warnings of similar nature
should follow soon.

gcc/c-family/ChangeLog:

	PR c++/94695
	* c.opt (Wrange-loop-construct): New option.

gcc/cp/ChangeLog:

	PR c++/94695
	* call.c (ref_conv_binds_directly_p): New function.
	* cp-tree.h (ref_conv_binds_directly_p): Declare.
	* parser.c (warn_for_range_copy): New function.
	(cp_convert_range_for): Call it.

gcc/ChangeLog:

	PR c++/94695
	* doc/invoke.texi: Document -Wrange-loop-construct.

gcc/testsuite/ChangeLog:

	PR c++/94695
	* g++.dg/warn/Wrange-loop-construct.C: New test.
2020-09-29 19:03:04 -04:00
David Edelsohn 01852cc865 testsuite: Remove unnecessary DWARF2 xfails on AIX
A number of DWARF2 testsuite xfails no longer trigger on AIX.  This patch
removes the unnecessary XFAIL decorations that cause extraneous notices
that clutter the testsuite output.

gcc/testsuite/ChangeLog:

2020-09-29  David Edelsohn  <dje.gcc@gmail.com>

	* g++.dg/debug/dwarf2/align-1.C: Remove AIX XFAIL.
	* g++.dg/debug/dwarf2/align-2.C: Same.
	* g++.dg/debug/dwarf2/align-3.C: Same.
	* g++.dg/debug/dwarf2/align-4.C: Same.
	* g++.dg/debug/dwarf2/align-5.C: Same.
	* g++.dg/debug/dwarf2/align-6.C: Same.
	* g++.dg/debug/dwarf2/defaulted-member-function-1.C: Same.
	* g++.dg/debug/dwarf2/defaulted-member-function-2.C: Same.
	* g++.dg/debug/dwarf2/defaulted-member-function-3.C: Same.
	* g++.dg/debug/dwarf2/inline-var-1.C: Same.
	* g++.dg/debug/dwarf2/inline-var-2.C: Same.
	* g++.dg/debug/dwarf2/inline-var-3.C: Same.
	* g++.dg/debug/dwarf2/noreturn-function.C: Same.
	* g++.dg/debug/dwarf2/ptrdmem-1.C: Same.
	* g++.dg/debug/dwarf2/ref-2.C: Same.
	* g++.dg/debug/dwarf2/ref-3.C: Same.
	* g++.dg/debug/dwarf2/ref-4.C: Same.
	* g++.dg/debug/dwarf2/refqual-1.C: Same.
	* g++.dg/debug/dwarf2/refqual-2.C: Same.
	* gcc.dg/debug/dwarf2/align-1.c: Same.
	* gcc.dg/debug/dwarf2/align-2.c: Same.
	* gcc.dg/debug/dwarf2/align-3.c: Same.
	* gcc.dg/debug/dwarf2/align-4.c: Same.
	* gcc.dg/debug/dwarf2/align-5.c: Same.
	* gcc.dg/debug/dwarf2/align-6.c: Same.
	* gcc.dg/debug/dwarf2/align-as-1.c: Same.
	* gcc.dg/debug/dwarf2/dwarf2-macro.c: Same.
	* gcc.dg/debug/dwarf2/dwarf2-macro2.c: Same.
	* gcc.dg/debug/dwarf2/lang-c89.c: Same.
	* gcc.dg/debug/dwarf2/noreturn-function-attribute.c: Same.
	* gcc.dg/debug/dwarf2/noreturn-function-keyword.c: Same.
	* gcc.dg/debug/dwarf2/pr71855.c: Same.
	* gcc.dg/debug/dwarf2/inline5.c: Add XFAIL on AIX.
2020-09-29 19:00:45 -04:00
David Malcolm d60d63a00b analyzer: fix signal-handler registration location [PR95188]
PR analyzer/95188 reports that diagnostics from
-Wanalyzer-unsafe-call-within-signal-handler use the wrong
source location when reporting the signal-handler registration
event in the diagnostic_path.  The diagnostics erroneously use the
location of the first stmt in the basic block containing the call
to "signal", rather than that of the call itself.

Fixed thusly.

gcc/analyzer/ChangeLog:
	PR analyzer/95188
	* engine.cc (stmt_requires_new_enode_p): Split enodes before
	"signal" calls.

gcc/testsuite/ChangeLog:
	PR analyzer/95188
	* gcc.dg/analyzer/signal-registration-loc.c: New test.
2020-09-29 18:31:48 -04:00
Jim Wilson 6649df18f9 Fix GCC 10+ build failure with zstd version 1.2.0 or older.
Extends the configure check for zstd.h to also verify the zstd version,
since gcc requires features that only exist in 1.3.0 and newer.  Without
this patch we get a build error for lto-compress.c when using an old zstd
version.

	gcc/
	PR bootstrap/97183
	* configure.ac (gcc_cv_header_zstd_h): Check ZSTD_VERISON_NUMBER.
	* configure: Regenerated.
2020-09-29 15:27:16 -07:00
Przemyslaw Wirkus 0eef5eea2b arm: add support for Cortex-X1
This adds support for the Arm Cortex-X1 CPU. For more information about this
processor, see [0].

[0] : https://www.arm.com/products/cortex-x

gcc/ChangeLog:

	* config/arm/arm-cpus.in: Add Cortex-X1 core.
	* config/arm/arm-tables.opt: Regenerate.
	* config/arm/arm-tune.md: Regenerate.
	* doc/invoke.texi: Update docs.
2020-09-29 22:32:00 +01:00
Przemyslaw Wirkus f836f3bc8f aarch64: add support for Cortex-X1
This adds support for the Arm Cortex-X1 CPU in AArch64 GCC. For more
information about this processor, see [0].

[0] : https://www.arm.com/products/cortex-x

gcc/ChangeLog:

	* config/aarch64/aarch64-cores.def: Add Cortex-X1 Arm core.
	* config/aarch64/aarch64-tune.md: Regenerate.
	* doc/invoke.texi: Add -mtune=cortex-x1 docs.
2020-09-29 22:32:01 +01:00
David Malcolm 9b4b1ed50f analyzer: silence -Wsign-compare warnings
gcc/analyzer/ChangeLog:
	* constraint-manager.cc
	(constraint_manager::add_constraint_internal): Whitespace fixes.
	Silence -Wsign-compare warning.
	* engine.cc (maybe_process_run_of_before_supernode_enodes):
	Silence -Wsign-compare warning.
2020-09-29 16:56:02 -04:00
Nathan Sidwell 7cbfe0894d c++: Hiddenness is a property of the symbol table
This patch moves the handling of decl-hiddenness entirely into the
name lookup machinery, where it belongs.  We need a few new flags,
because pressing the existing OVL_HIDDEN_P into play for non-function
decls doesn't work well.  For a local binding we only need one marker,
as there cannot be both a hidden implicit typedef and a hidden
function.  That's not true for namespace-scope, where they could both
be hidden.

The name-lookup machinery maintains the existing decl_hidden and co
flags, and asserts have been sprinkled around to make sure they are
consistent.  The next series of patches will remove those old markers.
(we'll need to keep one, as there are some special restrictions on
redeclaring friend functions with in-class definitions or default args.)

	gcc/cp/
	* cp-tree.h (ovl_insert): Change final parm to hidden-or-using
	indicator.
	* name-lookup.h (HIDDEN_TYPE_BINDING_P): New.
	(struct cxx_binding): Add type_is_hidden flag.
	* tree.c (ovl_insert): Change using_p parm to using_or_hidden,
	adjust.
	(ovl_skip_hidden): Assert we never see a naked hidden decl.
	* decl.c (xref_tag_1): Delete unhiding friend from here (moved to
	lookup_elaborated_type_1).
	* name-lookup.c (STAT_TYPE_HIDDEN_P, STAT_DECL_HIDDEN_P): New.
	(name_lookup::search_namespace_only): Check new hidden markers.
	(cxx_binding_make): Clear HIDDEN_TYPE_BINDING_P.
	(update_binding): Update new hidden markers.
	(lookup_name_1): Check HIDDEN_TYPE_BINDING_P and simplify friend
	ignoring.
	(lookup_elaborated_type_1): Use new hidden markers.  Reveal the
	decl here.
2020-09-29 12:13:08 -07:00
H.J. Lu dec881f85a x86: Replace <enqcmdntrin.h> with <enqcmdintrin.h>
Fix 2 typos in config/i386/enqcmdintrin.h by replacing <enqcmdntrin.h>
with <enqcmdintrin.h>:

[hjl@gnu-cfl-2 x86-gcc]$ echo "#include <enqcmdintrin.h>" | gcc -S -o /dev/null -x c -
In file included from <stdin>:1:
/usr/lib/gcc/x86_64-redhat-linux/10/include/enqcmdintrin.h:25:3: error: #error "Never use <enqcmdntrin.h> directly; include <x86intrin.h> instead."
   25 | # error "Never use <enqcmdntrin.h> directly; include <x86intrin.h> instead."
      |   ^~~~~
[hjl@gnu-cfl-2 x86-gcc]$

and _ENQCMDINTRIN_H_INCLUDED with _ENQCMDINTRIN_H_INCLUDED.

gcc/

	PR target/97247
	* config/i386/enqcmdintrin.h: Replace <enqcmdntrin.h> with
	<enqcmdintrin.h>.  Replace _ENQCMDNTRIN_H_INCLUDED with
	_ENQCMDINTRIN_H_INCLUDED.
2020-09-29 12:05:45 -07:00
Nathan Sidwell adcf8a11c7 c++: Name lookup simplifications
Here are a few cleanups, prior to landing the hidden decl changes.

1) Clear cxx_binding flags in the allocator, not at each user of the allocator.

2) Refactor update_binding.  The logic was getting too convoluted.

3) Set friendliness and anticipatedness before pushing a template decl (not after).

	gcc/cp/
	* name-lookup.c (create_local_binding): Do not clear
	INHERITED_VALUE_BINDING_P here.
	(name_lookup::process_binding): Move done hidden-decl triage to ...
	(name_lookup::search_namespace_only): ... here, its only caller.
	(cxx_binding_make): Clear flags here.
	(push_binding): Not here.
	(pop_local_binding): RAII.
	(update_binding): Refactor.
	(do_pushdecl): Assert we're never revealing a local binding.
	(do_pushdecl_with_scope): Directly call do_pushdecl.
	(get_class_binding): Do not clear LOCAL_BINDING_P here.
	* pt.c (push_template_decl): Set friend & anticipated before
	pushing.
2020-09-29 09:41:50 -07:00
David Edelsohn 74b5b8dec4 testsuite: Prevent spellcheck-inttypes failures on AIX.
AIX stdio.h implicitly includes sys/types.h, which implicitly includes
inttypes.h.  With a recent AIX header fixincludes change to unilaterally
define STDC Macros, the GCC testsuite uses of inttypes now fails.

This patch explicitly defines the _STD_TYPES_T macro when the test is
run on AIX so that the inttypes.h header behaves as the testcase requires.

gcc/testsuite/ChangeLog:

2020-09-29  David Edelsohn  <dje.gcc@gmail.com>

	* g++.dg/spellcheck-inttypes.C: Define _STD_TYPES_T on AIX.
	* gcc.dg/spellcheck-inttypes.c: Same.
2020-09-29 11:06:01 -04:00
Nathan Sidwell cc61827b55 c++: Identifier type value should not update binding
This simplification removes some unneeded behaviour in
set_identifier_type_value_with_scope, which was updating the namespace
binding.  And causing update_binding to have to deal with meeting two
implicit typedefs.  But the typedef is already there, and there's no
other way to have two such typedef's collide (we'll already have dealt
with that in lookup_elaborated_type).

So, let's kill this crufty code.

	gcc/cp/
	* name-lookup.c (update_binding): We never meet two implicit
	typedefs.
	(do_pushdecl): Adjust set_identifier_type_value_with_scope calls.
	(set_identifier_type_value_with_scope): Do not update binding in
	the namespace-case.  Assert it is already there.
2020-09-29 07:46:24 -07:00
Richard Biener 39a27bb01a tree-optimization/97241 - fix ICE in reduction vectorization
The following moves an ad-hoc attempt at discovering the SLP node
for a stmt to the place where we can find it in lock-step when
we find the stmt itself.

2020-09-29  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/97241
	* tree-vect-loop.c (vectorizable_reduction): Move finding
	the SLP node for the reduction stmt to a better place.

	* gcc.dg/vect/pr97241.c: New testcase.
2020-09-29 15:18:39 +02:00