Missing error-recovery code. While I was poking at this I also figured we
don't need to iterate over the members of a union.
* method.c (comp_info::~comp_info): Factor out of...
(build_comparison_op): Here. Handle error return from build_new_op.
From-SVN: r279235
Cases missed in r261813 "Update OpenACC data clause semantics to the 2.5
behavior".
libgomp/
* target.c (gomp_load_image_to_device, omp_target_associate_ptr):
Initialize 'dynamic_refcount' whenever we initialize 'refcount'.
Co-Authored-By: Julian Brown <julian@codesourcery.com>
From-SVN: r279230
Another place we need to look through the VIEW_CONVERT_EXPR we add to make a
use of a class NTTP have const type.
* pt.c (deducible_expression): Look through VIEW_CONVERT_EXPR.
From-SVN: r279228
2019-12-11 Lewis Hyatt <lhyatt@gmail.com>
PR 91853
* pretty-print.c (pp_quoted_string): Avoid hex-escaping valid
multibyte input. Fix off-by-one-bug printing the last byte before a
hex-escaped output.
(pp_character): Don't apply line wrapping in the middle of multibyte
characters.
(test_utf8): New test.
(pretty_print_c_tests): Call the new test.
From-SVN: r279226
When a CPU such as cortex-a55 is used with the soft-float ABI variant,
the compiler is incorrectly issuing a warning about a mismatch between
the architecture (generated internally) and the CPU. This is not
expected or intended.
The problem stems from the fact that we generate (correctly) an
architecture for a soft-float compilation, but then try to compare it
against the one recorded for the CPU. Normally we strip out the
floating point information before doing that comparison, but we
currently only do that for the features that can be affected by the
-mfpu option. For a soft-float environment we also need to strip out
any bits that depend on having floating-point present.
So this patch implements that and does a bit of housekeeping at the
same time:
- in arm-cpus.in it is not necessary for a CPU to specify both
+dotprod and +simd in its architecture specification, since +dotprod
implies +simd.
- I've refactored the ALL_SIMD fgroup in arm-cpus.in to create a new
subgroup ALL_SIMD_EXTERNAL and containing the bits that were
previously added directly to ALL_SIMD. Similarly, I've added an
ALL_FPU_EXTERNAL subgroup.
- in arm.c rename fpu_bitlist and all_fpubits to fpu_bitlist_internal
and all_fpubits_internal for consistency with the fgroup bits which
they contain.
* config/arm/arm-cpus.in (ALL_SIMD_EXTERNAL): New fgroup.
(ALL_SIMD): Use it.
(ALL_FPU_EXTERNAL): New fgroup.
(ALL_FP): Use it.
(cortex-a55, cortex-a75, cortex-a76, cortex-a76ae): Remove redundant
+simd from architecture specification.
(cortex-a77, neoverse-n1, cortex-a75.cortex-a55): Likewise.
* config/arm/arm.c (isa_all_fpubits, fpu_bitlist): Rename to ...
(isa_all_fpubits_internal, fpu_bitlist_internal): ... these.
(isa_all_fpbits): New bitmap.
(arm_option_override): Initialize it.
(arm_configure_build_target): If the target isa does not have any
FP enabled, do not warn about mismatches in FP-related feature bits.
From-SVN: r279219
The columns of the clause locations that are reported for C and C++ are
different and hence we need separate test expectations for both languages.
2019-12-11 Frederik Harwath <frederik@codesourcery.com>
PR other/92901
/gcc/testsuite/
* c-c++-common/clause-locations.c: Adjust test expectation for C++.
From-SVN: r279215
gcc/
PR target/92865
* config/i386/i386-expand.c (ix86_valid_mask_cmp_mode): Enable
integer mask cmov when available even with TARGET_XOP.
gcc/testsuite
* gcc.target/i386/pr92865-1.c: New test.
From-SVN: r279214
* include/pstl/glue_numeric_defs.h: Restore enable_if lost
during original import of pstl.
* include/pstl/glue_numeric_impl.h: Likewise.
From-SVN: r279212
When a type descriptor is needed (for e.g. interface conversion),
if the type is a pointer to a named type defined in another
package, we don't generate the definition of the type descriptor
because it is generated in the package where the type is defined.
However, if the named type is an alias to an unnamed type, its
descriptor is not generated in the other package, and we need to
generate it.
Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/210787
From-SVN: r279207
As discussed at https://github.com/cplusplus/draft/issues/3534 two
std::span constructors specify incorrect conditions for throwing
exceptions. This patch makes those constructors have correct
noexcept-specifiers that accurately reflect what can actually throw.
(span(ContiguousIterator, Sentinel)): Add conditional noexcept.
* include/std/span (span(ContiguousIterator, size_type)): Change
noexcept to be unconditionally true.
* testsuite/23_containers/span/nothrow_cons.cc: New test.
From-SVN: r279206
PR tree-optimization/92891
* builtins.c (gimple_call_alloc_size): Convert size to sizetype
before returning it.
* gcc.c-torture/compile/pr92891.c: New test.
From-SVN: r279205
2019-12-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/92796
* lra-int.h (lra_risky_transformations_p): Rename to
check_and_force_assignment_correctness_p.
* lra-assigns.c: Ditto.
(lra_assign): Reset check_and_force_assignment_correctness_p.
* lra-constraints.c (lra_risky_transformations_p): Rename to
check_and_force_assignment_correctness_p.
(lra_constraints): Set up check_and_force_assignment_correctness_p
only for the 1st sub-pass.
* lra-eliminations.c (process_insn_for_elimination): Set up
check_and_force_assignment_correctness_p if the insn chnaged its
code.
2019-12-10 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/92796
* gcc.target/powerpc/pr92796.c: New test.
From-SVN: r279204
2019-12-10 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91643
* trans-array.c (gfc_conv_array_parameter): Do not repack
an assumed rank dummy argument.
2019-12-10 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91643
* gfortran.dg/assumed_rank_18.f90: New test.
From-SVN: r279203
PR ipa/92883
* ipa-cp.c (propagate_vr_across_jump_function): Pass jvr rather
than *jfunc->m_vr to intersect. Formatting fix.
* gcc.dg/ipa/pr92883.c: New test.
From-SVN: r279194
PR middle-end/92825
* cfgexpand.c (add_stack_protection_conflicts): Change return type
from void to bool, return true if at least one stack_vars[i].decl
is addressable.
(record_or_union_type_has_array_p, stack_protect_decl_p): Remove.
(expand_used_vars): Don't call stack_protect_decl_p, instead for
-fstack-protector-strong set gen_stack_protect_signal to true
if add_stack_protection_conflicts returned true. Formatting fixes.
* doc/invoke.texi (-fstack-protector-strong): Clarify that optimized
out variables or variables not living on the stack don't count.
(-fstack-protector): Likewise. Clarify it affects >= 8 byte arrays
rather than > 8 byte.
* gcc.target/i386/pr92825.c: New test.
From-SVN: r279193
This testcase demonstrates that looking at cand->template_decl is not a good
starting place for finding the most general template, as it is only set for
primary templates.
* call.c (cand_parms_match): Handle all templated functions.
From-SVN: r279185
In my patch to implement C++20 "structural type" I tried to set the access
flags on the artificial base fields appropriately, but failed. I was
copying TREE_PRIVATE from the binfo, but TREE_PRIVATE on binfo is just a
temporary cache for dfs_access_in_type; we really need to get the
inheritance access information from BINFO_BASE_ACCESSES.
* class.c (build_base_field_1): Take access parameter.
(build_base_field): Likewise.
(build_base_fields, layout_virtual_bases): Pass it.
* tree.c (structural_type_p): Improve private base diagnostic.
From-SVN: r279184
A call as the immediate operand of decltype is handled differently; we don't
create an object of the return type as we do normally. But in the case of a
rewritten operator, we're adding another call as a wrapper, so the inner
call doesn't get the special handling.
* call.c (build_new_op_1): Clear tf_decltype on inner call.
From-SVN: r279183
2019-12-10 Martin Liska <mliska@suse.cz>
PR fortran/92874
* dependency.c (gfc_dep_compare_expr): Bail out
when one of the arguments is null.
2019-12-10 Martin Liska <mliska@suse.cz>
PR fortran/92874
* gfortran.dg/pr92874.f90: New test.
From-SVN: r279181
2019-12-10 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/92863
* misc.c (gfc_typename): If derived component is NULL for
derived or class, return "invalid type" or "invalid class",
respectively.
2019-12-10 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/92863
* gfortran.dg/interface_45.f90: New test.
From-SVN: r279180
* cgraph.c (cgraph_node::verify_node): Verify tp_first_run.
* cgraph.h (cgrpah_node): Turn tp_first_run back to int.
* cgraphunit.c (tp_first_run_node_cmp): Do not watch for overflows.
(expand_all_functions): First expand ordered section and then
unordered.
* profile.c (compute_value_histograms): Error on out of range
tp_first_runs.
From-SVN: r279179
* cgraph.c (cgraph_node::verify_node): Verify tp_first_run.
* cgraph.h (cgrpah_node): Turn tp_first_run back to int.
* cgraphunit.c (tp_first_run_node_cmp): Do not watch for overflows.
(expand_all_functions): First expand ordered section and then
unordered.
* lto-partition.c (lto_balanced_map): Fix printing of tp_first_run.
* profile.c (compute_value_histograms): Error on out of range
tp_first_runs.
From-SVN: r279178
With -msve-vector-bits=N, the payload of some partial SVE modes can
be 16 bytes or smaller, which makes them small enough to fit in a
pair of GPRs. We specifically don't want that, because the payload
is distributed evenly across the SVE register rather than collected
at one end. Marshalling it into a GPR via register operations would
be expensive.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't
allow SVE modes in GPRs.
gcc/testsuite/
* gcc.target/aarch64/sve/mixed_size_7.c: New test.
From-SVN: r279174
The INDEX patterns handle partial modes by choosing the container
size rather than the element size, so that the number of lanes
(and thus number of additions) matches the mode. This means that
all VNx4 modes use .s and all VNx2 modes use .d, etc.
When adding this, I'd forgotten that the choice between Wn and Xn
registers would need to be updated to use the container size too.
For partial VNx2s, we were using .d containers with Wn rather than
Xn source registers.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (vccore): New iterator.
* config/aarch64/aarch64-sve.md (vec_series<mode>): Use it instead
of vwcore.
(*vec_series<mode>_plus): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/mixed_size_6.c: New test.
From-SVN: r279173
The alias template wasn't working because it applied iter_reference_t to
the pack of iterators before and after passing the pack to the
__indeirect_result helper.
* include/bits/iterator_concepts.h (indirect_result_t): Do not apply
iter_reference_t to parameter pack.
* testsuite/24_iterators/indirect_callable/projected.cc: New test.
From-SVN: r279170
Check that the column information for OpenACC clauses is communicated correctly
to the middle-end, in particular by the Fortran front-end (cf. PR 92793).
2019-12-10 Frederik Harwath <frederik@codesourcery.com>
gcc/testsuite/
* c-c++-common/goacc/clause-locations.c: New test.
* gfortran.dg/goacc/clause-locations.f90: New test.
From-SVN: r279169
Since the Fortran front-end now sets the clause locations correctly, we can
emit warnings with more precise locations if we encounter conflicting
operations for a variable in reduction clauses.
2019-12-10 Frederik Harwath <frederik@codesourcery.com>
gcc/
* omp-low.c (scan_omp_for): Use clause location in warning.
From-SVN: r279168
The dwarf2 handling of vector constants currently divides the vector
into a length (number of elements) and byte element size. This doesn't
work well for MODE_VECTOR_BOOL, where several elements are packed into
the same byte.
We should probably add a way of encoding this in future, but for now
the safest thing is to punt, like we already do for variable-length
vectors.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* dwarf2out.c (loc_descriptor): Punt for MODE_VECTOR_BOOL.
(add_const_value_attribute): Likewise.
gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/debug_4.c: New test.
From-SVN: r279165
The direct_slp_reduc code in vect_create_epilog_for_reduction was
still assuming that all types involved in a reduction are the same
(up to types_compatible_p), whereas we now support differences in
sign. This was causing an ICE in gcc.dg/vect/pr92324-4.c for SVE.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* tree-vect-loop.c (vect_create_epilog_for_reduction): When
handling direct_slp_reduc, allow the PHI arguments to have
a different type from the vector elements.
From-SVN: r279164
