2017-02-16 Alan Modra <amodra@gmail.com>
PR rtl-optimization/79286
* ira.c (def_dominates_uses): New function.
(update_equiv_regs): Don't create an equivalence for insns that
may trap where the register def does not dominate the use.
* gcc.c-torture/execute/pr79286.c: New.
From-SVN: r245521
* pt.c (apply_late_template_attributes): Do apply non-dependent
attributes to types.
Co-Authored-By: Jason Merrill <jason@redhat.com>
From-SVN: r245516
2017-02-16 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/78127
* lra.c (lra): Call lra_eliminate before finish the loop after
lra_constraint.
From-SVN: r245514
PR libstdc++/60936
* src/c++11/snprintf_lite.cc (__concat_size_t): Calculate length
written to buffer, not length remaining in buffer.
From-SVN: r245505
PR c++/79512
c/
* c-parser.c (c_parser_omp_target): For -fopenmp-simd
ignore #pragma omp target even when not followed by identifier.
cp/
* parser.c (cp_parser_omp_target): For -fopenmp-simd
ignore #pragma omp target even when not followed by identifier.
testsuite/
* c-c++-common/gomp/pr79512.c: New test.
From-SVN: r245504
2017-02-16 Richard Biener <rguenther@suse.de>
* graphite.h: Do not include isl/isl_val_gmp.h, instead include
isl/isl_val.h.
* graphite-isl-ast-to-gimple.c (gmp_cst_to_tree): Remove.
(gcc_expression_from_isl_expr_int): Use generic isl_val interface.
* graphite-sese-to-poly.c: Do not include isl/isl_val_gmp.h.
(isl_val_int_from_wi): New function.
(extract_affine_gmp): Rename to ...
(extract_affine_wi): ... this, take a widest_int.
(extract_affine_int): Just wrap extract_affine_wi.
(add_param_constraints): Use isl_val_int_from_wi.
(add_loop_constraints): Likewise, and extract_affine_wi.
From-SVN: r245501
* class.c (build_clone): Also omit parms from TYPE_ARG_TYPES.
(adjust_clone_args): Adjust.
(add_method): Remember omitted parms.
* call.c (add_function_candidate): Likewise.
* mangle.c (write_method_parms): Likewise.
* method.c (ctor_omit_inherited_parms): Return false if there are no
parms to omit.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r245495
PR c++/79301
* parser.c (cp_parser_std_attribute): Don't pedwarn about
[[deprecated]] with -std=c++11 and [[fallthrough]] with
-std=c++11 and -std=c++14.
* g++.dg/cpp1y/feat-cxx11-neg.C: Remove (with pedwarn) from
[[deprecated]] comment.
* g++.dg/cpp1y/feat-cxx98-neg.C: Likewise.
* g++.dg/cpp1y/feat-cxx11.C: Likewise.
* g++.dg/cpp1y/attr-deprecated-neg.C: Don't expect warnings for
[[deprecated]] in -std=c++11.
* g++.dg/cpp0x/fallthrough2.C: Don't expect warnings for
[[fallthrough]] in -std=c++11 and -std=c++14.
From-SVN: r245489
PR c++/79288
* decl.c (grokdeclarator): For static data members, handle thread_p
only after handling inline.
* g++.dg/tls/pr79288.C: New test.
From-SVN: r245488
2017-02-14 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-cores.def (thunderx2t99): Move to under 'C"
cores and change the partno/implementer to be correct.
(thunderx2t99p1): New core which replaces thunderx2t99 and still has
the 'B" as the implementer.
* config/aarch64/aarch64-tune.md: Regenerate.
From-SVN: r245461
gcc/ChangeLog:
2017-02-14 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000.c: Add case statement entry to make the
xvcvuxdsp built-in argument unsigned.
* config/rs6000/vsx.md: Fix the source and return operand types so they
match the instruction definitions from the ISA document. Fix typo
in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
statement.
gcc/testsuite/ChangeLog:
2017-01-14 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
xvcvsxdsp and xvcvuxdsp instructions.
From-SVN: r245460
2017-02-14 Vladimir Makarov <vmakarov@redhat.com>
PR target/79282
* lra-int.h (struct lra_operand_data, struct lra_insn_reg): Add
member early_clobber_alts.
* lra-lives.c (reg_early_clobber_p): New.
(process_bb_lives): Use it.
* lra.c (new_insn_reg): New arg early_clobber_alts. Use it.
(debug_operand_data): Initialize early_clobber_alts.
(setup_operand_alternative): Set up early_clobber_alts.
(collect_non_operand_hard_regs): Ditto. Pass early clobber
alternatives to new_insn_reg.
(add_regs_to_insn_regno_info): Add arg early_clobber_alts. Use
it.
(lra_update_insn_regno_info): Pass the new arg.
From-SVN: r245459
David found the vec-adde{,c}-int128.c testcases fail on AIX. Those
tests should only run on targets that have int128.
This also changes the non-int128 testcases to check for the hardware
they require.
gcc/testsuite/
* gcc.target/powerpc/vec-adde-int128.c: Only run if int128 exists.
* gcc.target/powerpc/vec-addec-int128.c: Ditto.
* gcc.target/powerpc/vec-adde.c: Require vsx_hw, don't require a
64-bit default target.
* gcc.target/powerpc/vec-addec.c: Require p8vector_hw, don't require
a 64-bit default target.
From-SVN: r245453
When converting TI store with CONST_INT to V1TI store with CONST_VECTOR
in large model, an extra instruction may be needed to load CONST_VECTOR
into a register. Insert the extra instruction to the right place.
gcc/
PR target/79498
* config/i386/i386.c (timode_scalar_chain::convert_insn): Insert
the extra instruction to the right place to store 128-bit constant
when needed.
gcc/testsuite/
PR target/79498
* gcc.target/i386/pr79498.c: New test.
From-SVN: r245438
power, power2, rios, rios1, rios2, rsc, rsc2 support was removed.
rs64a never was a supported option; it's spelled rs64.
power5+ and powerpc64le are supported options but could not be set as
default.
* config.gcc (supported_defaults) [powerpc*-*-*]: Update.
From-SVN: r245435
PR tree-optimization/79095
* tree-vrp.c (extract_range_from_binary_expr_1): For EXACT_DIV_EXPR,
if the numerator has the range ~[0,0] make the resultant range ~[0,0].
(extract_range_from_binary_expr): For MINUS_EXPR with no derived range,
if the operands are known to be not equal, then the resulting range
is ~[0,0].
(intersect_ranges): If the new range is ~[0,0] and the old range is
wide, then prefer ~[0,0].
* tree-vrp.c (overflow_comparison_p_1): New function.
(overflow_comparison_p): New function.
* tree-vrp.c (register_edge_assert_for_2): Register additional asserts
if NAME is used in an overflow test.
(vrp_evaluate_conditional_warnv_with_ops): If the ops represent an
overflow check that can be expressed as an equality test, then adjust
ops to be that equality test.
PR tree-optimization/79095
* g++.dg/pr79095-1.C: New test
* g++.dg/pr79095-2.C: New test
* g++.dg/pr79095-3.C: New test
* g++.dg/pr79095-4.C: New test
* g++.dg/pr79095-5.C: New test
* gcc.c-torture/execute/arith-1.c: Update with more cases.
* gcc.dg/tree-ssa/pr79095-1.c: New test.
From-SVN: r245434
