3b31f72096
Fix gcc.dg/tree-ssa/builtin-sprintf-warn-4.c
...
gcc/testsuite/ChangeLog
PR preprocessor/77672
* gcc.dg/tree-ssa/builtin-sprintf-warn-4.c (test): Update
expected multiline output from first warning to reflect change
in r240434.
From-SVN: r240442
2016-09-23 16:55:27 +00:00
592459bf6b
builtin-sprintf-warn-2.c: Fix xfail pattern.
...
2016-09-23 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/testsuite/
* gcc.dg/tree-ssa/builtin-sprintf-warn-2.c: Fix xfail pattern.
From-SVN: r240441
2016-09-23 16:06:57 +00:00
b571e48048
Fix incorrect file in ChangeLog on previous commit
...
gcc/
* tree-ssa-loop-prefetch.c (issue_prefetch_ref): Add call
to duplicate_ssa_name_ptr_info.
From-SVN: r240440
2016-09-23 15:51:54 +00:00
ed481942e3
Ensure points-to information is maintained for prefetch.
...
gcc/
PR tree-optimization/77654
* tree-ssa-alias.c (issue_prefetch_ref): Add call
to duplicate_ssa_name_ptr_info.
From-SVN: r240439
2016-09-23 15:48:01 +00:00
0af06385d3
re PR testsuite/77411 (object-size-9.c -fpic -m32 failure)
...
2016-09-23 Bernd Edlinger <bernd.edlinger@hotmail.de>
Tom de Vries <tom@codesourcery.com>
PR testsuite/77411
* c-c++-common/ubsan/object-size-9.c: Call __builtin_exit in C++.
Co-Authored-By: Tom de Vries <tom@codesourcery.com>
From-SVN: r240437
2016-09-23 14:43:45 +00:00
8f01b67af5
atomic-12.c: Skip for C++1z.
...
* c-c++-common/gomp/atomic-12.c: Skip for C++1z.
* c-c++-common/gomp/atomic-13.c: Likewise.
* c-c++-common/gomp/atomic-14.c: Likewise.
* c-c++-common/pr60439.c: Remove invalid code.
* g++.dg/expr/bitfield4.C: Robustify for C++1z.
* g++.dg/expr/bitfield5.C: Likewise.
* g++.dg/expr/bitfield6.C: Likewise.
* g++.dg/expr/bool1.C: Likewise.
* g++.dg/expr/bool3.C: Likewise.
* g++.dg/expr/lval3.C: Likewise.
* g++.dg/expr/lval4.C: Likewise.
* g++.old-deja/g++.jason/bool5.C: Likewise.
From-SVN: r240436
2016-09-23 14:40:16 +00:00
7be8d66369
* configure.ac: Define HAVE_MEMALIGN for newlib.
...
From-SVN: r240435
2016-09-23 10:34:51 -04:00
bbd6fcf320
Provide location information for terminator characters (PR preprocessor/77672)
...
substring_loc::get_location currently fails for the final terminator
character in a STRING_CST from the C frontend, so that format_warning_va
falls back to using the location of the string as a whole.
This patch tweaks things [1] so that we use the final closing quote
as the location of the terminator character, as requested in
PR preprocessor/77672.
[1] specifically, cpp_interpret_string_1.
gcc/ChangeLog:
PR preprocessor/77672
* input.c (selftest::test_lexer_string_locations_simple): Update
test to expect location information of the terminator character
at the location of the final closing quote.
(selftest::test_lexer_string_locations_hex): Likewise.
(selftest::test_lexer_string_locations_oct): Likewise.
(selftest::test_lexer_string_locations_letter_escape_1): Likewise.
(selftest::test_lexer_string_locations_letter_escape_2): Likewise.
(selftest::test_lexer_string_locations_ucn4): Likewise.
(selftest::test_lexer_string_locations_ucn8): Likewise.
(selftest::test_lexer_string_locations_u8): Likewise.
(selftest::test_lexer_string_locations_utf8_source): Likewise.
(selftest::test_lexer_string_locations_concatenation_1): Likewise.
(selftest::test_lexer_string_locations_concatenation_2): Likewise.
(selftest::test_lexer_string_locations_concatenation_3): Likewise.
(selftest::test_lexer_string_locations_macro): Likewise.
(selftest::test_lexer_string_locations_long_line): Likewise.
gcc/testsuite/ChangeLog:
PR preprocessor/77672
* gcc.dg/plugin/diagnostic-test-string-literals-1.c
(test_terminator_location): New function.
libcpp/ChangeLog:
PR preprocessor/77672
* charset.c (cpp_interpret_string_1): Add a source_range for the
NUL-terminator, using the location of the trailing quote of the
final string.
From-SVN: r240434
2016-09-23 14:14:52 +00:00
30faeb0f99
Really commit testcase intended for r240230.
...
2016-09-23 Fritz Reese <fritzoreese@gmail.com>
Really commit testcase intended for r240230.
* gcc/testsuite/gfortran.dg/dec_structure_15.f90: Really commit.
From-SVN: r240433
2016-09-23 13:31:37 +00:00
113d06a486
tree-ssa-sccvn.c (visit_reference_op_call): Value number virtual definition to virtual use if...
...
2016-09-23 Richard Biener <rguenther@suse.de>
* tree-ssa-sccvn.c (visit_reference_op_call): Value number
virtual definition to virtual use if the call devirtualizes
to a const or pure function.
(visit_use): Also visit calls we can devirtualize to a
const or pure function.
* gcc.dg/tree-ssa/ssa-fre-56.c: New testcase.
From-SVN: r240431
2016-09-23 12:39:05 +00:00
26bedff5fd
re PR tree-optimization/77697 (suspicious code in tree-ssa-forwprop.c)
...
2016-09-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/77697
* tree-ssa-forwprop.c (defcodefor_name): Remove bogus code,
signal error if we have sth ternary or unhandled.
From-SVN: r240430
2016-09-23 12:37:22 +00:00
643e08545f
Revert bogus dg-extract-results.sh change
...
* dg-extract-results.sh: Revert bogus change.
From-SVN: r240429
2016-09-23 11:35:34 +00:00
cab9e1df4d
[PATCH 17/17][ARM] Add tests for NEON FP16 ACLE intrinsics.
...
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/advsimd-intrinsics/advsimd-intrinsics.exp: Enable
-march=armv8.2-a+fp16 when supported by the hardware.
* gcc.target/aarch64/advsimd-intrinsics/binary_op_float.inc: New.
* gcc.target/aarch64/advsimd-intrinsics/binary_op_no64.inc:
Add F16 tests, enabled if macro HAS_FLOAT16_VARIANT is defined. Add
semi-colons to a macro invocations.
* gcc.target/aarch64/advsimd-intrinsics/cmp_fp_op.inc: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/cmp_op.inc: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/cmp_zero_op.inc: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabd.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vabs.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vadd.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcage.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcagt.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcale.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcalt.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vceq.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcge.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vcgez_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcgt.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vcgtz_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcle.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vclez_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vclt.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vcltz_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vcvt.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined. Also fix some white-space.
* gcc.target/aarch64/advsimd-intrinsics/vcvtX.inc: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvta_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtm_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtp_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfma.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined. Also fix some long lines and white-space.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vfms.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined. Also fix some long lines and white-space.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmax.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vmaxnm_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmin.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vminnm_1.c: New.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul.c: Add F16
tests, enabled if macro __ARM_FEATURE_FP16_VECTOR_ARITHMETIC is
defined.
* gcc.target/aarch64/advsimd-intrinsics/vmul_lane.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vmul_n.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vneg.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vpXXX.inc: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpadd.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmax.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vpmin.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecpe.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrecps.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnd.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrte.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrsqrts.c: Likewise.
* gcc.target/gcc.target/aarch64/advsimd-intrinsics/vsub.c:
Likewise.
From-SVN: r240427
2016-09-23 10:57:20 +00:00
da9b2e696a
[PATCH 16/17][ARM] Add tests for VFP FP16 ACLE instrinsics.
...
testsuite/
2016-09-23 Jiong Wang <jiong.wang@arm.com>
Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New.
* gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New.
* gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New.
* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.
Co-Authored-By: Matthew Wahab <matthew.wahab@arm.com>
From-SVN: r240426
2016-09-23 10:54:14 +00:00
785cf02f68
[PATCH 15/17][ARM] Add tests for ARMv8.2-A FP16 support.
...
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-neon-1.c: New.
* gcc.target/arm/armv8_2-fp16-scalar-1.c: New.
* gcc.target/arm/armv8_2-fp16-scalar-2.c: New.
* gcc.target/arm/attr-fp16-arith-1.c: Add a test of intrinsics
support.
From-SVN: r240425
2016-09-23 10:48:47 +00:00
de955a690b
[PATCH 14/17][ARM] Add NEON FP16 instrinsics.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm_neon.h (vabd_f16): New.
(vabdq_f16): New.
(vabs_f16): New.
(vabsq_f16): New.
(vadd_f16): New.
(vaddq_f16): New.
(vcage_f16): New.
(vcageq_f16): New.
(vcagt_f16): New.
(vcagtq_f16): New.
(vcale_f16): New.
(vcaleq_f16): New.
(vcalt_f16): New.
(vcaltq_f16): New.
(vceq_f16): New.
(vceqq_f16): New.
(vceqz_f16): New.
(vceqzq_f16): New.
(vcge_f16): New.
(vcgeq_f16): New.
(vcgez_f16): New.
(vcgezq_f16): New.
(vcgt_f16): New.
(vcgtq_f16): New.
(vcgtz_f16): New.
(vcgtzq_f16): New.
(vcle_f16): New.
(vcleq_f16): New.
(vclez_f16): New.
(vclezq_f16): New.
(vclt_f16): New.
(vcltq_f16): New.
(vcltz_f16): New.
(vcltzq_f16): New.
(vcvt_f16_s16): New.
(vcvt_f16_u16): New.
(vcvt_s16_f16): New.
(vcvt_u16_f16): New.
(vcvtq_f16_s16): New.
(vcvtq_f16_u16): New.
(vcvtq_s16_f16): New.
(vcvtq_u16_f16): New.
(vcvta_s16_f16): New.
(vcvta_u16_f16): New.
(vcvtaq_s16_f16): New.
(vcvtaq_u16_f16): New.
(vcvtm_s16_f16): New.
(vcvtm_u16_f16): New.
(vcvtmq_s16_f16): New.
(vcvtmq_u16_f16): New.
(vcvtn_s16_f16): New.
(vcvtn_u16_f16): New.
(vcvtnq_s16_f16): New.
(vcvtnq_u16_f16): New.
(vcvtp_s16_f16): New.
(vcvtp_u16_f16): New.
(vcvtpq_s16_f16): New.
(vcvtpq_u16_f16): New.
(vcvt_n_f16_s16): New.
(vcvt_n_f16_u16): New.
(vcvtq_n_f16_s16): New.
(vcvtq_n_f16_u16): New.
(vcvt_n_s16_f16): New.
(vcvt_n_u16_f16): New.
(vcvtq_n_s16_f16): New.
(vcvtq_n_u16_f16): New.
(vfma_f16): New.
(vfmaq_f16): New.
(vfms_f16): New.
(vfmsq_f16): New.
(vmax_f16): New.
(vmaxq_f16): New.
(vmaxnm_f16): New.
(vmaxnmq_f16): New.
(vmin_f16): New.
(vminq_f16): New.
(vminnm_f16): New.
(vminnmq_f16): New.
(vmul_f16): New.
(vmul_lane_f16): New.
(vmul_n_f16): New.
(vmulq_f16): New.
(vmulq_lane_f16): New.
(vmulq_n_f16): New.
(vneg_f16): New.
(vnegq_f16): New.
(vpadd_f16): New.
(vpmax_f16): New.
(vpmin_f16): New.
(vrecpe_f16): New.
(vrecpeq_f16): New.
(vrnd_f16): New.
(vrndq_f16): New.
(vrnda_f16): New.
(vrndaq_f16): New.
(vrndm_f16): New.
(vrndmq_f16): New.
(vrndn_f16): New.
(vrndnq_f16): New.
(vrndp_f16): New.
(vrndpq_f16): New.
(vrndx_f16): New.
(vrndxq_f16): New.
(vrsqrte_f16): New.
(vrsqrteq_f16): New.
(vrecps_f16): New.
(vrecpsq_f16): New.
(vrsqrts_f16): New.
(vrsqrtsq_f16): New.
(vsub_f16): New.
(vsubq_f16): New.
From-SVN: r240424
2016-09-23 10:46:26 +00:00
29c3d574af
[PATCH 13/17][ARM] Add VFP FP16 instrinsics.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config.gcc (extra_headers): Add arm_fp16.h
* config/arm/arm_fp16.h: New.
* config/arm/arm_neon.h: Include "arm_fp16.h".
From-SVN: r240423
2016-09-23 10:41:04 +00:00
0768b127e5
[PATCH 12/17][ARM] Add builtins for NEON FP16 intrinsics.
...
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm_neon_builtins.def (vadd): New (v8hf, v4hf
variants).
(vmulf): New (v8hf, v4hf variants).
(vfma): New (v8hf, v4hf variants).
(vfms): New (v8hf, v4hf variants).
(vsub): New (v8hf, v4hf variants).
(vcage): New (v8hf, v4hf variants).
(vcagt): New (v8hf, v4hf variants).
(vcale): New (v8hf, v4hf variants).
(vcalt): New (v8hf, v4hf variants).
(vceq): New (v8hf, v4hf variants).
(vcgt): New (v8hf, v4hf variants).
(vcge): New (v8hf, v4hf variants).
(vcle): New (v8hf, v4hf variants).
(vclt): New (v8hf, v4hf variants).
(vceqz): New (v8hf, v4hf variants).
(vcgez): New (v8hf, v4hf variants).
(vcgtz): New (v8hf, v4hf variants).
(vcltz): New (v8hf, v4hf variants).
(vclez): New (v8hf, v4hf variants).
(vabd): New (v8hf, v4hf variants).
(vmaxf): New (v8hf, v4hf variants).
(vmaxnm): New (v8hf, v4hf variants).
(vminf): New (v8hf, v4hf variants).
(vminnm): New (v8hf, v4hf variants).
(vpmaxf): New (v4hf variant).
(vpminf): New (v4hf variant).
(vpadd): New (v4hf variant).
(vrecps): New (v8hf, v4hf variants).
(vrsqrts): New (v8hf, v4hf variants).
(vabs): New (v8hf, v4hf variants).
(vneg): New (v8hf, v4hf variants).
(vrecpe): New (v8hf, v4hf variants).
(vrnd): New (v8hf, v4hf variants).
(vrnda): New (v8hf, v4hf variants).
(vrndm): New (v8hf, v4hf variants).
(vrndn): New (v8hf, v4hf variants).
(vrndp): New (v8hf, v4hf variants).
(vrndx): New (v8hf, v4hf variants).
(vrsqrte): New (v8hf, v4hf variants).
(vmul_lane): Add v4hf and v8hf variants.
(vmul_n): Add v4hf and v8hf variants.
(vext): New (v8hf, v4hf variants).
(vcvts): New (v8hi, v4hi variants).
(vcvts): New (v8hf, v4hf variants).
(vcvtu): New (v8hi, v4hi variants).
(vcvtu): New (v8hf, v4hf variants).
(vcvts_n): New (v8hf, v4hf variants).
(vcvtu_n): New (v8hi, v4hi variants).
(vcvts_n): New (v8hi, v4hi variants).
(vcvtu_n): New (v8hf, v4hf variants).
(vbsl): New (v8hf, v4hf variants).
(vcvtas): New (v8hf, v4hf variants).
(vcvtau): New (v8hf, v4hf variants).
(vcvtms): New (v8hf, v4hf variants).
(vcvtmu): New (v8hf, v4hf variants).
(vcvtns): New (v8hf, v4hf variants).
(vcvtnu): New (v8hf, v4hf variants).
(vcvtps): New (v8hf, v4hf variants).
(vcvtpu): New (v8hf, v4hf variants).
From-SVN: r240422
2016-09-23 10:34:57 +00:00
66e31c3d9b
[PATCH 11/17][ARM] Add builtins for VFP FP16 intrinsics.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm-builtins.c (hf_UP): New.
(si_UP): New.
(vfp_builtin_data): New. Update comment.
(enum arm_builtins): Include "arm_vfp_builtins.def".
(ARM_BUILTIN_VFP_PATTERN_START): New.
(arm_init_vfp_builtins): New.
(arm_init_builtins): Add arm_init_vfp_builtins.
(arm_expand_vfp_builtin): New.
(arm_expand_builtins): Update for arm_expand_vfp_builtin. Fix
long line.
* config/arm/arm_vfp_builtins.def: New file.
* config/arm/t-arm (arm.o): Add arm_vfp_builtins.def.
(arm-builtins.o): Likewise.
From-SVN: r240421
2016-09-23 10:28:44 +00:00
1e40134071
Drop TREE_OVERFLOW
...
gcc/ChangeLog:
2016-09-23 Kugan Vivekanandarajah <kuganv@linaro.org>
PR ipa/77677
* ipa-cp.c (propagate_vr_accross_jump_function): Drop TREE_OVERFLOW
from constant while creating value range.
gcc/testsuite/ChangeLog:
2016-09-23 Kugan Vivekanandarajah <kuganv@linaro.org>
PR ipa/77677
* gcc.dg/torture/pr77677.c: New test.
From-SVN: r240420
2016-09-23 10:25:09 +00:00
8ed3eeac20
trans-intrinsic.c (gfc_conv_intrinsic_caf_get): Use the old caf- interface where possible.
...
gcc/fortran/ChangeLog:
2016-09-23 Andre Vehreschild <vehre@gcc.gnu.org>
* trans-intrinsic.c (gfc_conv_intrinsic_caf_get): Use the old caf-
interface where possible.
gcc/testsuite/ChangeLog:
2016-09-23 Andre Vehreschild <vehre@gcc.gnu.org>
* gfortran.dg/coarray_lib_comm_1.f90: Using the old caf-interface
here now.
From-SVN: r240419
2016-09-23 12:17:22 +02:00
23427d518b
[PATCH][IRA]Initialize ira_use_lra_p early by moving the initialization into
...
ira_init_once ().
ira_use_lra_p previously will be used unintialized in backend_init_target ().
gcc/
2016-09-23 Renlin Li <renlin.li@arm.com>
* ira.c (ira): Move ira_use_lra_p initialization code to ...
(ira_init_once): Here.
From-SVN: r240418
2016-09-23 10:16:22 +00:00
bf0728547a
hooks.h (hook_uint_uintp_false): Rename to...
...
* hooks.h (hook_uint_uintp_false): Rename to...
(hook_bool_uint_uintp_false): ... this.
* hooks.c (hook_uint_uintp_false): Rename to...
(hook_bool_uint_uintp_false): ... this.
* target.def (elf_flags_numeric): Use hook_bool_uint_uintp_false
instead of hook_uint_uintp_false.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r240417
2016-09-23 12:05:29 +02:00
bce2b8f958
[PATCH 10/17][ARM] Refactor support code for NEON builtins.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm-builtins.c (arm_init_neon_builtin): New.
(arm_init_builtins): Move body of a loop to the standalone
function arm_init_neon_builtin.
(arm_expand_neon_builtin_1): New. Update comment. Function body
moved from arm_neon_builtin with some white-space fixes.
(arm_expand_neon_builtin): Move code into the standalone function
arm_expand_neon_builtin_1.
From-SVN: r240416
2016-09-23 09:59:55 +00:00
55a9b91ba8
[PATCH 9/17][ARM] Add NEON FP16 arithmetic instructions.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (VCVTHI): New.
(NEON_VCMP): Add UNSPEC_VCLT and UNSPEC_VCLE. Fix a long line.
(NEON_VAGLTE): New.
(VFM_LANE_AS): New.
(VH_CVTTO): New.
(V_reg): Add HF, V4HF and V8HF. Fix white-space.
(V_HALF): Add V4HF. Fix white-space.
(V_if_elem): Add HF, V4HF and V8HF. Fix white-space.
(V_s_elem): Likewise.
(V_sz_elem): Fix white-space.
(V_elem_ch): Likewise.
(VH_elem_ch): New.
(scalar_mul_constraint): Add V8HF and V4HF.
(Is_float_mode): Fix white-space.
(Is_d_reg): Add V4HF and V8HF. Fix white-space.
(q): Add HF. Fix white-space.
(float_sup): New.
(float_SUP): New.
(cmp_op_unsp): Add UNSPEC_VCALE and UNSPEC_VCALT.
(neon_vfm_lane_as): New.
* config/arm/neon.md (add<mode>3_fp16): New.
(sub<mode>3_fp16): New.
(mul<mode>3add<mode>_neon): New.
(fma<VH:mode>4_intrinsic): New.
(fmsub<VCVTF:mode>4_intrinsic): Fix white-space.
(fmsub<VH:mode>4_intrinsic): New.
(<absneg_str><mode>2): New.
(neon_v<absneg_str><mode>): New.
(neon_v<fp16_rnd_str><mode>): New.
(neon_vrsqrte<mode>): New.
(neon_vpaddv4hf): New.
(neon_vadd<mode>): New.
(neon_vsub<mode>): New.
(neon_vmulf<mode>): New.
(neon_vfma<VH:mode>): New.
(neon_vfms<VH:mode>): New.
(neon_vc<cmp_op><mode>): New.
(neon_vc<cmp_op><mode>_fp16insn): New
(neon_vc<cmp_op_unsp><mode>_fp16insn_unspec): New.
(neon_vca<cmp_op><mode>): New.
(neon_vca<cmp_op><mode>_fp16insn): New.
(neon_vca<cmp_op_unsp><mode>_fp16insn_unspec): New.
(neon_vc<cmp_op>z<mode>): New.
(neon_vabd<mode>): New.
(neon_v<maxmin>f<mode>): New.
(neon_vp<maxmin>fv4hf: New.
(neon_<fmaxmin_op><mode>): New.
(neon_vrecps<mode>): New.
(neon_vrsqrts<mode>): New.
(neon_vrecpe<mode>): New (VH variant).
(neon_vdup_lane<mode>_internal): New.
(neon_vdup_lane<mode>): New.
(neon_vcvt<sup><mode>): New (VCVTHI variant).
(neon_vcvt<sup><mode>): New (VH variant).
(neon_vcvt<sup>_n<mode>): New (VH variant).
(neon_vcvt<sup>_n<mode>): New (VCVTHI variant).
(neon_vcvt<vcvth_op><sup><mode>): New.
(neon_vmul_lane<mode>): New.
(neon_vmul_n<mode>): New.
* config/arm/unspecs.md (UNSPEC_VCALE): New
(UNSPEC_VCALT): New.
(UNSPEC_VFMA_LANE): New.
(UNSPECS_VFMS_LANE): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: Use arm_v8_2a_fp16_neon
options. Add tests for float16x4_t and float16x8_t.
From-SVN: r240415
2016-09-23 09:54:44 +00:00
64c744b962
S/390: Improved risbg usage.
...
gcc/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/s390.md ("*extzv<mode>_zEC12", "*extzv<mode>_z10")
("*extzv<mode><clobbercc_or_nocc>"):
Correct a typo in a comment.
Merged patterns.
("*insv<mode>_zEC12", "*insv<mode>_z10")
("*insv<mode><clobbercc_or_nocc>"): Ditto.
("*insv<mode>_zEC12_appendbitsleft")
("*insv<mode><clobbercc_or_nocc>_appendbitsleft")
("*insv<mode>_z10_appendbitsleft"): Ditto.
("*insv<mode>_zEC12_noshift", "*insv<mode>_z10_noshift")
("*insv<mode><clobbercc_or_nocc>_noshift"): Ditto.
Provide pattern with operands switched.
("*pre_z10_extv<mode>"):
Use new subst patterns.
("*extzvdi<clobbercc_or_nocc>_lshiftrt", "*<risbg_n>_ior_and_sr_ze")
("*extvsidi<clobbercc_or_nocc>", "*<risbg_n>_and_subregdi_rotr")
("*<risbg_n>_and_subregdi_rotl", "*<risbg_n>_di_and_rot")
("*insv_z10_noshift_cc", "*insv_z10_noshift_cconly")
("*<risbg_n>_<mode>_ior_and_lshiftrt")
("*<risbg_n>_sidi_ior_and_lshiftrt")
("*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"):
New patterns.
("*extzv_<mode>_sll", "*extzv_<mode>_srl")
("*extzv_<mode>_srl<clobbercc_or_nocc>")
("*extzv_<mode>_sll<clobbercc_or_nocc>"): Renamed patterns, use risbgn
on zEC12.
("SINT"): New mode_iterator with SI, HI, QI.
* config/s390/subst.md ("clobbercc_or_nocc_subst", "z10_or_zEC12_cond")
("clobbercc_or_nocc", "risbg_n"): New constructs for risbg pattern
duplication.
gcc/testsuite/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gcc.target/s390/risbg-ll-1.c: Ported risbg tests from llvm.
* gcc.target/s390/risbg-ll-2.c: Ditto.
* gcc.target/s390/risbg-ll-3.c: Ditto.
From-SVN: r240414
2016-09-23 09:53:29 +00:00
c2586c82cd
S/390: Enable wraparound in s390_contiguous_bitmask_p.
...
gcc/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/predicates.md ("contiguous_bitmask_operand"): Adapt to new
interface of s390_contiguous_bitmask_p.
("contiguous_bitmask_nowrap_operand"): New predicate.
* ("*anddi3_cc", "*anddi3_cconly", "*anddi3"): Replace NxxDq with NxxDw.
* config/s390/constraints.md ("NxxDw", "NxxSq"): Adapt to new interface
of s390_contiguous_bitmask_p.
* ("NxxDw"): Rename NxxDq constraint to NxxDw.
("NxxSw"): New constraint.
* config/s390/s390.md ("*andsi3_zarch"): Enable bitmask wraparound.
* config/s390/s390-protos.h (s390_contiguous_bitmask_p): Updated
interface.
(s390_contiguous_bitmask_nowrap_p): Export.
* config/s390/s390.c (s390_contiguous_bitmask_nowrap_p): New name of
former s390_contiguous_bitmask_p.
(s390_contiguous_bitmask_p): Use s390_contiguous_bitmask_nowrap_p to
detect contiguous bit ranges with wraparound. Change signature to
return START and END position instead of POS and LENGTH.
(s390_contiguous_bitmask_vector_p): Remove extra code for continous bit
ranges with wraparound.
(s390_extzv_shift_ok): Use s390_contiguous_bitmask_nowrap_p.
(s390_contiguous_bitmask_vector_p,s390_extzv_shift_ok,print_operand):
Adapt to new signature of s390_contiguous_bitmask_p.
From-SVN: r240413
2016-09-23 09:49:58 +00:00
822f18cd92
tree-vect-loop-manip.c (create_intersect_range_checks_index): New.
...
* tree-vect-loop-manip.c (create_intersect_range_checks_index): New.
(create_intersect_range_checks): New.
(vect_create_cond_for_alias_checks): Call above function.
From-SVN: r240412
2016-09-23 09:47:52 +00:00
d403b8d4e8
[PATCH 8/17][ARM] Add VFP FP16 arithmetic instructions.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (Code iterators): Fix some white-space
in the comments.
(GLTE): New.
(ABSNEG): New
(FCVT): Moved from vfp.md.
(VCVT_HF_US_N): New.
(VCVT_SI_US_N): New.
(VCVT_HF_US): New.
(VCVTH_US): New.
(FP16_RND): New.
(absneg_str): New.
(FCVTI32typename): Moved from vfp.md.
(sup): Add UNSPEC_VCVTA_S, UNSPEC_VCVTA_U, UNSPEC_VCVTM_S,
UNSPEC_VCVTM_U, UNSPEC_VCVTN_S, UNSPEC_VCVTN_U, UNSPEC_VCVTP_S,
UNSPEC_VCVTP_U, UNSPEC_VCVT_HF_S_N, UNSPEC_VCVT_HF_U_N,
UNSPEC_VCVT_SI_S_N, UNSPEC_VCVT_SI_U_N, UNSPEC_VCVTH_S_N,
UNSPEC_VCVTH_U_N, UNSPEC_VCVTH_S and UNSPEC_VCVTH_U.
(vcvth_op): New.
(fp16_rnd_str): New.
(fp16_rnd_insn): New.
* config/arm/unspecs.md (UNSPEC_VCVT_HF_S_N): New.
(UNSPEC_VCVT_HF_U_N): New.
(UNSPEC_VCVT_SI_S_N): New.
(UNSPEC_VCVT_SI_U_N): New.
(UNSPEC_VCVTH_S): New.
(UNSPEC_VCVTH_U): New.
(UNSPEC_VCVTA_S): New.
(UNSPEC_VCVTA_U): New.
(UNSPEC_VCVTM_S): New.
(UNSPEC_VCVTM_U): New.
(UNSPEC_VCVTN_S): New.
(UNSPEC_VCVTN_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VCVTP_S): New.
(UNSPEC_VCVTP_U): New.
(UNSPEC_VRND): New.
(UNSPEC_VRNDA): New.
(UNSPEC_VRNDI): New.
(UNSPEC_VRNDM): New.
(UNSPEC_VRNDN): New.
(UNSPEC_VRNDP): New.
(UNSPEC_VRNDX): New.
* config/arm/vfp.md (<absneg_str>hf2): New.
(neon_vabshf): New.
(neon_v<fp16_rnd_str>hf): New.
(neon_vrndihf): New.
(addhf3): New.
(subhf3): New.
(divhf3): New.
(mulhf3): New.
(*mulsf3neghf_vfp): New.
(*negmulhf3_vfp): New.
(*mulsf3addhf_vfp): New.
(*mulhf3subhf_vfp): New.
(*mulhf3neghfaddhf_vfp): New.
(*mulhf3neghfsubhf_vfp): New.
(fmahf4): New.
(neon_vfmahf): New.
(fmsubhf4_fp16): New.
(neon_vfmshf): New.
(*fnmsubhf4): New.
(*fnmaddhf4): New.
(neon_vsqrthf): New.
(neon_vrsqrtshf): New.
(FCVT): Move to iterators.md.
(FCVTI32typename): Likewise.
(neon_vcvth<sup>hf): New.
(neon_vcvth<sup>si): New.
(neon_vcvth<sup>_nhf_unspec): New.
(neon_vcvth<sup>_nhf): New.
(neon_vcvth<sup>_nsi_unspec): New.
(neon_vcvth<sup>_nsi): New.
(neon_vcvt<vcvth_op>h<sup>si): New.
(neon_<fmaxmin_op>hf): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2-fp16-arith-1.c: New.
* gcc.target/arm/armv8_2-fp16-conv-1.c: New.
From-SVN: r240411
2016-09-23 09:46:26 +00:00
e2080e79be
Add missing ChangeLog from r240375
...
From-SVN: r240410
2016-09-23 09:45:04 +00:00
576987fc74
S/390: Mode attrs "bitoff[_plus]" simplify risbg instructions.
...
Add a new mode attribute to simplify some instruction patterns.
gcc/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes.
("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10")
("*insv<mode>_zEC12_appendbitsleft")
("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll")
("*r<noxa>sbg_<mode>_srl"): Use new attributes.
gcc/testsuite/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly
output to the simplified instructions.
From-SVN: r240409
2016-09-23 09:44:15 +00:00
199d1d488f
ipa-cp.c (ipcp_store_vr_results): Avoid static local var zero.
...
* ipa-cp.c (ipcp_store_vr_results): Avoid static local
var zero.
* sreal.h (sreal::min, sreal::max): Avoid static local vars,
construct values without normalization.
* tree-ssa-sccvn.c (vn_reference_lookup_3): Don't initialize
static local lhs_ops to vNULL.
cp/
* name-lookup.c (store_bindings, store_class_bindings): Don't
initialize static local bindings_need_stored to vNULL.
From-SVN: r240408
2016-09-23 11:43:09 +02:00
4ffc8099a7
[PATCH 7/17][ARM] Add FP16 data movement instructions.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/arm/arm.c (coproc_secondary_reload_class): Make HFmode
available when FP16 instructions are available.
(output_move_vfp): Add support for 16-bit data moves.
(arm_validize_comparison): Fix some white-space. Support HFmode
by conversion to SFmode.
* config/arm/arm.md (truncdfhf2): Fix a comment.
(extendhfdf2): Likewise.
(cstorehf4): New.
(movsicc): Fix some white-space.
(movhfcc): New.
(movsfcc): Fix some white-space.
(*cmovhf): New.
* config/arm/vfp.md (*arm_movhi_vfp): Disable when VFP FP16
instructions are available.
(*thumb2_movhi_vfp): Likewise.
(*arm_movhi_fp16): New.
(*thumb2_movhi_fp16): New.
(*movhf_vfp_fp16): New.
(*movhf_vfp_neon): Disable when VFP FP16 instructions are
available.
(*movhf_vfp): Likewise.
(extendhfsf2): Enable when VFP FP16 instructions are available.
(truncsfhf2): Enable when VFP FP16 instructions are available.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/armv8_2_fp16-move-1.c: New.
* gcc.target/arm/fp16-aapcs-1.c: Update expected output.
Co-Authored-By: Jiong Wang <jiong.wang@arm.com>
From-SVN: r240407
2016-09-23 09:35:22 +00:00
99924e7a7b
Fix typos: adress -> address
...
* config/s390/vx-builtins.md: Replace 'adress' with 'address'.
From-SVN: r240406
2016-09-23 09:32:15 +00:00
b437ebca65
gcc-dg.exp (process-message): Support relative line number notation - .+4 or .-1 etc.
...
* lib/gcc-dg.exp (process-message): Support relative line number
notation - .+4 or .-1 etc.
* gcc.dg/dg-test-1.c: New test.
From-SVN: r240405
2016-09-23 11:23:52 +02:00
b1a970a5cc
[PATCH 6/17][ARM] Add data processing intrinsics for float16_t.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm.c (arm_evpc_neon_vuzp): Add support for V8HF and
V4HF modes.
(arm_evpc_neon_vtrn): Likewise.
(arm_evpc_neon_vrev): Likewise.
(arm_evpc_neon_vext): Likewise.
* config/arm/arm_neon.h (vbsl_f16): New.
(vbslq_f16): New.
(vdup_n_f16): New.
(vdupq_n_f16): New.
(vdup_lane_f16): New.
(vdupq_lane_f16): New.
(vext_f16): New.
(vextq_f16): New.
(vmov_n_f16): New.
(vmovq_n_f16): New.
(vrev64_f16): New.
(vrev64q_f16): New.
(vtrn_f16): New.
(vtrnq_f16): New.
(vuzp_f16): New.
(vuzpq_f16): New.
(vzip_f16): New.
(vzipq_f16): New.
* config/arm/arm_neon_buillins.def (vdup_n): New (v8hf, v4hf variants).
(vdup_lane): New (v8hf, v4hf variants).
(vext): New (v8hf, v4hf variants).
(vbsl): New (v8hf, v4hf variants).
* config/arm/iterators.md (VDQWH): New.
(VH): New.
(V_double_vector_mode): Add V8HF and V4HF. Fix white-space.
(Scalar_mul_8_16): Fix white-space.
(Is_d_reg): Add V4HF and V8HF.
* config/arm/neon.md (neon_vdup_lane<mode>_internal): New.
(neon_vdup_lane<mode>): New.
(neon_vtrn<mode>_internal): Replace VDQW with VDQWH.
(*neon_vtrn<mode>_insn): Likewise.
(neon_vzip<mode>_internal): Likewise. Also fix white-space.
(*neon_vzip<mode>_insn): Likewise
(neon_vuzp<mode>_internal): Likewise.
(*neon_vuzp<mode>_insn): Likewise
* config/arm/vec-common.md (vec_perm_const<mode>): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(FP16_SUPPORTED): New
(expected-hfloat-16x4): Make conditional on __fp16 support.
(expected-hfloat-16x8): Likewise.
(vdup_n_f16): Disable for non-AArch64 targets.
* gcc.target/aarch64/advsimd-intrinsics/vbsl.c: Add __fp16 tests,
conditional on FP16_SUPPORTED.
* gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vext.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Add support
for testing __fp16.
* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: Add __fp16 tests,
conditional on FP16_SUPPORTED.
* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise.
From-SVN: r240404
2016-09-23 09:23:01 +00:00
50df9464b8
[PATCH 5/17][ARM] Enable HI mode moves for floating point values.
...
gcc/
2016-09-23 Jiong Wang <jiong.wang@arm.com>
Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm.c (output_move_vfp): Weaken assert to allow
HImode.
(arm_hard_regno_mode_ok): Allow HImode values in VFP registers.
* config/arm/arm.md (*movhi_bytes): Disable when VFP registers are
available. Also fix some white-space.
* config/arm/vfp.md (*arm_movhi_vfp): New.
(*thumb2_movhi_vfp): New.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/short-vfp-1.c: New.
From-SVN: r240403
2016-09-23 09:15:24 +00:00
536b9f42ce
[PATCH 4/17][ARM] Define feature macros for FP16.
...
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm-c.c (arm_cpu_builtins): Define
"__ARM_FEATURE_FP16_SCALAR_ARITHMETIC" and
"__ARM_FEATURE_FP16_VECTOR_ARITHMETIC".
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* gcc.target/arm/attr-fp16-arith-1.c: New.
From-SVN: r240402
2016-09-23 09:09:28 +00:00
1b9e31cf74
[PATCH 3/17][Testsuite] Add ARM support for ARMv8.2-A with FP16 arithmetic instructions.
...
gcc/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* doc/sourcebuild.texi (ARM-specific attributes): Add anchor for
arm_v8_1a_neon_ok. Add entries for arm_v8_2a_fp16_scalar_ok,
arm_v8_2a_fp16_scalar_hw, arm_v8_2a_fp16_neon_ok and
arm_v8_2a_fp16_neon_hw.
(Add options): Add entries for arm_v8_1a_neon, arm_v8_2a_scalar,
arm_v8_2a_neon.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* lib/target-supports.exp (add_options_for_arm_v8_2a_fp16_scalar):
New.
(add_options_for_arm_v8_2a_fp16_neon): New.
(check_effective_target_arm_arch_v8_2a_ok): Auto-generate.
(add_options_for_arm_arch_v8_2a): Auto-generate.
(check_effective_target_arm_arch_v8_2a_multilib): Auto-generate.
(check_effective_target_arm_v8_2a_fp16_scalar_ok_nocache): New.
(check_effective_target_arm_v8_2a_fp16_scalar_ok): New.
(check_effective_target_arm_v8_2a_fp16_neon_ok_nocache): New.
(check_effective_target_arm_v8_2a_fp16_neon_ok): New.
(check_effective_target_arm_v8_2a_fp16_scalar_hw): New.
(check_effective_target_arm_v8_2a_fp16_neon_hw): New.
From-SVN: r240401
2016-09-23 09:00:34 +00:00
a5b42ee713
[PATCH 2/17][Testsuite] Add a selector for ARM FP16 alternative format support.
...
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* doc/sourcebuild.texi (ARM-specific attributes): Add entries for
arm_fp16_alternative_ok and arm_fp16_none_ok.
testsuite/
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* g++.dg/ext/arm-fp16/arm-fp16-ops-3.C: Use
arm_fp16_alternative_ok.
* g++.dg/ext/arm-fp16/arm-fp16-ops-4.C: Likewise.
* gcc.dg/torture/arm-fp16-int-convert-alt.c: Likewise.
* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c: Likewise.
* gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c: Likewise.
* gcc.target/arm/fp16-compile-alt-1.c: Likewise.
* gcc.target/arm/fp16-compile-alt-10.c: Likewise.
* gcc.target/arm/fp16-compile-alt-11.c: Likewise.
* gcc.target/arm/fp16-compile-alt-12.c: Likewise.
* gcc.target/arm/fp16-compile-alt-2.c: Likewise.
* gcc.target/arm/fp16-compile-alt-3.c: Likewise.
* gcc.target/arm/fp16-compile-alt-4.c: Likewise.
* gcc.target/arm/fp16-compile-alt-5.c: Likewise.
* gcc.target/arm/fp16-compile-alt-6.c: Likewise.
* gcc.target/arm/fp16-compile-alt-7.c: Likewise.
* gcc.target/arm/fp16-compile-alt-8.c: Likewise.
* gcc.target/arm/fp16-compile-alt-9.c: Likewise.
* gcc.target/arm/fp16-compile-none-1.c: Use arm_fp16_none_ok.
* gcc.target/arm/fp16-compile-none-2.c: Likewise.
* gcc.target/arm/fp16-rounding-alt-1.c: Use
arm_fp16_alternative_ok.
* lib/target-supports.exp
(check_effective_target_arm_fp16_alternative_ok_nocache): New.
(check_effective_target_arm_fp16_alternative_ok): New.
(check_effective_target_arm_fp16_none_ok_nocache): New.
(check_effective_target_arm_fp16_none_ok): New.
From-SVN: r240400
2016-09-23 08:52:55 +00:00
fcbc975bed
Fix typo in IPA ICF
...
* ipa-icf.c (sem_variable::merge): Replace adress
with address.
* gcc.dg/ipa/pr77653.c: Replace adress
with address.
From-SVN: r240399
2016-09-23 08:49:41 +00:00
4040b89af8
[PATCH 1/17][ARM] Add ARMv8.2-A command line option and profile.
...
2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
* config/arm/arm-arches.def ("armv8.1-a"): Add FL_CRC32.
("armv8.2-a"): New.
("armv8.2-a+fp16"): New.
* config/arm/arm-protos.h (FL2_ARCH8_2): New.
(FL2_FP16INST): New.
(FL2_FOR_ARCH8_2A): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (arm_arch8_2): New.
(arm_fp16_inst): New.
(arm_option_override): Set arm_arch8_2 and arm_fp16_inst. Check
for incompatible fp16-format settings.
* config/arm/arm.h (TARGET_VFP_FP16INST): New.
(TARGET_NEON_FP16INST): New.
(arm_arch8_2): Declare.
(arm_fp16_inst): Declare.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add entries for
march=armv8.2-a and march=armv8.2-a+fp16.
* config/arm/t-aprofile (Arch Matches): Add entries for armv8.2-a
and armv8.2-a+fp16.
* doc/invoke.texi (ARM Options): Add "-march=armv8.1-a",
"-march=armv8.2-a" and "-march=armv8.2-a+fp16".
From-SVN: r240398
2016-09-23 08:45:16 +00:00
69ec211343
Remove fused-madd from documentation
...
* doc/extend.texi: Remove fused-madd from i386 target
options.
From-SVN: r240395
2016-09-23 07:58:33 +00:00
1822b732a3
Support movbe as a i386 target optimization node
...
* gcc.target/i386/movbe-4.c: New test.
* config/i386/i386.c (ix86_valid_target_attribute_inner_p):
Handle movbe.
From-SVN: r240394
2016-09-23 07:58:07 +00:00
fab18cc4f7
Support crc32 as a i386 target optimization node
...
* config/i386/i386.c (ix86_valid_target_attribute_inner_p):
Handle crc32.
* gcc.target/i386/crc32-5.c: New test.
From-SVN: r240393
2016-09-23 07:57:07 +00:00
e70f01b561
re PR target/71652 (ICE in in ix86_target_macros_internal, at config/i386/i386-c.c:187)
...
Fix PR target/71652
PR target/71652
* config/i386/i386.c (ix86_option_override_internal): Change
signature and return false when there's an error related to
arch string.
(release_options_strings): New function.
(ix86_valid_target_attribute_tree): Call the function.
* gcc.target/i386/pr71652.c: New test.
* gcc.target/i386/pr71652-2.c: New test.
* gcc.target/i386/pr71652-3.c: New test.
From-SVN: r240392
2016-09-23 07:55:57 +00:00
f2e81d0585
gcc-dg.exp (process-message): Support relative line number notation - .+4 or .-1 etc.
...
* lib/gcc-dg.exp (process-message): Support relative line number
notation - .+4 or .-1 etc.
* gcc.dg/dg-test-1.c: New test.
From-SVN: r240391
2016-09-23 09:46:15 +02:00
aaa1b10f54
* hsa-gen.c (hsa_op_immed::hsa_op_immed Use CONSTRUCTOR_NELTS (...)
...
instead of vec_safe_length (CONSTRUCTOR_ELTS (...)).
(gen_hsa_ctor_assignment): Likewise.
* print-tree.c (print_node): Likewise.
* tree-dump.c (dequeue_and_dump): Likewise.
* tree-sra.c (sra_modify_constructor_assign): Likewise.
* expr.c (store_constructor): Likewise.
* fold-const.c (operand_equal_p): Likewise.
* tree-pretty-print.c (dump_generic_node): Likewise.
* hsa-brig.c (hsa_op_immed::emit_to_buffer): Likewise.
* ipa-icf-gimple.c (func_checker::compare_operand): Likewise.
cp/
* typeck2.c (process_init_constructor_record): Use
CONSTRUCTOR_NELTS (...) instead of
vec_safe_length (CONSTRUCTOR_ELTS (...)).
* decl.c (reshape_init_r): Likewise.
(check_initializer): Likewise.
ada/
* gcc-interface/decl.c (gnat_to_gnu_entity): Use
CONSTRUCTOR_NELTS (...) instead of
vec_safe_length (CONSTRUCTOR_ELTS (...)).
From-SVN: r240390
2016-09-23 09:34:43 +02:00
9500733cc6
hooks.h (hook_uint_uintp_false): Declare.
...
2016-09-23 Richard Biener <rguenther@suse.de>
* hooks.h (hook_uint_uintp_false): Declare.
From-SVN: r240389
2016-09-23 07:22:32 +00:00
33989cfff5
Provide right LDD offset bound in avr_address_cost
...
This patch fixes cost computation in avr_address_cost - instead of the
hardcoded 61, it uses the already existing MAX_LD_OFFSET(mode) macro.
This showed up when investigating a code size regression in the ivopts
pass. That pass computes address_cost with and without an offset to
decide on the right induction variable candidate(s). The legitimate
address target hook returns false for offsets more than 63, so the
pass calls the TARGET_ADDRESS_COST hook with 62 as the offset.
The avr_address_cost hook returns 18 as the cost, and the ivopts pass
concludes that the cost of address with *any* offset is 18, which is not
true - the higher cost is incurred only with offsets bigger than MAX_LD_OFFSET.
This in turn results in a suboptimal choice of induction variables in the
ivopts pass. The patch changes the hardcoded 61 to use the mode
specific MAX_LD_OFFSET instead.
Regression testing with just that fix showed one additional
compilation timeout. That turned out to be the same as
https://lists.nongnu.org/archive/html/avr-gcc-list/2014-03/msg00010.html
- the middle end takes too much time to decide on the best strategy to
multiply DImode values on a 64 bit host. This already causes timeouts
for a few builtin-arith-overflow-* tests (see
https://gcc.gnu.org/ml/gcc-testresults/2016-09/msg02018.html ), so it
isn't really related to this fix. Just providing a cost estimate for
DImode mul fixes the timeout though, so the patch does that by scaling
SImode costs by 2 for DImode muls.
With both changes in, there are no regressions, and the
builtin-arith-overflow-* tests now PASS and don't timeout.
gcc/ChangeLog
2016-09-22 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
* config/avr/avr.c (avr_rtx_costs_1): Handle DImode MULT.
(avr_address_cost): Replace 61 with MAX_LD_OFFSET(mode).
From-SVN: r240388
2016-09-23 07:12:35 +00:00
David Malcolm
Thomas Preud'homme
Matthew Fortune
Doug Gilmore
Bernd Edlinger
Marek Polacek
Jason Merrill
Fritz Reese
Richard Biener
Rainer Orth
Matthew Wahab
Jiong Wang
Kugan Vivekanandarajah
Andre Vehreschild
Renlin Li
Uros Bizjak
Dominik Vogt
Bin Cheng
Tamar Christina
Jakub Jelinek
Martin Liska
Jakub Jelinek
Matthew Wahab
Senthil Kumar Selvaraj