Commit Graph

55307 Commits

Author SHA1 Message Date
Bernd Edlinger c41f1c42bf Fix include path for in-tree cloog.
2014-06-23  Bernd Edlinger  <bernd.edlinger@hotmail.de>

        Fix include path for in-tree cloog.
        * config/cloog.m4 (CLOOG_INIT_FLAGS): Remove bogus include path.
        * configure: Regenerate.

P.S: moved a few ChangeLog entries to gcc/ChangeLog

From-SVN: r211913
2014-06-23 19:15:16 +00:00
Paul Gortmaker 82ec440684 gcc.c (set_multilib_dir): Fix typo.
2014-06-23  Paul Gortmaker  <paul.gortmaker@windriver.com>

        * gcc.c (set_multilib_dir): Fix typo.

From-SVN: r211911
2014-06-23 12:51:36 -06:00
Richard Biener e5d8bd8c77 tree-ssa-loop.c (gate_loop): New function.
2014-06-23  Richard Biener  <rguenther@suse.de>

	* tree-ssa-loop.c (gate_loop): New function.
	(pass_tree_loop::gate): Call it.
	(pass_data_tree_no_loop, pass_tree_no_loop,
	make_pass_tree_no_loop): New.
	* tree-vectorizer.c: Include tree-scalar-evolution.c
	(pass_slp_vectorize::execute): Initialize loops and SCEV if
	required.
	(pass_slp_vectorize::clone): New method.
	* timevar.def (TV_TREE_NOLOOP): New.
	* tree-pass.h (make_pass_tree_no_loop): Declare.
	* passes.def (pass_tree_no_loop): New pass group with
	SLP vectorizer.

	* g++.dg/vect/slp-pr50413.cc: Scan and cleanup appropriate SLP dumps.
	* g++.dg/vect/slp-pr50819.cc: Likewise.
	* g++.dg/vect/slp-pr56812.cc: Likewise.
	* gcc.dg/vect/bb-slp-1.c: Likewise.
	* gcc.dg/vect/bb-slp-10.c: Likewise.
	* gcc.dg/vect/bb-slp-11.c: Likewise.
	* gcc.dg/vect/bb-slp-13.c: Likewise.
	* gcc.dg/vect/bb-slp-14.c: Likewise.
	* gcc.dg/vect/bb-slp-15.c: Likewise.
	* gcc.dg/vect/bb-slp-16.c: Likewise.
	* gcc.dg/vect/bb-slp-17.c: Likewise.
	* gcc.dg/vect/bb-slp-18.c: Likewise.
	* gcc.dg/vect/bb-slp-19.c: Likewise.
	* gcc.dg/vect/bb-slp-2.c: Likewise.
	* gcc.dg/vect/bb-slp-20.c: Likewise.
	* gcc.dg/vect/bb-slp-21.c: Likewise.
	* gcc.dg/vect/bb-slp-22.c: Likewise.
	* gcc.dg/vect/bb-slp-23.c: Likewise.
	* gcc.dg/vect/bb-slp-24.c: Likewise.
	* gcc.dg/vect/bb-slp-25.c: Likewise.
	* gcc.dg/vect/bb-slp-26.c: Likewise.
	* gcc.dg/vect/bb-slp-27.c: Likewise.
	* gcc.dg/vect/bb-slp-28.c: Likewise.
	* gcc.dg/vect/bb-slp-29.c: Likewise.
	* gcc.dg/vect/bb-slp-3.c: Likewise.
	* gcc.dg/vect/bb-slp-30.c: Likewise.
	* gcc.dg/vect/bb-slp-31.c: Likewise.
	* gcc.dg/vect/bb-slp-32.c: Likewise.
	* gcc.dg/vect/bb-slp-4.c: Likewise.
	* gcc.dg/vect/bb-slp-5.c: Likewise.
	* gcc.dg/vect/bb-slp-6.c: Likewise.
	* gcc.dg/vect/bb-slp-7.c: Likewise.
	* gcc.dg/vect/bb-slp-8.c: Likewise.
	* gcc.dg/vect/bb-slp-8a.c: Likewise.
	* gcc.dg/vect/bb-slp-8b.c: Likewise.
	* gcc.dg/vect/bb-slp-9.c: Likewise.
	* gcc.dg/vect/bb-slp-cond-1.c: Likewise.
	* gcc.dg/vect/bb-slp-pattern-1.c: Likewise.
	* gcc.dg/vect/bb-slp-pattern-2.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-1.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-2.c: Likewise.
	* gcc.dg/vect/fast-math-bb-slp-call-3.c: Likewise.
	* gcc.dg/vect/no-tree-reassoc-bb-slp-12.c: Likewise.
	* gcc.dg/vect/no-tree-sra-bb-slp-pr50730.c: Likewise.
	* gcc.dg/vect/pr26359.c: Likewise.
	* gcc.dg/vect/costmodel/ppc/costmodel-bb-slp-9a.c: Likewise.

From-SVN: r211904
2014-06-23 16:51:10 +00:00
H.J. Lu 228e5d2b0c Assume x86-64 if a 32-bit processor supports SSE2 and 64-bit
PR target/61570
	* config/i386/driver-i386.c (host_detect_local_cpu): Set arch
	to x86-64 if a 32-bit processor supports SSE2 and 64-bit.

From-SVN: r211901
2014-06-23 09:28:36 -07:00
James Greenhalgh 0379033b63 Re: [AArch64] Implement ADD in vector registers for 32-bit scalar values.
gcc/

	* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
	"yes" where needed.

From-SVN: r211899
2014-06-23 16:00:02 +00:00
Alan Modra 82bb92454f re PR bootstrap/61583 (stage2 and stage3 compare failure due to value range loss)
gcc/
	PR bootstrap/61583
	* tree-vrp.c (remove_range_assertions): Do not set is_unreachable
	to zero on debug statements.
gcc/testsuite/
	* gcc.dg/pr61583.c: New.

From-SVN: r211897
2014-06-24 00:38:30 +09:30
Alan Lawrence 096c59be14 PR/60825 Make {int,uint}64x1_t in arm_neon.h a proper vector type
gcc/ChangeLog:
 	PR target/60825
	* config/aarch64/aarch64-builtins.c (aarch64_types_unop_qualifiers):
	Ignore third operand if present by marking qualifier_internal.

	* config/aarch64/aarch64-simd-builtins.def (abs): Comment.

	* config/aarch64/arm_neon.h (int64x1_t, uint64x1_t): Typedef to GCC
	vector extension.
	(aarch64_vget_lane_s64, aarch64_vdup_lane_s64,
	arch64_vdupq_lane_s64, aarch64_vdupq_lane_u64): Remove macro.
	(vqadd_s64, vqadd_u64, vqsub_s64, vqsub_u64, vqneg_s64, vqabs_s64,
	vcreate_s64, vcreate_u64, vreinterpret_s64_f64, vreinterpret_u64_f64,
	vcombine_u64, vbsl_s64, vbsl_u64, vceq_s64, vceq_u64, vceqz_s64,
	vceqz_u64, vcge_s64, vcge_u64, vcgez_s64, vcgt_s64, vcgt_u64,
	vcgtz_s64, vcle_s64, vcle_u64, vclez_s64, vclt_s64, vclt_u64,
	vcltz_s64, vdup_n_s64, vdup_n_u64, vld1_s64, vld1_u64, vmov_n_s64,
	vmov_n_u64, vqdmlals_lane_s32, vqdmlsls_lane_s32,
	vqdmulls_lane_s32, vqrshl_s64, vqrshl_u64, vqrshl_u64, vqshl_s64,
	vqshl_u64, vqshl_n_s64, vqshl_n_u64, vqshl_n_s64, vqshl_n_u64,
	vqshlu_n_s64, vrshl_s64, vrshl_u64, vrshr_n_s64, vrshr_n_u64,
	vrsra_n_s64, vrsra_n_u64, vshl_n_s64, vshl_n_u64, vshl_s64,
	vshl_u64, vshr_n_s64, vshr_n_u64, vsli_n_s64, vsli_n_u64,
	vsqadd_u64, vsra_n_s64, vsra_n_u64, vsri_n_s64, vsri_n_u64,
	vst1_s64, vst1_u64, vtst_s64, vtst_u64, vuqadd_s64): Wrap existing
	logic in GCC vector extensions
	
	(vpaddd_s64, vaddd_s64, vaddd_u64, vceqd_s64, vceqd_u64, vceqzd_s64
	vceqzd_u64, vcged_s64, vcged_u64, vcgezd_s64, vcgtd_s64, vcgtd_u64,
	vcgtzd_s64, vcled_s64, vcled_u64, vclezd_s64, vcltd_s64, vcltd_u64,
	vcltzd_s64, vqdmlals_s32, vqdmlsls_s32, vqmovnd_s64, vqmovnd_u64
	vqmovund_s64, vqrshld_s64, vqrshld_u64, vqrshrnd_n_s64,
	vqrshrnd_n_u64, vqrshrund_n_s64, vqshld_s64, vqshld_u64,
	vqshld_n_u64, vqshrnd_n_s64, vqshrnd_n_u64, vqshrund_n_s64,
	vrshld_u64, vrshrd_n_u64, vrsrad_n_u64, vshld_n_u64, vshld_s64,
	vshld_u64, vslid_n_u64, vsqaddd_u64, vsrad_n_u64, vsrid_n_u64,
	vsubd_s64, vsubd_u64, vtstd_s64, vtstd_u64): Fix type signature.

	(vabs_s64): Use GCC vector extensions; call __builtin_aarch64_absdi.

	(vget_high_s64, vget_high_u64): Reimplement with GCC vector
	extensions.

	(__GET_LOW, vget_low_u64): Wrap result using vcreate_u64.
	(vget_low_s64): Use __GET_LOW macro.
	(vget_lane_s64, vget_lane_u64, vdupq_lane_s64, vdupq_lane_u64): Use
	gcc vector extensions, add call to __builtin_aarch64_lane_boundsi.
	(vdup_lane_s64, vdup_lane_u64,): Add __builtin_aarch64_lane_bound_si.
	(vdupd_lane_s64, vdupd_lane_u64): Fix type signature, add
	__builtin_aarch64_lane_boundsi, use GCC vector extensions.

	(vcombine_s64): Use GCC vector extensions; remove cast.
	(vqaddd_s64, vqaddd_u64, vqdmulls_s32, vqshld_n_s64, vqshlud_n_s64,
	vqsubd_s64, vqsubd_u64, vrshld_s64, vrshrd_n_s64, vrsrad_n_s64,
	vshld_n_s64, vshrd_n_s64, vslid_n_s64, vsrad_n_s64, vsrid_n_s64):
	Fix type signature; remove cast.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C (f22, f23): New tests of 
	[u]int64x1_t.

	* gcc.target/aarch64/aapcs64/func-ret-64x1_1.c: Add {u,}int64x1 cases.
	* gcc.target/aarch64/aapcs64/test_64x1_1.c: Likewise.

	* gcc.target/aarch64/scalar_intrinsics.c (test_vaddd_u64,
	test_vaddd_s64, test_vceqd_s64, test_vceqzd_s64, test_vcged_s64,
	test_vcled_s64, test_vcgezd_s64, test_vcged_u64, test_vcgtd_s64,
	test_vcltd_s64, test_vcgtzd_s64, test_vcgtd_u64, test_vclezd_s64,
	test_vcltzd_s64, test_vqaddd_u64, test_vqaddd_s64, test_vqdmlals_s32,
	test_vqdmlsls_s32, test_vqdmulls_s32, test_vuqaddd_s64,
	test_vsqaddd_u64, test_vqmovund_s64, test_vqmovnd_s64,
	test_vqmovnd_u64, test_vsubd_u64, test_vsubd_s64, test_vqsubd_u64,
	test_vqsubd_s64, test_vshld_s64, test_vshld_u64, test_vrshld_s64,
	test_vrshld_u64, test_vshrd_n_s64, test_vshrd_n_u64, test_vsrad_n_s64,
	test_vsrad_n_u64, test_vrshrd_n_s64, test_vrshrd_n_u64,
	test_vrsrad_n_s64, test_vrsrad_n_u64, test_vqrshld_s64,
	test_vqrshld_u64, test_vqshlud_n_s64, test_vqshld_s64, test_vqshld_u64,
	test_vqshld_n_u64, test_vqshrund_n_s64, test_vqrshrund_n_s64,
	test_vqshrnd_n_s64, test_vqshrnd_n_u64, test_vqrshrnd_n_s64,
	test_vqrshrnd_n_u64, test_vshld_n_s64, test_vshdl_n_u64,
	test_vslid_n_s64, test_vslid_n_u64, test_vsrid_n_s64,
	test_vsrid_n_u64): Fix signature to match intrinsic.
	
	(test_vabs_s64): Remove.
	(test_vaddd_s64_2, test_vsubd_s64_2): Use force_simd.

	(test_vdupd_lane_s64): Rename to...
	(test_vdupd_laneq_s64): ...and remove a call to force_simd.

	(test_vdupd_lane_u64): Rename to...
	(test_vdupd_laneq_u64): ...and remove a call to force_simd.

	(test_vtst_s64): Rename to...
	(test_vtstd_s64): ...and change int64x1_t to int64_t.

	(test_vtst_u64): Rename to...
	(test_vtstd_u64): ...and change uint64x1_t to uint64_t.

	* gcc.target/aarch64/singleton_intrinsics_1.c: New file.
	* gcc.target/aarch64/vdup_lane_1.c, gcc.target/aarch64/vdup_lane_2.c:
	Remove out-of-bounds tests.
	* gcc.target/aarch64/vneg_s.c (INDEX*, RUN_TEST): Remove INDEX macro.

From-SVN: r211894
2014-06-23 14:07:42 +00:00
Alan Lawrence c6a29a091a PR/60825 Make float64x1_t in arm_neon.h a proper vector type
gcc/ChangeLog:
	PR target/60825
	* config/aarch64/aarch64.c (aarch64_simd_mangle_map): Add entry for
	V1DFmode.
	* config/aarch64/aarch64-builtins.c (aarch64_simd_builtin_type_mode):
	add V1DFmode
	(BUILTIN_VD1): New.
	(BUILTIN_VD_RE): Remove.
	(aarch64_init_simd_builtins): Add V1DF to modes/modenames.
	(aarch64_fold_builtin): Update reinterpret patterns, df becomes v1df.
	* config/aarch64/aarch64-simd-builtins.def (create): Make a v1df
	variant but not df.
	(vreinterpretv1df*, vreinterpret*v1df): New.
	(vreinterpretdf*, vreinterpret*df): Remove.
	* config/aarch64/aarch64-simd.md (aarch64_create, aarch64_reinterpret*):
	Generate V1DFmode pattern not DFmode.
	* config/aarch64/iterators.md (VD_RE): Include V1DF, remove DF.
	(VD1): New.
	* config/aarch64/arm_neon.h (float64x1_t): typedef with gcc extensions.
	(vcreate_f64): Remove cast, use v1df builtin.
	(vcombine_f64): Remove cast, get elements with gcc vector extensions.
	(vget_low_f64, vabs_f64, vceq_f64, vceqz_f64, vcge_f64, vgfez_f64,
	vcgt_f64, vcgtz_f64, vcle_f64, vclez_f64, vclt_f64, vcltz_f64,
	vdup_n_f64, vdupq_lane_f64, vld1_f64, vld2_f64, vld3_f64, vld4_f64,
	vmov_n_f64, vst1_f64): Use gcc vector extensions.
	(vget_lane_f64, vdupd_lane_f64, vmulq_lane_f64, ): Use gcc extensions,
	add range check using __builtin_aarch64_im_lane_boundsi.
	(vfma_lane_f64, vfmad_lane_f64, vfma_laneq_f64, vfmaq_lane_f64,
	vfms_lane_f64, vfmsd_lane_f64, vfms_laneq_f64, vfmsq_lane_f64): Fix
	type signature, use gcc vector extensions.
	(vreinterpret_p8_f64, vreinterpret_p16_f64, vreinterpret_f32_f64,
	vreinterpret_f64_f32, vreinterpret_f64_p8, vreinterpret_f64_p16,
	vreinterpret_f64_s8, vreinterpret_f64_s16, vreinterpret_f64_s32,
	vreinterpret_f64_s64, vreinterpret_f64_u8, vreinterpret_f64_u16,
	vreinterpret_f64_u32, vreinterpret_f64_u64, vreinterpret_s8_f64,
	vreinterpret_s16_f64, vreinterpret_s32_f64, vreinterpret_s64_f64,
	vreinterpret_u8_f64, vreinterpret_u16_f64, vreinterpret_u32_f64,
	vreinterpret_u64_f64): Use v1df builtin not df.

gcc/testsuite/ChangeLog:
	* g++.dg/abi/mangle-neon-aarch64.C: Also test mangling of float64x1_t.
	* gcc.target/aarch64/aapcs/test_64x1_1.c: New test.
	* gcc.target/aarch64/aapcs/func-ret-64x1_1.c: New test.
	* gcc.target/aarch64/simd/ext_f64_1.c (main): Compare vector elements.
	* gcc.target/aarch64/vadd_f64.c: Rewrite with macro to use vector types.
	* gcc.target/aarch64/vsub_f64.c: Likewise.
	* gcc.target/aarch64/vdiv_f.c (INDEX*, RUN_TEST): Remove indexing scheme
	as now the same for all variants.
	* gcc.target/aarch64/vrnd_f64_1.c (compare_f64): Return float64_t not
	float64x1_t.

From-SVN: r211892
2014-06-23 12:46:52 +00:00
James Greenhalgh 463036be82 [AArch64] Implement ADD in vector registers for 32-bit scalar values.
gcc/

	* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
	vector registers.

gcc/testsuite/

	* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.

From-SVN: r211887
2014-06-23 09:04:40 +00:00
Jan Hubicka 1cff83e21d lto-cgraph.c (lto_output_node, input_node): Set/get init/fini priority directly.
* lto-cgraph.c (lto_output_node, input_node): Set/get init/fini priority
	directly.

From-SVN: r211886
2014-06-23 06:33:35 +00:00
Zhenqiang Chen 2c97f4728c loop-invariant.c (pre_check_invariant_p): New function.
2014-06-23  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* loop-invariant.c (pre_check_invariant_p): New function.
	(find_invariant_insn): Call pre_check_invariant_p.

From-SVN: r211885
2014-06-23 02:47:54 +00:00
Richard Henderson 08281ce0fb re PR bootstrap/61565 (ICE building libjava/interpret.cc)
PR target/61565

* compare-elim.c (struct comparison): Add eh_note.
(find_comparison_dom_walker::before_dom_children): Don't eliminate
a redundant comparison in a different EH region.  Purge EH edges if
necessary.

From-SVN: r211881
2014-06-22 12:32:57 -07:00
Segher Boessenkool 37317a1fc0 rs6000: Merge the var_shift yes/no alternatives
All instructions that are "var_shift" for some alternative have the shift
amount as operands[2].

This patch introduces an attribute "maybe_var_shift".  If that is set to
"yes", the default value of "var_shift" is set based on the operands[2]
value.

With that, we can merge the var_shift yes/no cases everywhere.  Do so.

Also change some more "i" to "n".

From-SVN: r211880
2014-06-22 19:21:08 +02:00
Segher Boessenkool 85c1cb2250 rs6000: Merge ashrsi3 and ashrdi3
From-SVN: r211879
2014-06-22 19:18:05 +02:00
Segher Boessenkool 137b8eb295 rs6000: Merge rotlsi3 and rotldi3
This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl
mnemonics, because they are shorter and more importantly they look the
same for 32-bit and 64-bit.

From-SVN: r211878
2014-06-22 19:16:03 +02:00
Segher Boessenkool d70be98ee1 Merge ashlsi3 and ashldi3
From-SVN: r211877
2014-06-22 19:14:02 +02:00
Segher Boessenkool f39a447c2d rs6000: Merge lshrsi3 and lshrdi3
For this create a new mode_attr "hH".

Also change "i" constraints on the shift amount to "n", which better
describes what it really is (GCC takes the integer value of these
operands and does arithmetic on them; symbolic constants will not work
here).

Also merge the "dot" insns with the corresponding splitters.  To do
this, don't allow the dot insns for CBE non-microcode mode at all
(it previously would just split it back always).

From-SVN: r211876
2014-06-22 19:11:55 +02:00
Segher Boessenkool 1a2443af3a rs6000: Remove "O" alternative from lshrsi3
Nothing will ever generate RTL matching this alternative.  Maybe long
ago this was needed, but not anymore.

From-SVN: r211875
2014-06-22 19:09:24 +02:00
Richard Sandiford 82db17cbd4 mips.c (mips_move_to_gpr_cost): Remove mode argument.
gcc/
	* config/mips/mips.c (mips_move_to_gpr_cost): Remove mode argument.
	(mips_move_from_gpr_cost): Likewise.
	(mips_register_move_cost): Update accordingly.
	(mips_secondary_reload_class): Remove name of in_p.

From-SVN: r211874
2014-06-22 09:57:02 +00:00
Marc Glisse 43c5fcfc0e re PR target/61503 (RTL representation of i386 shrdl instruction is incorrect?)
2014-06-22  Marc Glisse  <marc.glisse@inria.fr>

	PR target/61503
	* config/i386/i386.md (x86_64_shrd, x86_shrd,
	ix86_rotr<dwi>3_doubleword): Replace ashiftrt with lshiftrt.

From-SVN: r211873
2014-06-22 09:16:35 +00:00
Jan-Benedict Glaw 476571534d nios2.c: Include "builtins.h".
2014-06-21  Jan-Benedict Glaw  <jbglaw@lug-owl.de>

gcc/
	* config/nios2/nios2.c: Include "builtins.h".

From-SVN: r211868
2014-06-21 21:52:02 +00:00
Jan Hubicka 714c800f1f cgraph.h (tls_model_names): New variable.
* cgraph.h (tls_model_names): New variable.
	* print-tree.c (print_node): Simplify.
	* varpool.c (tls_model_names): New variable.
	(dump_varpool_node): Output tls model.

	* lto-symtab.c (lto_varpool_replace_node): Report TLS model conflicts.

From-SVN: r211865
2014-06-21 02:46:34 +00:00
Jan Hubicka b48972129f localalias.c: New testcase.
* gcc.dg/localalias.c: New testcase.
	* gcc.dg/localalias-2.c: New testcase.
	* gcc.dg/globalalias.c: New testcase.
	* gcc.dg/globalalias-2.c: New testcase.
	* ipa-visibility.c (function_and_variable_visibility): Disable
	temporarily local aliases for some targets.

From-SVN: r211864
2014-06-21 02:39:49 +00:00
Marek Polacek 0e37a2f33d asan.c (pass_sanopt::execute): Handle IFN_UBSAN_BOUNDS.
* asan.c (pass_sanopt::execute): Handle IFN_UBSAN_BOUNDS.
	* flag-types.h (enum sanitize_code): Add SANITIZE_BOUNDS and or it
	into SANITIZE_UNDEFINED.
	* doc/invoke.texi: Describe -fsanitize=bounds.
	* gimplify.c (gimplify_call_expr): Add gimplification of internal
	functions created in the FEs.
	* internal-fn.c: Move "internal-fn.h" after "tree.h".
	(expand_UBSAN_BOUNDS): New function.
	* internal-fn.def (UBSAN_BOUNDS): New internal function.
	* internal-fn.h: Don't define internal functions here.
	* opts.c (common_handle_option): Add -fsanitize=bounds.
	* sanitizer.def (BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS,
	BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS_ABORT): Add.
	* tree-core.h: Define internal functions here.
	(struct tree_base): Add ifn field.
	* tree-pretty-print.c: Include "internal-fn.h".
	(dump_generic_node): Handle functions without CALL_EXPR_FN.
	* tree.c (get_callee_fndecl): Likewise.
	(build_call_expr_internal_loc): New function.
	* tree.def (CALL_EXPR): Update description.
	* tree.h (CALL_EXPR_IFN): Define.
	(build_call_expr_internal_loc): Declare.
	* ubsan.c (get_ubsan_type_info_for_type): Return 0 for non-arithmetic
	types.
	(ubsan_type_descriptor): Change bool parameter to enum
	ubsan_print_style.  Adjust the code.  Add handling of
	UBSAN_PRINT_ARRAY.
	(ubsan_expand_bounds_ifn): New function.
	(ubsan_expand_null_ifn): Adjust ubsan_type_descriptor call.
	(ubsan_build_overflow_builtin): Likewise.
	(instrument_bool_enum_load): Likewise.
	(ubsan_instrument_float_cast): Likewise.
	* ubsan.h (enum ubsan_print_style): New enum.
	(ubsan_expand_bounds_ifn): Declare.
	(ubsan_type_descriptor): Adjust declaration.  Use a default parameter.
c-family/
	* c-gimplify.c: Include "c-ubsan.h" and "pointer-set.h".
	(ubsan_walk_array_refs_r): New function.
	(c_genericize): Instrument array bounds.
	* c-ubsan.c: Include "internal-fn.h".
	(ubsan_instrument_division): Mark instrumented arrays as having
	side effects.  Adjust ubsan_type_descriptor call.
	(ubsan_instrument_shift): Likewise.
	(ubsan_instrument_vla): Adjust ubsan_type_descriptor call.
	(ubsan_instrument_bounds): New function.
	(ubsan_array_ref_instrumented_p): New function.
	(ubsan_maybe_instrument_array_ref): New function.
	* c-ubsan.h (ubsan_instrument_bounds): Declare.
	(ubsan_array_ref_instrumented_p): Declare.
	(ubsan_maybe_instrument_array_ref): Declare.
testsuite/
	* c-c++-common/ubsan/bounds-1.c: New test.
	* c-c++-common/ubsan/bounds-2.c: New test.
	* c-c++-common/ubsan/bounds-3.c: New test.
	* c-c++-common/ubsan/bounds-4.c: New test.
	* c-c++-common/ubsan/bounds-5.c: New test.
	* c-c++-common/ubsan/bounds-6.c: New test.

From-SVN: r211859
2014-06-20 21:20:51 +00:00
Maciej W. Rozycki 9674047260 rs6000.md: Append `DONE' to preparation statements of `bswap' pattern splitters.
* config/rs6000/rs6000.md: Append `DONE' to preparation
	statements of `bswap' pattern splitters.

From-SVN: r211857
2014-06-20 19:42:22 +00:00
Tom de Vries 73b3e61bca Update definition of call_fusage_contains_non_callee_clobbers
2014-06-20  Tom de Vries  <tom@codesourcery.com>

	* target.def (call_fusage_contains_non_callee_clobbers): Update
	definition.
	* doc/tm.texi: Regenerate.

From-SVN: r211852
2014-06-20 18:28:12 +00:00
Yury Gribov 0cbf438b11 asan.c (instrument_strlen_call): Fixed instrumentation of trailing byte.
2014-06-18  Yury Gribov  <y.gribov@samsung.com>

gcc/
	* asan.c (instrument_strlen_call): Fixed instrumentation of
	trailing byte.

gcc/testsuite/
	* c-c++-common/asan/strlen-overflow-1.c: New test.

Co-Authored-By: Max Ostapenko <m.ostapenko@partner.samsung.com>

From-SVN: r211849
2014-06-20 16:33:28 +03:00
Martin Jambor bec81025ed re PR ipa/61540 (internal compiler error in try_make_edge_direct_virtual_call)
2014-06-20  Martin Jambor  <mjambor@suse.cz>

	PR ipa/61540
	* ipa-prop.c (impossible_devirt_target): New function.
	(try_make_edge_direct_virtual_call): Use it, also instead of
	asserting.

testsuite/
        * g++.dg/ipa/pr61540.C: New test.

From-SVN: r211847
2014-06-20 13:19:46 +02:00
Yury Gribov bf613c022e re PR sanitizer/61530 (segfault with asan)
2014-06-18  Yury Gribov  <y.gribov@samsung.com>

gcc/
	PR sanitizer/61530
	* asan.c (build_check_stmt): Add condition.

gcc/testsuite/
	* c-c++-common/asan/pr61530.c: New test.
	

Co-Authored-By: Max Ostapenko <m.ostapenko@partner.samsung.com>

From-SVN: r211846
2014-06-20 13:26:55 +03:00
Martin Jambor 803d0ab0e8 re PR ipa/61211 (ICE: verify_cgraph_node failed: edge points to wrong declaration with -O3 -fno-inline)
2014-06-20  Martin Jambor  <mjambor@suse.cz>

	PR ipa/61211
	* cgraph.c (clone_of_p): Allow skipped_branch to deal with
	expanded clones.

From-SVN: r211844
2014-06-20 11:54:39 +02:00
Kyrylo Tkachov 278821f265 [AArch64] Fix some saturating math NEON intrinsics types.
[gcc/]
	* config/aarch64/iterators.md (VCOND): Handle SI and HI modes.
	Update comments.
	(VCONQ): Make comment more helpful.
	(VCON): Delete.
	* config/aarch64/aarch64-simd.md
	(aarch64_sqdmulh_lane<mode>):
	Use VCOND for operands 2.  Update lane checking and flipping logic.
	(aarch64_sqrdmulh_lane<mode>): Likewise.
	(aarch64_sq<r>dmulh_lane<mode>_internal): Likewise.
	(aarch64_sqdmull2<mode>): Remove VCON, use VQ_HSI mode iterator.
	(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, VD_HSI): Change mode
	attribute of operand 3 to VCOND.
	(aarch64_sqdml<SBINQOPS:as>l_lane<mode>_internal, SD_HSI): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_lane<mode>_internal): Likewise.
	(aarch64_sqdmull_lane<mode>_internal, VD_HSI): Likewise.
	(aarch64_sqdmull_lane<mode>_internal, SD_HSI): Likewise.
	(aarch64_sqdmull2_lane<mode>_internal): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, VD_HSI: New
	define_insn.
	(aarch64_sqdml<SBINQOPS:as>l_laneq<mode>_internal, SD_HSI): Likewise.
	(aarch64_sqdml<SBINQOPS:as>l2_laneq<mode>_internal): Likewise.
	(aarch64_sqdmull_laneq<mode>_internal, VD_HSI): Likewise.
	(aarch64_sqdmull_laneq<mode>_internal, SD_HSI): Likewise.
	(aarch64_sqdmull2_laneq<mode>_internal): Likewise.
	(aarch64_sqdmlal_lane<mode>): Change mode attribute of penultimate
	operand to VCOND.  Update lane flipping and bounds checking logic.
	(aarch64_sqdmlal2_lane<mode>): Likewise.
	(aarch64_sqdmlsl_lane<mode>): Likewise.
	(aarch64_sqdmull_lane<mode>): Likewise.
	(aarch64_sqdmull2_lane<mode>): Likewise.
	(aarch64_sqdmlal_laneq<mode>):
	Replace VCON usage with VCONQ.
	Emit aarch64_sqdmlal_laneq<mode>_internal insn.
	(aarch64_sqdmlal2_laneq<mode>): Emit
	aarch64_sqdmlal2_laneq<mode>_internal insn.
	Replace VCON with VCONQ.
	(aarch64_sqdmlsl2_lane<mode>): Replace VCON with VCONQ.
	(aarch64_sqdmlsl2_laneq<mode>): Likewise.
	(aarch64_sqdmull_laneq<mode>): Emit
	aarch64_sqdmull_laneq<mode>_internal insn.
	Replace VCON with VCONQ.
	(aarch64_sqdmull2_laneq<mode>): Emit
	aarch64_sqdmull2_laneq<mode>_internal insn.
	(aarch64_sqdmlsl_laneq<mode>): Replace VCON usage with VCONQ.
	* config/aarch64/arm_neon.h (vqdmlal_high_lane_s16): Change type
	of 3rd argument to int16x4_t.
	(vqdmlalh_lane_s16): Likewise.
	(vqdmlslh_lane_s16): Likewise.
	(vqdmull_high_lane_s16): Likewise.
	(vqdmullh_lane_s16): Change type of 2nd argument to int16x4_t.
	(vqdmlal_lane_s16): Don't create temporary int16x8_t value.
	(vqdmlsl_lane_s16): Likewise.
	(vqdmull_lane_s16): Don't create temporary int16x8_t value.
	(vqdmlal_high_lane_s32): Change type 3rd argument to int32x2_t.
	(vqdmlals_lane_s32): Likewise.
	(vqdmlsls_lane_s32): Likewise.
	(vqdmull_high_lane_s32): Change type 2nd argument to int32x2_t.
	(vqdmulls_lane_s32): Likewise.
	(vqdmlal_lane_s32): Don't create temporary int32x4_t value.
	(vqdmlsl_lane_s32): Likewise.
	(vqdmull_lane_s32): Don't create temporary int32x4_t value.
	(vqdmulhh_lane_s16): Change type of second argument to int16x4_t.
	(vqrdmulhh_lane_s16): Likewise.
	(vqdmlsl_high_lane_s16): Likewise.
	(vqdmulhs_lane_s32): Change type of second argument to int32x2_t.
	(vqdmlsl_high_lane_s32): Likewise.
	(vqrdmulhs_lane_s32): Likewise.

[gcc/testsuite]
	* gcc.target/aarch64/simd/vqdmulhh_lane_s16.c: New test.
	* gcc.target/aarch64/simd/vqdmulhs_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhh_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhs_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_high_lane_s16.c: New test.
	* gcc.target/aarch64/simd/vqdmlal_high_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_high_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_high_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlal_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlalh_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlals_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_high_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_high_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_high_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsl_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlslh_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmlsls_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulh_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulh_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulhq_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulhq_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_high_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_high_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_high_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_high_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmull_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqdmullh_lane_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqdmulls_lane_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulh_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulh_laneq_s32.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhq_laneq_s16.c: Likewise.
	* gcc.target/aarch64/simd/vqrdmulhq_laneq_s32.c: Likewise.
	* gcc.target/aarch64/vector_intrinsics.c: Simplify arm_neon.h include.
	(test_vqdmlal_high_lane_s16): Fix parameter type.
	(test_vqdmlal_high_lane_s32): Likewise.
	(test_vqdmull_high_lane_s16): Likewise.
	(test_vqdmull_high_lane_s32): Likewise.
	(test_vqdmlsl_high_lane_s32): Likewise.
	(test_vqdmlsl_high_lane_s16): Likewise.
	* gcc.target/aarch64/scalar_intrinsics.c (test_vqdmlalh_lane_s16):
	Fix argument type.
	(test_vqdmlals_lane_s32): Likewise.
	(test_vqdmlslh_lane_s16): Likewise.
	(test_vqdmlsls_lane_s32): Likewise.
	(test_vqdmulhh_lane_s16): Likewise.
	(test_vqdmulhs_lane_s32): Likewise.
	(test_vqdmullh_lane_s16): Likewise.
	(test_vqdmulls_lane_s32): Likewise.
	(test_vqrdmulhh_lane_s16): Likewise.
	(test_vqrdmulhs_lane_s32): Likewise.

From-SVN: r211842
2014-06-20 08:51:34 +00:00
Tom de Vries 6621ab6860 Fix finding reg-sets of call insn
2014-06-20  Tom de Vries  <tom@codesourcery.com>

	* final.c (collect_fn_hard_reg_usage): Add separate IOR_HARD_REG_SET for
	get_call_reg_set_usage.

From-SVN: r211841
2014-06-20 08:02:02 +00:00
Tom de Vries 5fea818693 Don't save function_used_regs if it contains all call_used_regs
2014-06-20  Tom de Vries  <tom@codesourcery.com>

	* final.c (collect_fn_hard_reg_usage): Don't save function_used_regs if
	it contains all call_used_regs.

From-SVN: r211840
2014-06-20 08:01:52 +00:00
Tom de Vries 53f2f6c1c4 Use function_used_regs variable in collect_fn_hard_reg_usage
2014-06-20  Tom de Vries  <tom@codesourcery.com>

	* final.c (collect_fn_hard_reg_usage): Add and use variable
	function_used_regs.

From-SVN: r211839
2014-06-20 08:01:41 +00:00
Jan Hubicka 569b1784fe cgraph.h (struct symtab_node): Add field in_init_priority_hash (set_init_priority...
* cgraph.h (struct symtab_node): Add field in_init_priority_hash
	(set_init_priority, get_init_priority, set_fini_priority,
	get_fini_priority): New methods.
	* tree.c (init_priority_for_decl): Remove.
	(init_ttree): Do not initialize init priority.
	(decl_init_priority_lookup, decl_fini_priority_lookup): Rewrite.
	(decl_priority_info): Remove.
	(decl_init_priority_insert): Rewrite.
	(decl_fini_priority_insert): Rewrite.
	* tree.h (tree_priority_map_eq, tree_priority_map_hash,
	tree_priority_map_marked_p): Remove.
	* lto-cgraph.c (lto_output_node, input_node): Stream init priorities.
	* lto-streamer-out.c (hash_tree): Do not hash priorities.
	* tree-streamer-out.c (pack_ts_decl_with_vis_value_fields): Do
	not output priorities.
	(pack_ts_function_decl_value_fields): Likewise.
	* tree-streamer-in.c (unpack_ts_decl_with_vis_value_fields): Do
	not input priorities.
	(unpack_ts_function_decl_value_fields): Likewise.
	* symtab.c (symbol_priority_map): Declare.
	(init_priority_hash): Declare.
	(symtab_unregister_node): Unregister from priority hash, too.
	(symtab_node::get_init_priority, cgraph_node::get_fini_priority):
	New methods.
	(symbol_priority_map_eq, symbol_priority_map_hash): New functions.
	(symbol_priority_info): New function.
	(symtab_node::set_init_priority, cgraph_node::set_fini_priority):
	New methods.
	* tree-core.h (tree_priority_map): Remove.

	* lto.c (compare_tree_sccs_1): Do not compare priorities.

From-SVN: r211838
2014-06-20 07:09:27 +00:00
Jakub Jelinek 88f5cfcd2b tree-ssa-math-opts.c (do_shift_rotate, [...]): Cast 0xff to uint64_t before shifting it up.
* tree-ssa-math-opts.c (do_shift_rotate, find_bswap_or_nop_1): Cast
	0xff to uint64_t before shifting it up.

From-SVN: r211837
2014-06-20 08:30:19 +02:00
Julian Brown 6d45574aa2 arm.c (arm_output_mi_thunk): Fix offset for TARGET_THUMB1_ONLY.
2014-06-20  Julian Brown  <julian@codesourcery.com>
	    Chung-Lin Tang  <cltang@codesourcery.com>

	* config/arm/arm.c (arm_output_mi_thunk): Fix offset for
	TARGET_THUMB1_ONLY. Add comments.


Co-Authored-By: Chung-Lin Tang <cltang@codesourcery.com>

From-SVN: r211834
2014-06-20 05:38:40 +00:00
Tom de Vries d07a3fed35 Fix aarch64_emit_call_insn return type
2014-06-19  Tom de Vries  <tom@codesourcery.com>

	* config/aarch64/aarch64-protos.h (aarch64_emit_call_insn): Change
	return type to void.
	* config/aarch64/aarch64.c (aarch64_emit_call_insn): Same.

From-SVN: r211823
2014-06-19 12:21:13 +00:00
Zhenqiang Chen 61fc05c74a loop-invariant.c (get_inv_cost): Skip invariants, which are marked as "move", from depends_on.
2014-06-19  Zhenqiang Chen  <zhenqiang.chen@linaro.org>

	* loop-invariant.c (get_inv_cost): Skip invariants, which are marked
	as "move", from depends_on.

From-SVN: r211818
2014-06-19 09:04:58 +00:00
Terry Guo dbb73879ff thumb1.md (define_split): Split 64bit constant in earlier stage.
gcc/ChangeLog:

2014-06-19  Terry Guo  <terry.guo@arm.com>

	* config/arm/thumb1.md (define_split): Split 64bit constant in earlier
	stage.

gcc/testsuite/ChangeLog:

2014-06-19  Terry Guo  <terry.guo@arm.com>

	* gcc.target/arm/thumb1-load-64bit-constant-1.c: New test.
	* gcc.target/arm/thumb1-load-64bit-constant-2.c: Ditto.
	* gcc.target/arm/thumb1-load-64bit-constant-3.c: Ditto.

From-SVN: r211817
2014-06-19 07:50:48 +00:00
Segher Boessenkool 36bd0c3e42 rs6000: Make cr5 allocatable
A comment in rs6000.h says "cr5 is not supposed to be used".  I checked
all ABIs, going as far back as PowerOpen (1994), and found no mention
of this.

Also document cr6 is used by some vector instructions.

From-SVN: r211811
2014-06-19 01:13:40 +02:00
Kaz Kojima be6b0becc0 re PR target/61550 ([SH] build failure with ICE in gen_reg_rtx, at emit-rtl.c:943)
PR target/61550
	* config/sh/sh.c (prepare_move_operands): Don't process TLS
	addresses here if reload in progress or completed.

From-SVN: r211807
2014-06-18 22:11:55 +00:00
Robert Suchanek a78cc31452 Enable LRA for MIPS
gcc/

	* config/mips/constraints.md ("d"): BASE_REG_CLASS replaced by
	"TARGET_MIPS16 ? M16_REGS : GR_REGS".
	* config/mips/mips.c (mips_regno_to_class): Update for M16_SP_REGS.
	(mips_regno_mode_ok_for_base_p): Remove use of !strict_p for MIPS16.
	(mips_register_priority): New function that implements the target
	hook TARGET_REGISTER_PRIORITY.
	(mips_spill_class): Likewise for TARGET_SPILL_CLASS.
	(mips_lra_p): Likewise for TARGET_LRA_P.
	(TARGET_REGISTER_PRIORITY): Define macro.
	(TARGET_SPILL_CLASS): Likewise.
	(TARGET_LRA_P): Likewise.
	* config/mips/mips.h (reg_class): Add M16_SP_REGS and SPILL_REGS
	classes.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(BASE_REG_CLASS): Use M16_SP_REGS.
	* config/mips/mips.md (*mul_acc_si): Add alternative tuned for LRA.
	New set attribute to enable alternatives depending on the register
	allocator used.
	(*mul_acc_si_r3900, *mul_sub_si): Likewise.
	(*lea64): Disable pattern for MIPS16.
	* config/mips/mips.opt (mlra): New option.

From-SVN: r211805
2014-06-18 20:40:34 +00:00
Uros Bizjak 30256befe1 ChangeLog: Fix whitespace.
* ChangeLog: Fix whitespace.
	* testsuite/ChangeLog: Fix invalid entry.

From-SVN: r211804
2014-06-18 22:14:08 +02:00
Robert Suchanek c31d2d11a9 Add support for reloading a frame address with an invalid base
gcc/

	* lra-constraints.c (base_to_reg): New function.
	(process_address): Use new function.

From-SVN: r211802
2014-06-18 19:50:00 +00:00
Tom de Vries 786077082e -fuse-caller-save - Enable for AArch64
2014-05-30  Tom de Vries  <tom@codesourcery.com>

	* config/aarch64/aarch64-protos.h (aarch64_emit_call_insn): Declare.
	* config/aarch64/aarch64.c
	(TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS): Redefine as true.
	(aarch64_emit_call_insn): New function.
	(aarch64_load_symref_appropriately): Use aarch64_emit_call_insn instead
	of emit_call_insn.
	* config/aarch64/aarch64.md (define_expand "call_internal")
	(define_expand "call_value_internal", define_expand "sibcall_internal")
	(define_expand "sibcall_value_internal"): New.
	(define_expand "call", define_expand "call_value")
	(define_expand "sibcall", define_expand "sibcall_value"): Use internal
	expand variant and aarch64_emit_call_insn.

	* gcc.target/aarch64/fuse-caller-save.c: New test.

From-SVN: r211799
2014-06-18 16:09:01 +00:00
Radovan Obradovic 7a32d6c491 -fuse-caller-save - Enable for ARM
2014-06-18  Radovan Obradovic  <robradovic@mips.com>
            Tom de Vries  <tom@codesourcery.com>

	* config/arm/arm-protos.h (arm_emit_call_insn): Add bool parameter.
	* config/arm/arm.c (TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS):
	Redefine to true.
	(arm_emit_call_insn): Add and use sibcall parameter.  Add IP and CC
	clobbers to CALL_INSN_FUNCTION_USAGE.
	(define_expand "sibcall_internal")
	(define_expand "sibcall_value_internal"): New.
	(define_expand "call", define_expand "call_value"): Add argument to
	arm_emit_call_insn.
	(define_expand "sibcall"): Use sibcall_internal and arm_emit_call_insn.
	(define_expand "sibcall_value"): Use sibcall_value_internal and
	arm_emit_call_insn.

	* gcc.target/arm/fuse-caller-save.c: New test.

Co-Authored-By: Tom de Vries <tom@codesourcery.com>

From-SVN: r211798
2014-06-18 15:50:59 +00:00
Charles Baylis 4b9fcb37ba bpabi.c (__gnu_uldivmod_helper): Remove.
2014-06-18  Charles Baylis  <charles.baylis@linaro.org>

	* config/arm/bpabi.c (__gnu_uldivmod_helper): Remove.

From-SVN: r211797
2014-06-18 15:44:45 +00:00
Charles Baylis a7a7d3c8f0 bpabi-v6m.S (__aeabi_uldivmod): Perform division using __udivmoddi4.
2014-06-18  Charles Baylis  <charles.baylis@linaro.org>

	* config/arm/bpabi-v6m.S (__aeabi_uldivmod): Perform division using
	__udivmoddi4.

From-SVN: r211796
2014-06-18 15:44:10 +00:00
Charles Baylis 158ef346fd bpabi.S (__aeabi_ldivmod, [...]): Use .cfi_* directives for DWARF annotations.
2014-06-18  Charles Baylis  <charles.baylis@linaro.org>

	* config/arm/bpabi.S (__aeabi_ldivmod, __aeabi_uldivmod,
	push_for_divide, pop_for_divide): Use .cfi_* directives for DWARF
	annotations. Fix DWARF information.

From-SVN: r211795
2014-06-18 15:43:35 +00:00