2018-09-03 Martin Liska <mliska@suse.cz>
PR driver/83193
* common/common-target.def: Add TARGET_GET_VALID_OPTION_VALUES.
* common/common-targhooks.c (default_get_valid_option_values):
New function.
* common/common-targhooks.h (default_get_valid_option_values):
Likewise.
* common/config/i386/i386-common.c: Move processor_target_table
from i386.c.
(ix86_get_valid_option_values): New function.
(TARGET_GET_VALID_OPTION_VALUES): New macro.
* config/i386/i386.c (struct ptt): Move to i386-common.c.
(PTA_*): Move all defined masks into i386-common.c.
(ix86_function_specific_restore): Use new processor_cost_table.
* config/i386/i386.h (struct ptt): Moved from i386.c.
(struct pta): Likewise.
* doc/tm.texi: Document new TARGET_GET_VALID_OPTION_VALUES.
* doc/tm.texi.in: Likewise.
* opt-suggestions.c (option_proposer::suggest_option):
Pass prefix to build_option_suggestions.
(option_proposer::get_completions): Likewise.
(option_proposer::build_option_suggestions): Use the new target
hook.
* opts.c (struct option_help_tuple): New struct.
(print_filtered_help): Use the new target hook.
2018-09-03 Martin Liska <mliska@suse.cz>
PR driver/83193
* gcc.dg/completion-4.c: New test.
From-SVN: r264052
/cp
2018-09-03 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/84980
* constraint.cc (finish_shorthand_constraint): Early return if the
constraint is erroneous.
/testsuite
2018-09-03 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/84980
* g++.dg/concepts/pr84980.C: New.
From-SVN: r264051
2018-09-03 Martin Liska <mliska@suse.cz>
PR middle-end/59521
* predict.c (set_even_probabilities): Add likely_edges
argument and handle cases where we have precisely one
likely edge.
(combine_predictions_for_bb): Catch also likely_edges.
(tree_predict_by_opcode): Handle gswitch statements.
* tree-cfg.h (find_case_label_for_value): New declaration.
(find_taken_edge_switch_expr): Likewise.
* tree-switch-conversion.c (switch_decision_tree::balance_case_nodes):
Find pivot in decision tree based on probabily, not by number of
nodes.
2018-09-03 Martin Liska <mliska@suse.cz>
PR middle-end/59521
* c-c++-common/pr59521-1.c: New test.
* c-c++-common/pr59521-2.c: New test.
* gcc.dg/tree-prof/pr59521-3.c: New test.
From-SVN: r264050
2018-09-01 Jerry DeLisle <jvdelisle@gcc.gnu.org>
* io/io.h: Change declaration of vlist type to
gfc_full_array_i4 to eliminate warning for mismatched type.
* io/format.c ((parse_format_list): Use gfc_full_array_i4.
* io/io.h: Use gfc_full_array_i4.
From-SVN: r264043
2018-08-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/87168
* tree-ssa-sccvn.c (SSA_VAL): Add visited output parameter.
(rpo_elim::eliminate_avail): When OP was not visited it must
be available.
* gcc.dg/torture/pr87168.c: New testcase.
From-SVN: r264021
2018-08-31 Martin Liska <mliska@suse.cz>
* ipa-icf.c (sem_item::add_type): Use
sem_item::m_type_hash_cache.
* ipa-icf.h: Move the cache from sem_item_optimizer
to sem_item.
From-SVN: r264014
TARGET_FPRND should be on for everything ISA 2.04 and later, and
TARGET_VSX implies ISA 2.06 or later; but it is possible to disable
TARGET_FPRND (separately via -mno-fprnd, but also implicitly)
currently, and then things fall down. This patch makes things not
fall down.
PR target/86684
PR target/87149
* config/rs6000/rs6000.md (lround<mode>di2): Gate on TARGET_FPRND.
From-SVN: r264011
2018-08-31 Paul Thomas <pault@gcc.gnu.org>
PR fortran/86328
PR fortran/86760
* trans-array.c (gfc_conv_scalarized_array_ref): Do not fix
info->descriptor but pass it directly to gfc_build_array_ref.
(gfc_conv_array_ref): Likewise for se->expr.
* trans.c (gfc_build_array_ref): If 'decl' is a COMPONENT_REF
obtain the span field directly from it.
2018-08-31 Paul Thomas <pault@gcc.gnu.org>
PR fortran/86328
PR fortran/86760
* gfortran.dg/pr86328.f90 : New test.
in comment 12 of the PR.
* gfortran.dg/pr86760.f90 : New test.
From-SVN: r264008
2018-08-30 Sandra Loosemore <sandra@codesourcery.com>
gcc/
* target.def (custom_function_descriptors): Improve documentation.
* doc/tm.texi.in (Trampolines): Expand discussion of function
descriptors and move TARGET_CUSTOM_FUNCTION_DESCRIPTORS to the
beginning of the section.
* doc/tm.texi: Regenerated.
From-SVN: r263999
gcc:
2018-08-30 Jose E. Marchesi <jose.marchesi@oracle.com>
* cfg.h (class auto_edge_flag): Spell out the template-id of the
base class in the initializer list. This is a workaround for
building with older GCC.
(class auto_bb_flag): Likewise.
From-SVN: r263997
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "Intel® AES New Instructions" "No".
[1] https://en.wikipedia.org/wiki/AES_instruction_set
2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.
From-SVN: r263989
For values where the result cannot be represented the shift width would
be equal to the width of the type, which is undefined. Perform two
well-defined shifts instead of one possible undefined shift.
* include/bits/hashtable_policy.h (__clp2): Fix calculation for LLP64
targets where sizeof(size_t) > sizeof(long). Avoid undefined shifts
of the number of bits in the type.
* include/std/bit (__ceil2): Avoid undefined shifts.
* testsuite/26_numerics/bit/bit.pow.two/ceil2.cc: Test values with
the most signifiant bit set.
From-SVN: r263986
* lto-streamer-out.c (DFS::DFS_write_tree_body): Do not follow
TYPE_STUB_DECL.
(hash_tree): Do not visit TYPE_STUB_DECL.
* tree-streamer-out.c (write_ts_type_common_tree_pointers): Do not
stream TYPE_STUB_DECL.
* tree-streamer-in.c (lto_input_ts_type_common_tree_pointers): Likewise.
* ipa-utils.h (type_with_linkage_p): Do not rely on TYPE_STUB_DECL
after free_lang_data.
(type_in_anonymous_namespace_p): Likewise.
From-SVN: r263985
* sreal.h (SREAL_PART_BITS): Change to 31; remove seemingly unnecessary
comment that it has to be even number.
(class sreal): Change m_sig type to int32_t.
* sreal.c (sreal::dump, sreal::to_int, opreator+, operator-): Use
int64_t for temporary calculations.
(sreal_verify_basics): Drop one bit from minimum and maximum.
From-SVN: r263981
2018-08-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/87147
* tree-ssa-sccvn.c (SSA_VISITED): New function.
(visit_phi): When the degenerate result is from the backedge and
we didn't visit its definition yet drop to VARYING.
(do_rpo_vn): Properly mark blocks with incoming backedges as executable.
* gcc.dg/torture/pr87147.c: New testcase.
From-SVN: r263980
* include/ext/pointer.h (_Pointer_adapter): Define operators for
pointer arithmetic using long long offsets.
* testsuite/ext/ext_pointer/1.cc: Test pointer arithmetic using
long long values.
From-SVN: r263976
On AArch64 we have integer modes larger than TImode, and while we can generate
moves for these they're not as efficient.
So instead make sure we limit the maximum we can copy to TImode. This means
copying a 16 byte struct will issue 1 TImode copy, which will be done using a
single STP as we expect but an CImode sized copy won't issue CImode operations.
I am also moving the residual code inside the if since smallest_mode_for_int may
trap if the mode doesn't exist. And the only time we know the mode to exist for
sure is when the condition of the if is true. This also saves repeated calls to
the iterator.
gcc/
2018-08-30 Tamar Christina <tamar.christina@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_movmem): Set TImode max.
gcc/testsuite/
2018-08-30 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/large_struct_copy_2.c: New.
From-SVN: r263974