2017-02-16 Richard Biener <rguenther@suse.de>
* graphite.h: Do not include isl/isl_val_gmp.h, instead include
isl/isl_val.h.
* graphite-isl-ast-to-gimple.c (gmp_cst_to_tree): Remove.
(gcc_expression_from_isl_expr_int): Use generic isl_val interface.
* graphite-sese-to-poly.c: Do not include isl/isl_val_gmp.h.
(isl_val_int_from_wi): New function.
(extract_affine_gmp): Rename to ...
(extract_affine_wi): ... this, take a widest_int.
(extract_affine_int): Just wrap extract_affine_wi.
(add_param_constraints): Use isl_val_int_from_wi.
(add_loop_constraints): Likewise, and extract_affine_wi.
From-SVN: r245501
2017-02-14 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-cores.def (thunderx2t99): Move to under 'C"
cores and change the partno/implementer to be correct.
(thunderx2t99p1): New core which replaces thunderx2t99 and still has
the 'B" as the implementer.
* config/aarch64/aarch64-tune.md: Regenerate.
From-SVN: r245461
gcc/ChangeLog:
2017-02-14 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000.c: Add case statement entry to make the
xvcvuxdsp built-in argument unsigned.
* config/rs6000/vsx.md: Fix the source and return operand types so they
match the instruction definitions from the ISA document. Fix typo
in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
statement.
gcc/testsuite/ChangeLog:
2017-01-14 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
xvcvsxdsp and xvcvuxdsp instructions.
From-SVN: r245460
2017-02-14 Vladimir Makarov <vmakarov@redhat.com>
PR target/79282
* lra-int.h (struct lra_operand_data, struct lra_insn_reg): Add
member early_clobber_alts.
* lra-lives.c (reg_early_clobber_p): New.
(process_bb_lives): Use it.
* lra.c (new_insn_reg): New arg early_clobber_alts. Use it.
(debug_operand_data): Initialize early_clobber_alts.
(setup_operand_alternative): Set up early_clobber_alts.
(collect_non_operand_hard_regs): Ditto. Pass early clobber
alternatives to new_insn_reg.
(add_regs_to_insn_regno_info): Add arg early_clobber_alts. Use
it.
(lra_update_insn_regno_info): Pass the new arg.
From-SVN: r245459
When converting TI store with CONST_INT to V1TI store with CONST_VECTOR
in large model, an extra instruction may be needed to load CONST_VECTOR
into a register. Insert the extra instruction to the right place.
gcc/
PR target/79498
* config/i386/i386.c (timode_scalar_chain::convert_insn): Insert
the extra instruction to the right place to store 128-bit constant
when needed.
gcc/testsuite/
PR target/79498
* gcc.target/i386/pr79498.c: New test.
From-SVN: r245438
power, power2, rios, rios1, rios2, rsc, rsc2 support was removed.
rs64a never was a supported option; it's spelled rs64.
power5+ and powerpc64le are supported options but could not be set as
default.
* config.gcc (supported_defaults) [powerpc*-*-*]: Update.
From-SVN: r245435
PR tree-optimization/79095
* tree-vrp.c (extract_range_from_binary_expr_1): For EXACT_DIV_EXPR,
if the numerator has the range ~[0,0] make the resultant range ~[0,0].
(extract_range_from_binary_expr): For MINUS_EXPR with no derived range,
if the operands are known to be not equal, then the resulting range
is ~[0,0].
(intersect_ranges): If the new range is ~[0,0] and the old range is
wide, then prefer ~[0,0].
* tree-vrp.c (overflow_comparison_p_1): New function.
(overflow_comparison_p): New function.
* tree-vrp.c (register_edge_assert_for_2): Register additional asserts
if NAME is used in an overflow test.
(vrp_evaluate_conditional_warnv_with_ops): If the ops represent an
overflow check that can be expressed as an equality test, then adjust
ops to be that equality test.
PR tree-optimization/79095
* g++.dg/pr79095-1.C: New test
* g++.dg/pr79095-2.C: New test
* g++.dg/pr79095-3.C: New test
* g++.dg/pr79095-4.C: New test
* g++.dg/pr79095-5.C: New test
* gcc.c-torture/execute/arith-1.c: Update with more cases.
* gcc.dg/tree-ssa/pr79095-1.c: New test.
From-SVN: r245434
With the target attribute stuff the only user of the builtin types
flags value has been removed. So drop that value from the builtin
types list entirely.
gcc/ChangeLog:
2017-02-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/s390/s390-builtin-types.def: Remove flags argument.
* config/s390/s390.c (s390_init_builtins): Likewise.
From-SVN: r245432
2017-02-14 Amit Pawar <amit.pawar@amd.com>
* config/i386/i386.c (znver1_cost): Fix the alignment for function and
max skip bytes for function, loop and jump.
From-SVN: r245423
PR tree-optimization/79408
* tree-vrp.c (simplify_div_or_mod_using_ranges): Handle also the
case when on TRUNC_MOD_EXPR op0 is INTEGER_CST.
(simplify_stmt_using_ranges): Call simplify_div_or_mod_using_ranges
also if rhs1 is INTEGER_CST.
* gcc.dg/tree-ssa/pr79408-2.c: New test.
From-SVN: r245420
2017-02-14 Richard Biener <rguenther@suse.de>
PR middle-end/79432
* tree-into-ssa.c (insert_phi_nodes): When the function can
have abnormal edges rewrite SSA names with broken use-def
dominance out of SSA and register them for PHI insertion.
* gcc.dg/torture/pr79432.c: New testcase.
From-SVN: r245417
PR rtl-optimization/79388
PR rtl-optimization/79450
* combine.c (distribute_notes): When removing TEM_INSN for which
corresponding dest has last value recorded, invalidate that last
value.
* gcc.c-torture/execute/pr79388.c: New test.
* gcc.c-torture/execute/pr79450.c: New test.
From-SVN: r245390
PR ipa/79224
* ipa-inline-analysis.c (get_minimal_bb): New function.
(record_modified): Use it.
(remap_edge_change_prob): Handle also ancestor functions.
From-SVN: r245357
PR middle-end/79454
* internal-fn.c (expand_vector_ubsan_overflow): Use piece-wise
result computation whenever lhs doesn't have vector mode, not
just when it has BLKmode.
From-SVN: r245354
Richard Biener
Jeff Law
Martin Sebor
Bin Cheng
Thomas Schwinge
Jakub Jelinek
Dominik Vogt
Andrew Pinski
Carl Love
Vladimir Makarov
Uros Bizjak
H.J. Lu
Segher Boessenkool
Andreas Krebbel
Martin Liska
James Greenhalgh
Kyrylo Tkachov
Amit Pawar
Prathamesh Kulkarni
Aaron Sawdey
Jakub Jelinek
Nathan Sidwell
Gerald Pfeifer
Sandra Loosemore
Jan Hubicka