Presently sys/sysmacros.h is entirely defined in sysdeps. This would
mean that the deprecation logic coming up in the next patch would have
to be written twice (in generic/ and unix/sysv/linux/). To avoid that,
hoist all but the unavoidably system-dependent logic to misc/, leaving a
bits/ header behind. This also promotes the Linux-specific encoding of
dev_t, which accommodates 32-bit major and minor numbers in a 64-bit dev_t,
to generic, as glibc's dev_t is always 64 bits wide.
The former Linux implementation used inline functions to avoid evaluating
arguments more than once. After this change, all platforms use inline
functions, which means that three new symbols are added to the generic ABI.
(These symbols are in the user namespace, which is how they have always
been on Linux. They begin with "gnu_dev_", so collisions with user code
are pretty unlikely.)
New ports henceforth need only provide a bits/sysmacros.h defining
internal macros __SYSMACROS_{DECLARE,DEFINE}_{MAJOR,MINOR,MAKEDEV}.
This is only necessary if the kernel encoding is incompatible with
the now-generic encoding (for instance, it would be necessary for
FreeBSD).
While I was at it, I added a basic round-trip test for these functions.
* sysdeps/generic/sys/sysmacros.h: Delete file.
* sysdeps/unix/sysv/linux/makedev.c: Delete file.
* sysdeps/unix/sysv/linux/sys/sysmacros.h: Move file ...
* bits/sysmacros.h: ... here; this encoding is now the generic
encoding. Now defines only the following macros:
__SYSMACROS_DECLARE_MAJOR, __SYSMACROS_DEFINE_MAJOR,
__SYSMACROS_DECLARE_MINOR, __SYSMACROS_DEFINE_MINOR,
__SYSMACROS_DECLARE_MAKEDEV, __SYSMACROS_DEFINE_MAKEDEV.
* misc/sys/sysmacros.h, misc/makedev.c: New files that use
bits/sysmacros.h and the above new macros to generate the
public implementations of major, minor, and makedev.
* misc/tst-makedev.c: New test.
* include/sys/sysmacros.h: New wrapper.
* misc/Makefile (headers): Add sys/sysmacros.h, bits/sysmacros.h.
(routines): Add makedev.
(tests): Add tst-makedev.
* misc/Versions [GLIBC_2.25]: Add gnu_dev_major, gnu_dev_minor,
gnu_dev_makedev.
* posix/Makefile (headers): Remove sys/sysmacros.h.
* sysdeps/unix/sysv/linux/Makefile (sysdep_routines): Remove makedev.
* sysdeps/arm/nacl/libc.abilist: Add GLIBC_2.25,
gnu_dev_major, gnu_dev_makedev, gnu_dev_minor.
* sysdeps/unix/sysv/linux/aarch64/libc.abilist
* sysdeps/unix/sysv/linux/alpha/libc.abilist
* sysdeps/unix/sysv/linux/arm/libc.abilist
* sysdeps/unix/sysv/linux/hppa/libc.abilist
* sysdeps/unix/sysv/linux/i386/libc.abilist
* sysdeps/unix/sysv/linux/ia64/libc.abilist
* sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist
* sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist
* sysdeps/unix/sysv/linux/microblaze/libc.abilist
* sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist
* sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist
* sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist
* sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist
* sysdeps/unix/sysv/linux/nios2/libc.abilist
* sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist
* sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist
* sysdeps/unix/sysv/linux/powerpc/powerpc64/libc-le.abilist
* sysdeps/unix/sysv/linux/powerpc/powerpc64/libc.abilist
* sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist
* sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist
* sysdeps/unix/sysv/linux/sh/libc.abilist
* sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist
* sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx32/libc.abilist
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx64/libc.abilist
* sysdeps/unix/sysv/linux/tile/tilepro/libc.abilist
* sysdeps/unix/sysv/linux/x86_64/64/libc.abilist
* sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist:
Add GLIBC_2.25.
There is quiet truncation to double arithmetic in several
files. I noticed them when building ldbl-128 in a
soft-fp context. This did not change any test results.
Instead of a flag which indicates the pointer can be freed, dtv_t
now includes the pointer which should be freed. Due to padding,
the size of dtv_t does not increase.
To avoid using memalign, the new allocate_dtv_entry function
allocates a sufficiently large buffer so that a sub-buffer
can be found in it which starts with an aligned pointer. Both
the aligned and original pointers are kept, the latter for calling
free later.
This patch adds the new UDP_ENCAP_GTP0 and UDP_ENCAP_GTP1U from Linux
4.7 to sysdeps/gnu/netinet/udp.h.
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by the patch).
* sysdeps/gnu/netinet/udp.h (UDP_ENCAP_GTP0): New macro.
(UDP_ENCAP_GTP1U): Likewise.
This patch adds the new PF_QIPCRTR and AF_QIPCRTR from Linux 4.7 to
sysdeps/unix/sysv/linux/bits/socket.h.
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by the patch).
* sysdeps/unix/sysv/linux/bits/socket.h (PF_QIPCRTR): New macro.
(PF_MAX): Update value.
(AF_QIPCRTR): New macro.
sparc64 passes floating point values in the floating point registers.
As the the generic ceil, floor and trunc functions use integer
instructions, it makes sense to provide a VIS3 version consisting in
the the generic version compiled with -mvis3. GCC will then use
movdtox, movxtod, movwtos and movstow instructions.
sparc32 passes the floating point values in the integer registers, so it
doesn't make sense to do the same.
Changelog:
* sysdeps/ieee754/dbl-64/s_trunc.c: Avoid alias renamed.
* sysdeps/ieee754/dbl-64/wordsize-64/s_trunc.c: Likewise.
* sysdeps/ieee754/flt-32/s_truncf.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/Makefile
[$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines):
Add s_ceilf-vis3, s_ceil-vis3, s_floorf-vis3, s_floor-vis3,
s_truncf-vis3, s_trunc-vis3.
(CFLAGS-s_ceilf-vis3.c): New. Set to -Wa,-Av9d -mvis3.
(CFLAGS-s_ceil-vis3.c): Likewise.
(CFLAGS-s_floorf-vis3.c): Likewise.
(CFLAGS-s_floor-vis3.c): Likewise.
(CFLAGS-s_truncf-vis3.c): Likewise.
(CFLAGS-s_trunc-vis3.c): Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.c: New file.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floor.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.c: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.c: Likewise.
As pointer out on the mailing list, the inline assembly code in
sysdeps/powerpc/ifunc-sel.h doesn't have a list of clobbered registers
and used wrong constraints.
This patch fixes that. I verified it doesn't introduce any change in the
generated code.
Changelog:
* sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Add "11", "12", "cr0" to the
clobber list. Use "i" constraint instead of "X".
(ifunc_one): Add "12" to the clobber list. Use "i" constraint instead
of "X".
On 32-bit PowerPC GCC 6 always saves the PIC register on the stack in
the prologue and adjust the stack in the epilogue. It is therefore not
possible anymore to just exit the function in the inline asm code,
otherwise it corrupts the stack pointer. This causes the following tests
to fail when using GCC 6:
FAIL: elf/ifuncmain1
FAIL: elf/ifuncmain1pic
FAIL: elf/ifuncmain1picstatic
FAIL: elf/ifuncmain1pie
FAIL: elf/ifuncmain1staticpic
FAIL: elf/ifuncmain1staticpie
FAIL: elf/ifuncmain1vis
FAIL: elf/ifuncmain1vispic
FAIL: elf/ifuncmain1vispie
FAIL: elf/ifuncmain2pic
FAIL: elf/ifuncmain2picstatic
FAIL: elf/ifuncmain3
FAIL: elf/ifuncmain4picstatic
FAIL: elf/ifuncmain5
FAIL: elf/ifuncmain5picstatic
FAIL: elf/ifuncmain5staticpic
The solution is to replace the beqlr instructions by a beq to the end
of the inline asm code. This fixes all the above failures.
ChangeLog:
* sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Replace beqlr instructions
by beq instructions jumping to the end of the function.
The alpha specific version of trunc and truncf always add and subtract
0x1.0p23 or 0x1.0p52 even for big values. This causes this kind of
errors in the testsuite:
Failure: Test: trunc_towardzero (0x1p107)
Result:
is: 1.6225927682921334e+32 0x1.fffffffffffffp+106
should be: 1.6225927682921336e+32 0x1.0000000000000p+107
difference: 1.8014398509481984e+16 0x1.0000000000000p+54
ulp : 0.5000
max.ulp : 0.0000
Change this by returning the input value when its absolute value is
greater than 0x1.0p23 or 0x1.0p52. NaN have to go through the add and
subtract operations to get possibly silenced.
Finally remove the code to handle inexact exception, trunc should never
generate such an exception.
Changelog:
* sysdeps/alpha/fpu/s_trunc.c (__trunc): Return the input value
when its absolute value is greater than 0x1.0p52.
[_IEEE_FP_INEXACT] Remove.
* sysdeps/alpha/fpu/s_truncf.c (__truncf): Return the input value
when its absolute value is greater than 0x1.0p23.
[_IEEE_FP_INEXACT] Remove.
The alpha version of rint wrongly return sNaN for sNaN input. Fix that
by checking for NaN and by returning the input value added with itself
in that case.
Changelog:
* sysdeps/alpha/fpu/s_rint.c (__rint): Add argument with itself
when it is a NaN.
* sysdeps/alpha/fpu/s_rintf.c (__rintf): Likewise.
The alpha version of floor wrongly return sNaN for sNaN input. Fix that
by checking for NaN and by returning the input value added with itself
in that case.
Finally remove the code to handle inexact exception, floor should never
generate such an exception.
Changelog:
* sysdeps/alpha/fpu/s_floor.c (__floor): Add argument with itself
when it is a NaN.
[_IEEE_FP_INEXACT] Remove.
* sysdeps/alpha/fpu/s_floorf.c (__floorf): Likewise.
The alpha version of ceil wrongly return sNaN for sNaN input. Fix that
by checking for NaN and by returning the input value added with itself
in that case.
Finally remove the code to handle inexact exception, ceil should never
generate such an exception.
Changelog:
* sysdeps/alpha/fpu/s_ceil.c (__ceil): Add argument with itself
when it is a NaN.
[_IEEE_FP_INEXACT] Remove.
* sysdeps/alpha/fpu/s_ceilf.c (__ceilf): Likewise.
The ceil, floor and trunc functions on sparc do not fully follow the
standard and trigger an inexact exception when presented a value which
is not an integer. Since glibc 2.24 this causes a few tests to fail,
for instance:
testing double (without inline functions)
Failure: ceil (lit_pi): Exception "Inexact" set
Failure: ceil (-lit_pi): Exception "Inexact" set
Failure: ceil (min_subnorm_value): Exception "Inexact" set
Failure: ceil (min_value): Exception "Inexact" set
Failure: ceil (0.1): Exception "Inexact" set
Failure: ceil (0.25): Exception "Inexact" set
Failure: ceil (0.625): Exception "Inexact" set
Failure: ceil (-min_subnorm_value): Exception "Inexact" set
Failure: ceil (-min_value): Exception "Inexact" set
Failure: ceil (-0.1): Exception "Inexact" set
Failure: ceil (-0.25): Exception "Inexact" set
Failure: ceil (-0.625): Exception "Inexact" set
I tried to fix that by using the same strategy than used on other
architectures, that is by saving the FSR register at the beginning
and restoring it at the end of the function. When doing so I noticed
a comment that this operation might be very costly, so I decided to
do some benchmarks.
The benchmarks below represent the time required to run each of the
function 60 millions of times with different input value. I have done
that in the basic V9 code, the VIS2 code, and using the default C
implementation of the libc, for both sparc32 and sparc64, on a Niagara
T1 based machine and an UltraSparc IIIi. Given I don't have access to a
more recent machine), I haven't been able to test the VIS3 version. Also
it should be noted that it doesn't make sense to do this benchmark for
V8 or earlier as in that case we use the default C implementation. The
results are available in the table below, the "+ fix" version correspond
to the one saving and restoring the FSR.
Niagara T1 / sparc32
--------------------
ceilf ceil floorf floor truncf trunc
V9 19.10 22.48 19.10 22.48 16.59 19.27
V9 + fix 19.77 23.34 19.77 23.33 17.27 20.12
VIS2 16.87 19.62 16.87 19.62
VIS2 + fix 17.55 20.47 17.55 20.47
C impl 11.39 13.80 11.40 13.80 10.88 10.84
Niagara T1 / sparc64
--------------------
ceilf ceil floorf floor truncf trunc
V9 18.14 22.23 18.14 22.23 15.64 19.02
V9 + fix 18.82 23.08 18.82 23.08 16.32 19.87
VIS2 15.92 19.37 15.92 19.37
VIS2 + fix 16.59 20.22 16.59 20.22
C impl 11.39 13.60 11.39 15.36 10.88 12.65
UltraSparc IIIi / sparc32
-------------------------
ceilf ceil floorf floor truncf trunc
V9 4.81 7.09 6.61 11.64 4.91 7.05
V9 + fix 7.20 10.42 7.14 10.54 6.76 9.47
VIS2 4.81 7.03 4.76 7.13
VIS2 + fix 6.76 9.51 6.71 9.63
C impl 3.88 8.62 3.90 9.45 3.57 6.62
UltraSparc IIIi / sparc64
-------------------------
ceilf ceil floorf floor truncf trunc
V9 3.48 4.39 3.48 4.41 3.01 3.85
V9 + fix 4.76 5.90 4.76 5.90 4.86 6.26
VIS2 2.95 3.61 2.95 3.61
VIS2 + fix 4.24 5.37 4.30 7.97
C impl 3.63 4.89 3.62 6.38 3.33 4.03
The first thing that should be noted is that the C implementation is
always faster on the Niagara T1 based machine. On the UltraSparc IIIi
the float version on sparc32 is also faster.
Coming back about the fix saving and restoring the FSR, it appears
it has a big impact as expected. In that case the C implementation is
always faster than the fixed implementations.
This patch therefore removes the sparc specific implementations in
favor of the generic ones.
Changelog:
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile
[$(subdir) = math] (libm-sysdep_routines): Remove.
[$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines):
Remove s_ceilf-vis3, s_ceil-vis3, s_floorf-vis3, s_floor-vis3,
s_truncf-vis3, s_trunc-vis3.
* sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S: Delete
file.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_floor.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_floorf.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S: Likewise.
* sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S: Likewise.
* sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_ceil.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_ceilf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_floor.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_floorf.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_trunc.S: Likewise.
* sysdeps/sparc/sparc64/fpu/s_truncf.S: Likewise.
Don't compile do_test with -mavx, -mavx nor -mavx512 since they won't run
on non-AVX machines.
[BZ #20384]
* sysdeps/x86_64/fpu/Makefile (extra-test-objs): Add
test-double-libmvec-sincos-avx-main.o,
test-double-libmvec-sincos-avx2-main.o,
test-double-libmvec-sincos-main.o,
test-float-libmvec-sincosf-avx-main.o,
test-float-libmvec-sincosf-avx2-main.o and
test-float-libmvec-sincosf-main.o.
test-float-libmvec-sincosf-avx512-main.o.
($(objpfx)test-double-libmvec-sincos): Also link with
$(objpfx)test-double-libmvec-sincos-main.o.
($(objpfx)test-double-libmvec-sincos-avx): Also link with
$(objpfx)test-double-libmvec-sincos-avx-main.o.
($(objpfx)test-double-libmvec-sincos-avx2): Also link with
$(objpfx)test-double-libmvec-sincos-avx2-main.o.
($(objpfx)test-float-libmvec-sincosf): Also link with
$(objpfx)test-float-libmvec-sincosf-main.o.
($(objpfx)test-float-libmvec-sincosf-avx): Also link with
$(objpfx)test-float-libmvec-sincosf-avx2-main.o.
[$(config-cflags-avx512) == yes] (extra-test-objs): Add
test-double-libmvec-sincos-avx512-main.o and
($(objpfx)test-double-libmvec-sincos-avx512): Also link with
$(objpfx)test-double-libmvec-sincos-avx512-main.o.
($(objpfx)test-float-libmvec-sincosf-avx512): Also link with
$(objpfx)test-float-libmvec-sincosf-avx512-main.o.
(CFLAGS-test-double-libmvec-sincos.c): Removed.
(CFLAGS-test-float-libmvec-sincosf.c): Likewise.
(CFLAGS-test-double-libmvec-sincos-main.c): New.
(CFLAGS-test-double-libmvec-sincos-avx-main.c): Likewise.
(CFLAGS-test-double-libmvec-sincos-avx2-main.c): Likewise.
(CFLAGS-test-float-libmvec-sincosf-main.c): Likewise.
(CFLAGS-test-float-libmvec-sincosf-avx-main.c): Likewise.
(CFLAGS-test-float-libmvec-sincosf-avx2-main.c): Likewise.
(CFLAGS-test-float-libmvec-sincosf-avx512-main.c): Likewise.
(CFLAGS-test-double-libmvec-sincos-avx.c): Set to -DREQUIRE_AVX.
(CFLAGS-test-float-libmvec-sincosf-avx.c ): Likewise.
(CFLAGS-test-double-libmvec-sincos-avx2.c): Set to
-DREQUIRE_AVX2.
(CFLAGS-test-float-libmvec-sincosf-avx2.c ): Likewise.
(CFLAGS-test-double-libmvec-sincos-avx512.c): Set to
-DREQUIRE_AVX512F.
(CFLAGS-test-float-libmvec-sincosf-avx512.c): Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos.c: Rewritten.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c: Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx-main.c: New
file.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512-main.c:
Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-main.c:
Likewise.
This partly reverts commit f8238ae3c7
that regenerated the ulps, to make the max ulps good for gcc-5,
gcc-6 and gcc-trunk as well.
* sysdeps/aarch64/libm-test-ulps: Updated.
If the default memcpy variant is called with a length of >1MB on 31bit,
r13 is clobbered as the algorithm is switching to mvcle. The mvcle code
returns without restoring r13. All other cases are restoring r13.
If memcpy is called from outside libc the ifunc resolver will only select
this variant if running on machines older than z10.
Otherwise or if memcpy is called from inside libc, this default memcpy
variant is called.
The testcase timezone/tst-tzset is triggering this issue in some combinations
of gcc versions and optimization levels.
This bug was introduced in commit 04bb21ac93
and thus is a regression compared to former glibc 2.23 release.
This patch removes the usage of r13 at all. Thus it is not saved and restored.
The base address for execute-instruction is now stored in r5 which is obtained
after r5 is not needed anymore as 256byte block counter.
ChangeLog:
* sysdeps/s390/s390-32/memcpy.S (memcpy): Eliminate the usage
of r13 as it is not restored in mvcle case.
If a function passes in a variable named "ret", the code will miscompile
when it declares a local ret variable. In some cases, it's even a build
failure like so:
../sysdeps/unix/sysv/linux/spawni.c: In function '__spawni_child':
../sysdeps/unix/sysv/linux/spawni.c:289:5: error: address of register variable 'ret' requested
while (write_not_cancel (p, &ret, sizeof ret) < 0)
Compile i386 rtld-*.os with -mno-sse -mno-mmx -mfpmath=387 so that no
code in ld.so uses mm/xmm/ymm/zmm registers on i386 since the first 3
mm/xmm/ymm/zmm registers are used to pass vector parameters which must
be preserved.
* sysdeps/i386/Makefile (rtld-CFLAGS): New.
[subdir == elf] (CFLAGS-.os): Replace -mno-sse -mno-mmx
-mfpmath=387 with $(rtld-CFLAGS).
[subdir != elf] (CFLAGS-.os): Compile rtld-*.os with
$(rtld-CFLAGS).
During the sincos consolidation I made two mistakes, one was a logical
error due to which cos(0x1.8475e5afd4481p+0) returned
sin(0x1.8475e5afd4481p+0) instead.
The second issue was an error in negating inputs for the correct
quadrants for sine. I could not find a suitable test case for this
despite running a program to search for such an input for a couple of
hours.
Following patch fixes both issues. Tested on x86_64. Thanks to Matt
Clay for identifying the issue.
[BZ #20357]
* sysdeps/ieee754/dbl-64/s_sin.c (sloww): Fix up condition
to call __mpsin/__mpcos and to negate values.
* math/auto-libm-test-in: Add test.
* math/auto-libm-test-out: Regenerate.
This patch changes both the nptl and libc Linux raise implementation
to avoid the issues described in BZ#15368. The strategy used is
summarized in bug report first comment:
1. Block all signals (including internal NPTL ones);
2. Get pid and tid directly from syscall (not relying on cached
values);
3. Call tgkill;
4. Restore old signal mask.
Tested on x86_64 and i686.
[BZ #15368]
* sysdeps/unix/sysv/linux/nptl-signals.h
(__nptl_clear_internal_signals): New function.
(__libc_signal_block_all): Likewise.
(__libc_signal_block_app): Likewise.
(__libc_signal_restore_set): Likewise.
* sysdeps/unix/sysv/linux/pt-raise.c (raise): Use Linux raise.c
implementation.
* sysdeps/unix/sysv/linux/raise.c (raise): Reimplement to not use
the cached pid/tid value in pthread structure.
64-bit off_t in pread64, preadv, pwrite64 and pwritev syscalls is passed
in one 64-bit register for both x32 and x86-64. Since the inline
asm statement only passes long, which is 32-bit for x32, in registers,
64-bit off_t is truncated to 32-bit on x32. Since __ASSUME_PREADV and
__ASSUME_PWRITEV are defined unconditionally, these syscalls can be
implemented in syscalls.list to pass 64-bit off_t in one 64-bit register.
Tested on x86-64 and x32 with off_t > 4GB on pread64/pwrite64 and
preadv64/pwritev64.
[BZ #20348]
* sysdeps/unix/sysv/linux/x86_64/syscalls.list: Add pread64,
preadv64, pwrite64 and pwritev64.
Since _dl_tlsdesc_dynamic is called via PLT, we need to add 8 bytes for
push in the PLT entry to align the stack.
[BZ #20309]
* configure.ac (have-mtls-dialect-gnu2): Set to yes if
-mtls-dialect=gnu2 works.
* configure: Regenerated.
* elf/Makefile [have-mtls-dialect-gnu2 = yes]
(tests): Add tst-gnu2-tls1.
(modules-names): Add tst-gnu2-tls1mod.
($(objpfx)tst-gnu2-tls1): New.
(tst-gnu2-tls1mod.so-no-z-defs): Likewise.
(CFLAGS-tst-gnu2-tls1mod.c): Likewise.
* elf/tst-gnu2-tls1.c: New file.
* elf/tst-gnu2-tls1mod.c: Likewise.
* sysdeps/x86_64/dl-tlsdesc.S (_dl_tlsdesc_dynamic): Add 8
bytes for push in the PLT entry to align the stack.
Define LO_HI_LONG to skip pos_h since it is ignored by kernel:
static inline loff_t pos_from_hilo(unsigned long high, unsigned long low)
{
#define HALF_LONG_BITS (BITS_PER_LONG / 2)
return (((loff_t)high << HALF_LONG_BITS) << HALF_LONG_BITS) | low;
}
where size of loff_t == size of long.
[BZ #20349]
* sysdeps/unix/sysv/linux/x86_64/sysdep.h (LO_HI_LONG): New.
AArch64 uses HWCAP bits but they are not defined in sys/auxv.h.
This patch adds a copy of the linux v4.6 arm64 uapi asm/hwcap.h
definitions.
* sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h: New.
When glibc is built with --enable-profile, the ENTRY of
asm functions includes CALL_MCOUNT for profiling.
(matters for binaries static linked against libc_p.a.)
CALL_MCOUNT did not save/restore argument registers
around the _mcount call so it clobbered them.
(it is enough to only save/restore the arguments passed
to a given asm function, but that would be too many asm
changes so it is simpler to always save all argument
registers in this macro.)
float args are not saved: mcount does not clobber the
float regs and currently no asm function takes float
arguments anyway.
[BZ #18707]
* sysdeps/aarch64/Makefile (CFLAGS-mcount.c): Add -mgeneral-regs-only.
* sysdeps/aarch64/sysdep.h (CALL_MCOUNT): Save argument registers.
The p{read,write}v{64} consolidation patch [1] added a wrong guard
for LO_HI_LONG definition. It currently uses both
'__WORDSIZE == 64' and 'defined __ASSUME_WORDSIZE64_ILP32' to set
the value to be passed in one argument, otherwise it will be split
in two.
However it fails on MIPS64n32 where syscalls n32 uses the compat
implementation in the kernel meaning the off_t arguments are passed
in two separate registers.
GLIBC already defines a macro for such cases (__OFF_T_MATCHES_OFF64_T),
so this patch uses it instead.
Checked on x86_64, i686, x32, aarch64, armhf, and s390.
* sysdeps/unix/sysv/linux/sysdep.h
[__WORDSIZE == 64 || __ASSUME_WORDSIZE64_ILP32] (LO_HI_LONG): Remove
guards.
* misc/tst-preadvwritev-common.c: New file.
* misc/tst-preadvwritev.c: Use tst-preadvwritev-common.c.
* misc/tst-preadvwritev64.c: Use tst-preadwritev-common.c and add
a check for files larger than 2GB.
[1] 4751bbe2ad
This patch removes the __ASSUME_OFF_DIFF_OFF64 define introduced in
p{read,write} consolidation patch. This define was added based on
the idea 32 bits ports would continue to follow previous off{64}_t
definition where off_t size differs from off64_t one.
However, with recent AArch64/ILP32 patch submission and also with
discussion for RISCV kernel interface, 32 bits ports now may aim
to use off_t and off64_t with the same size as 64 bits.
So current assumption for both p{read,write} and p{read,write}v
are not compatible with new type definition. This patch now makes
the syscall wrappers to only depend on __OFF_T_MATCHES_OFF64_T to
define the default and 64-suffix variant, as follow:
<function>.c
#ifndef __OFF_T_MATCHES_OFF64_T
/* build <function> */
#endif
and
<function>64.c
/* build <function>64 */
#ifdef __OFF_T_MATCHES_OFF64_T
weak_alias (fallocate64, fallocate)
#endif
Tested on x86_64, i686, x32, and armhf.
* sysdeps/unix/sysv/linux/mips/kernel-features.h
(__ASSUME_OFF_DIFF_OFF64): Remove define.
* sysdeps/unix/sysv/linux/pread.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pread): Replace by
__OFF_T_MATCHES_OFF64_T.
* sysdeps/unix/sysv/linux/pread64.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pread64): Likewise.
* sysdeps/unix/sysv/linux/preadv.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (preadv): Likewise.
* sysdeps/unix/sysv/linux/preadv64.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (preadv64): Likewise.
* sysdeps/unix/sysv/linux/pwrite.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwrite): Likewise.
* sysdeps/unix/sysv/linux/pwrite64.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwrite64): Likewise.
* sysdeps/unix/sysv/linux/pwritev.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwritev): Likewise.
* sysdeps/unix/sysv/linux/pwritev64.c
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwritev64): Likewise.
The previous uses of this symbol were all in wordsize-32 code.
In commit eeddfa91cb ("Consolidate off_t/off64_t syscall
argument passing") it was expanded to be used in pread/pwrite.
Accordingly, we only define it in 32-bit compilation modes now.
Both tilepro and tilegx32 follow this convention for the
kernel ABI. tilegx64 follows it for passing 128-bit values,
but there are no such ABIs in the kernel.
Commit a6a4395d fixed modf implementation by compiling s_modf.c and
s_modff.c with -fsignaling-nans. However these files are also included
from the pre-POWER5+ implementation, and thus these files should also
be compiled with -fsignaling-nans.
Changelog:
[BZ #20240]
* sysdeps/powerpc/powerpc32/power4/fpu/multiarch/Makefile
(CFLAGS-s_modf-ppc32.c): New variable.
(CFLAGS-s_modff-ppc32.c): Likewise.
* sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile
(CFLAGS-s_modf-ppc64.c): Likewise.
(CFLAGS-s_modff-ppc64.c): Likewise.
On s390, the current prelink undo code in elf_machine_lazy_rel()
has the requirement, that the plt stubs use the first got slots
after the 3 reserved ones.
In case of undoing prelink, the plt got slots are reset to the correct
addresses whithin the corresponding plt-stub. Therefore the address
is calculated by the address of the first plt-stub-address which
was written by prelink (see l->l_mach.plt) to got[1] and index of
current relocation multiplied with 32 (=size of one plt slot).
The index was calculated with ¤t-got-slot - &got[3].
This patch removes the requirement, that the plt-got-slots are
starting at got[3]. The index is now calculated with
¤t-reloc - &reloc[0]. The first struct Elf64_Rela is stored
at DT_JMPREL.
This patch is needed to prepare for partial relro support.
Ulrich Weigand suggested this approach to use DT_JMPREL - Thanks.
ChangeLog:
* sysdeps/s390/linkmap.h (struct link_map_machine):
Remove member gotplt and add member jmprel.
* sysdeps/s390/s390-32/dl-machine.h
(elf_machine_runtime_setup): Setup member jmprel with DT_JMPREL
instead of gotplt with &got[3].
(elf_machine_lazy_rel): Calculate address with reloc and jmprel.
* sysdeps/s390/s390-64/dl-machine.h: Likewise.
If the input values are unaligned and if there are null characters in the
memory before the starting address of the input values, strcasecmp
gives incorrect return code. Fixed it by adding mask the bits that
are not part of the string.
In a reference to PR ld/19908 make ld.so respect symbol export classes
aka visibility and treat STV_HIDDEN and STV_INTERNAL symbols as local,
preventing such symbols from preempting exported symbols.
According to the ELF gABI[1] neither STV_HIDDEN nor STV_INTERNAL symbols
are supposed to be present in linked binaries:
"A hidden symbol contained in a relocatable object must be either
removed or converted to STB_LOCAL binding by the link-editor when the
relocatable object is included in an executable file or shared object."
"An internal symbol contained in a relocatable object must be either
removed or converted to STB_LOCAL binding by the link-editor when the
relocatable object is included in an executable file or shared object."
however some GNU binutils versions produce such symbols in some cases.
PR ld/19908 is one and we also have this note in scripts/abilist.awk:
so clearly there is linked code out there which contains such symbols
which is prone to symbol table misinterpretation, and it'll be more
productive if we handle this gracefully, under the Robustness Principle:
"be liberal in what you accept, and conservative in what you produce",
especially as this is a simple (STV_HIDDEN|STV_INTERNAL) => STB_LOCAL
mapping.
References:
[1] "System V Application Binary Interface - DRAFT - 24 April 2001",
The Santa Cruz Operation, Inc., "Symbol Table",
<http://www.sco.com/developers/gabi/2001-04-24/ch4.symtab.html>
* sysdeps/generic/ldsodefs.h
(dl_symbol_visibility_binds_local_p): New inline function.
* elf/dl-addr.c (determine_info): Treat hidden and internal
symbols as local.
* elf/dl-lookup.c (do_lookup_x): Likewise.
* elf/dl-reloc.c (RESOLVE_MAP): Likewise.
nearbyint and nearbyintf should not trigger inexact exceptions, but
should still trigger an invalid exception for a sNaN input.
The SPARC specific implementations of these functions save the FSR at
the beginning of the function and restore it at the end to not trigger
an inexact exception. This however doesn't work for an sNaN input which
need to trigger an invalid exception. Fix that by adding a fcmp
instruction using the input value before saving FSR, so that an invalid
exception is triggered for a sNaN input.
This fixes the math/test-nearbyint-except test on SPARC.
Changelog:
* sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Trigger an
invalid exception for a sNaN input.
* sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise.
* sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S
(__nearbyint_vis3): Likewise
* sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S
(__nearbyintf_vis3): Likewise
* sparc/sparc64/fpu/s_nearbyint.S (__nearbyint): Likewise.
* sparc/sparc64/fpu/s_nearbyintf.S (__nearbyintf): Likewise.
* sparc/sparc64/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3):
Likewise.
* sparc/sparc64/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3):
Likewise.
If assembler doesn't support AVX512DQ, _dl_runtime_resolve_avx is used
to save the first 8 vector registers, which only saves the lower 256
bits of vector register, for lazy binding. When it is called on AVX512
platform, the upper 256 bits of ZMM registers are clobbered. Parameters
passed in ZMM registers will be wrong when the function is called the
first time. This patch requires binutils 2.24, whose assembler can store
and load ZMM registers, to build x86-64 glibc. Since mathvec library
needs assembler support for AVX512DQ, we disable mathvec if assembler
doesn't support AVX512DQ.
[BZ #20139]
* config.h.in (HAVE_AVX512_ASM_SUPPORT): Renamed to ...
(HAVE_AVX512DQ_ASM_SUPPORT): This.
* sysdeps/x86_64/configure.ac: Require assembler from binutils
2.24 or above.
(HAVE_AVX512_ASM_SUPPORT): Removed.
(HAVE_AVX512DQ_ASM_SUPPORT): New.
* sysdeps/x86_64/configure: Regenerated.
* sysdeps/x86_64/dl-trampoline.S: Make HAVE_AVX512_ASM_SUPPORT
check unconditional.
* sysdeps/x86_64/multiarch/ifunc-impl-list.c: Likewise.
* sysdeps/x86_64/multiarch/memcpy.S: Likewise.
* sysdeps/x86_64/multiarch/memcpy_chk.S: Likewise.
* sysdeps/x86_64/multiarch/memmove-avx512-no-vzeroupper.S:
Likewise.
* sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S:
Likewise.
* sysdeps/x86_64/multiarch/memmove.S: Likewise.
* sysdeps/x86_64/multiarch/memmove_chk.S: Likewise.
* sysdeps/x86_64/multiarch/mempcpy.S: Likewise.
* sysdeps/x86_64/multiarch/mempcpy_chk.S: Likewise.
* sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S:
Likewise.
* sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S:
Likewise.
* sysdeps/x86_64/multiarch/memset.S: Likewise.
* sysdeps/x86_64/multiarch/memset_chk.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S: Check
HAVE_AVX512DQ_ASM_SUPPORT instead of HAVE_AVX512_ASM_SUPPORT.
* sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx51:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S:
Likewise.
current vector function declaration "#pragma omp declare simd notinbranch",
according to which vector sincos should have vector of pointers for second and
third parameters. It is fixed with implementation as wrapper to version
having second and third parameters as pointers.
[BZ #20024]
* sysdeps/x86/fpu/test-math-vector-sincos.h: New.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos2_core_sse4.S: Fixed ABI
of this implementation of vector function.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos4_core_avx2.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S:
Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf4_core_sse4.S: Likewise.
* sysdeps/x86_64/fpu/multiarch/svml_s_sincosf8_core_avx2.S: Likewise.
* sysdeps/x86_64/fpu/svml_d_sincos2_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_d_sincos4_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S: Likewise.
* sysdeps/x86_64/fpu/svml_d_sincos8_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_s_sincosf16_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_s_sincosf4_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_s_sincosf8_core.S: Likewise.
* sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen2-wrappers.c: Use another wrapper
for testing vector sincos with fixed ABI.
* sysdeps/x86_64/fpu/test-double-vlen4-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx.c: New test.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512.c: Likewise.
* sysdeps/x86_64/fpu/test-double-libmvec-sincos.c: Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx.c: Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2.c: Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512.c: Likewise.
* sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c: Likewise.
* sysdeps/x86_64/fpu/Makefile: Added new tests.
Commits d81f90cc and 89faa0340 replaced called to __isnan and __isinf
by the corresponding GCC builtins. In turns GCC emits calls to _Qp_cmp.
We should therefore add _Qp_cmp to localplt.data as otherwise the
elf/check-localplt test fails with:
Extra PLT reference: libc.so: _Qp_cmp
A similar change has already been done for SPARC32 in commit 6ef1cb95.
Changelog:
* sysdeps/unix/sysv/linux/sparc/sparc64/localplt.data: Add _Qp_cmp.
This implementation is based on the one already used at
sysdeps/x86_64/fpu/e_expf.S.
This implementation improves the performance by ~14% on average in synthetic
benchmarks at the cost of decreasing accuracy to 1 ULP.
The patched change fixes a regression for executables compiled with the
-p option and linked with gcrt1.o. The executables crash on startup.
This regression was introduced in 2.22 and was noticed in the gcc testsuite.
Although the Enhanced REP MOVSB/STOSB (ERMS) implementations of memmove,
memcpy, mempcpy and memset aren't used by the current processors, this
patch adds Prefer_ERMS check in memmove, memcpy, mempcpy and memset so
that they can be used in the future.
* sysdeps/x86/cpu-features.h (bit_arch_Prefer_ERMS): New.
(index_arch_Prefer_ERMS): Likewise.
* sysdeps/x86_64/multiarch/memcpy.S (__new_memcpy): Return
__memcpy_erms for Prefer_ERMS.
* sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
(__memmove_erms): Enabled for libc.a.
* ysdeps/x86_64/multiarch/memmove.S (__libc_memmove): Return
__memmove_erms or Prefer_ERMS.
* sysdeps/x86_64/multiarch/mempcpy.S (__mempcpy): Return
__mempcpy_erms for Prefer_ERMS.
* sysdeps/x86_64/multiarch/memset.S (memset): Return
__memset_erms for Prefer_ERMS.
For some reasons I have not investigated yet, tst-mode-switch-1 hangs on
a MIPS UTM-8 machine running an o32 userland and a 3.6.1 kernel.
This patch changes the test so that it runs under the test-skeleton
framework, causing the test to fail after a timeout instead of hanging
the whole testsuite. At the same time, also change the tst-mode-switch-2
and tst-mode-switch-3 tests.
Changelog:
* sysdeps/mips/tst-mode-switch-1.c (main): Converted to ...
(do_test): ... this.
(TEST_FUNCTION): New macro.
Include test-skeleton.c.
* sysdeps/mips/tst-mode-switch-2.c (main): Likewise.
* sysdeps/mips/tst-mode-switch-3.c (main): Likewise.
As discussed in
<https://sourceware.org/ml/libc-alpha/2016-05/msg00577.html>, TS
18661-1 disallows ceil, floor, round and trunc functions from raising
the "inexact" exception, in accordance with general IEEE 754 semantics
for when that exception is raised. Fixing this for x87 floating point
is more complicated than for the other versions of these functions,
because they use the frndint instruction that raises "inexact" and
this can only be avoided by saving and restoring the whole
floating-point environment.
As I noted in
<https://sourceware.org/ml/libc-alpha/2016-06/msg00128.html>, I have
now implemented a GCC option -fno-fp-int-builtin-inexact for GCC 7,
such that GCC will inline these functions on x86, without caring about
"inexact", when the default -ffp-int-builtin-inexact is in effect.
This allows users to get optimized code depending on the options they
pass to the compiler, while making the out-of-line functions follow TS
18661-1 semantics and avoid "inexact".
This patch duly fixes the out-of-line trunc function implementations
to avoid "inexact", in the same way as the nearbyint implementations.
I do not know how the performance of implementations such as these
based on saving the environment and changing the rounding mode
temporarily compares to that of the C versions or SSE 4.1 versions (of
course, for 32-bit x86 SSE implementations still need to get the
return value in an x87 register); it's entirely possible other
implementations could be faster in some cases.
Tested for x86_64 and x86.
[BZ #15479]
* sysdeps/i386/fpu/s_trunc.S (__trunc): Save and restore
floating-point environment rather than just control word.
* sysdeps/i386/fpu/s_truncf.S (__truncf): Likewise.
* sysdeps/i386/fpu/s_truncl.S (__truncl): Save and restore
floating-point environment, with "invalid" exceptions merged in,
rather than just control word.
* sysdeps/x86_64/fpu/s_truncl.S (__truncl): Likewise.
* math/libm-test.inc (trunc_test_data): Do not allow spurious
"inexact" exceptions.
As discussed in
<https://sourceware.org/ml/libc-alpha/2016-05/msg00577.html>, TS
18661-1 disallows ceil, floor, round and trunc functions from raising
the "inexact" exception, in accordance with general IEEE 754 semantics
for when that exception is raised. Fixing this for x87 floating point
is more complicated than for the other versions of these functions,
because they use the frndint instruction that raises "inexact" and
this can only be avoided by saving and restoring the whole
floating-point environment.
As I noted in
<https://sourceware.org/ml/libc-alpha/2016-06/msg00128.html>, I have
now implemented a GCC option -fno-fp-int-builtin-inexact for GCC 7,
such that GCC will inline these functions on x86, without caring about
"inexact", when the default -ffp-int-builtin-inexact is in effect.
This allows users to get optimized code depending on the options they
pass to the compiler, while making the out-of-line functions follow TS
18661-1 semantics and avoid "inexact".
This patch duly fixes the out-of-line floor function implementations
to avoid "inexact", in the same way as the nearbyint implementations.
I do not know how the performance of implementations such as these
based on saving the environment and changing the rounding mode
temporarily compares to that of the C versions or SSE 4.1 versions (of
course, for 32-bit x86 SSE implementations still need to get the
return value in an x87 register); it's entirely possible other
implementations could be faster in some cases.
Tested for x86_64 and x86.
[BZ #15479]
* sysdeps/i386/fpu/s_floor.S (__floor): Save and restore
floating-point environment rather than just control word.
* sysdeps/i386/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/i386/fpu/s_floorl.S (__floorl): Save and restore
floating-point environment, with "invalid" exceptions merged in,
rather than just control word.
* sysdeps/x86_64/fpu/s_floorl.S (__floorl): Likewise.
* math/libm-test.inc (floor_test_data): Do not allow spurious
"inexact" exceptions.
As discussed in
<https://sourceware.org/ml/libc-alpha/2016-05/msg00577.html>, TS
18661-1 disallows ceil, floor, round and trunc functions from raising
the "inexact" exception, in accordance with general IEEE 754 semantics
for when that exception is raised. Fixing this for x87 floating point
is more complicated than for the other versions of these functions,
because they use the frndint instruction that raises "inexact" and
this can only be avoided by saving and restoring the whole
floating-point environment.
As I noted in
<https://sourceware.org/ml/libc-alpha/2016-06/msg00128.html>, I have
now implemented a GCC option -fno-fp-int-builtin-inexact for GCC 7,
such that GCC will inline these functions on x86, without caring about
"inexact", when the default -ffp-int-builtin-inexact is in effect.
This allows users to get optimized code depending on the options they
pass to the compiler, while making the out-of-line functions follow TS
18661-1 semantics and avoid "inexact".
This patch duly fixes the out-of-line ceil function implementations to
avoid "inexact", in the same way as the nearbyint implementations.
I do not know how the performance of implementations such as these
based on saving the environment and changing the rounding mode
temporarily compares to that of the C versions or SSE 4.1 versions (of
course, for 32-bit x86 SSE implementations still need to get the
return value in an x87 register); it's entirely possible other
implementations could be faster in some cases.
Tested for x86_64 and x86.
[BZ #15479]
* sysdeps/i386/fpu/s_ceil.S (__ceil): Save and restore
floating-point environment rather than just control word.
* sysdeps/i386/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/i386/fpu/s_ceill.S (__ceill): Save and restore
floating-point environment, with "invalid" exceptions merged in,
rather than just control word.
* sysdeps/x86_64/fpu/s_ceill.S (__ceill): Likewise.
* math/libm-test.inc (ceil_test_data): Do not allow spurious
"inexact" exceptions.
Commit 43c29487 tried to fix the vfork aliases in libpthread.so on MIPS
and SPARC, but failed to do it correctly, introducing an ABI change.
This patch does the remaining changes needed to align the MIPS and SPARC
vfork implementations with the other architectures. That way the the
alpha version of pt-vfork.S works correctly for MIPS and SPARC. The
changes for alpha were done in 82aab97c.
Changelog:
* sysdeps/unix/sysv/linux/mips/vfork.S (__vfork): Rename into
__libc_vfork.
(__vfork) [IS_IN (libc)]: Remove alias.
(__libc_vfork) [IS_IN (libc)]: Define as an alias.
* sysdeps/unix/sysv/linux/sparc/sparc32/vfork.S: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/vfork.S: Likewise.
atomic_compare_and_exchange_bool_rel and
catomic_compare_and_exchange_bool_rel are removed and replaced with the
new C11-like atomic_compare_exchange_weak_release. The concurrent code
in nscd/cache.c has not been reviewed yet, so this patch does not add
detailed comments.
* nscd/cache.c (cache_add): Use new C11-like atomic operation instead
of atomic_compare_and_exchange_bool_rel.
* nptl/pthread_mutex_unlock.c (__pthread_mutex_unlock_full): Likewise.
* include/atomic.h (atomic_compare_and_exchange_bool_rel,
catomic_compare_and_exchange_bool_rel): Remove.
* sysdeps/aarch64/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/alpha/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/arm/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/mips/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
* sysdeps/tile/atomic-machine.h
(atomic_compare_and_exchange_bool_rel): Likewise.
The x86_64 and i386 versions of scalbl return sNaN for some cases of
sNaN input and are missing "invalid" exceptions for other cases. This
results from overly complicated code that either returns a NaN input,
or discards both inputs when one is NaN and loads a NaN from memory.
This patch fixes this by simplifying the code to add the arguments
when either one is NaN.
Tested for x86_64 and x86.
[BZ #20296]
* sysdeps/i386/fpu/e_scalbl.S (__ieee754_scalbl): Add arguments
when either argument is a NaN.
* sysdeps/x86_64/fpu/e_scalbl.S (__ieee754_scalbl): Likewise.
* math/libm-test.inc (scalb_test_data): Add sNaN tests.
The i386 implementations of nearbyint functions, and x86_64
nearbyintl, contain code to mask the "inexact" exception. However,
the fnstenv instruction has the effect of masking all exceptions, so
this masking code has been redundant since fnstenv was added to those
implementations (by commit 846d9a4a3acdb4939ca7bf6aed48f9f6f26911be;
commit 71d1b0166b added the test
math/test-nearbyint-except-2.c that verifies these functions do work
when called with "inexact" traps enabled); this patch removes the
redundant code.
Tested for x86_64 and x86.
* sysdeps/i386/fpu/s_nearbyint.S (__nearbyint): Do not mask
"inexact" exceptions after fnstenv.
* sysdeps/i386/fpu/s_nearbyintf.S (__nearbyintf): Likewise.
* sysdeps/i386/fpu/s_nearbyintl.S (__nearbyintl): Likewise.
* sysdeps/x86_64/fpu/s_nearbyintl.S (__nearbyintl): Likewise.
This file was added to sysdeps/generic/bits in 2012. This appears to
have been an oversight, as the entire sysdeps/generic/bits directory was
moved to the top level in 2005. Accordingly the generic bits/hwcap.h
belongs there too.
* sysdeps/generic/bits/hwcap.h: Moved to ...
* bits/hwcap.h: Here.
This patch fixes the p{readv,writev}{64} consolidation implementation
from commits 4e77815 and af5fdf5. Different from pread/pwrite
implementation, preadv/pwritev implementation does not require
__ALIGNMENT_ARG because kernel syscall prototypes define
the high and low part of the off_t, if it is the case, directly
(different from pread/pwrite where the architecture ABI for passing
64-bit values must be in consideration for passsing the arguments).
It also adds some basic tests for preadv/pwritev.
Tested on x86_64, i686, and armhf.
* misc/Makefile (tests): Add tst-preadvwritev and tst-preadvwritev64.
* misc/tst-preadvwritev.c: New file.
* misc/tst-preadvwritev64.c: Likewise.
* sysdeps/unix/sysv/linux/preadv.c (preadv): Remove SYSCALL_LL{64}
usage.
* sysdeps/unix/sysv/linux/preadv64.c (preadv64): Likewise.
* sysdeps/unix/sysv/linux/pwritev.c (pwritev): Likewise.
* sysdeps/unix/sysv/linux/pwritev64.c (pwritev64): Likewise.
* sysdeps/unix/sysv/linux/sysdep.h (LO_HI_LONG): New macro.
is the fastest way to search for '\0'. Otherwise use memchr with an infinite
size. This is 3x faster on benchtests for large sizes. Passes GLIBC tests.
* sysdeps/aarch64/rawmemchr.S (__rawmemchr): New file.
* sysdeps/aarch64/strlen.S (__strlen): Change to __strlen to avoid PLT.
cases: small copies of up to 16 bytes, medium copies of 17..96 bytes which are
fully unrolled. Large copies of more than 96 bytes align the destination and
use an unrolled loop processing 64 bytes per iteration. In order to share code
with memmove, small and medium copies read all data before writing, allowing
any kind of overlap. All memmoves except for the large backwards case fall
into memcpy for optimal performance. On a random copy test memcpy/memmove are
40% faster on Cortex-A57 and 28% on Cortex-A53.
* sysdeps/aarch64/memcpy.S (memcpy):
Rewrite of optimized memcpy and memmove.
* sysdeps/aarch64/memmove.S (memmove): Remove
memmove code (merged into memcpy.S).
With recent binutils versions the GNU libc fails to build on at least
MISP and SPARC, with this kind of error:
/home/aurel32/glibc/glibc-build/nptl/libpthread.so:(*IND*+0x0): multiple definition of `vfork@GLIBC_2.0'
/home/aurel32/glibc/glibc-build/nptl/libpthread.so::(.text+0xee50): first defined here
It appears that on these architectures pt-vfork.S includes vfork.S
(through the alpha version of pt-vfork.S) and that the __vfork aliases
are not conditionalized on IS_IN (libc) like on other architectures.
Therefore the aliases are also wrongly included in libpthread.so.
Fix this by properly conditionalizing the aliases like on other
architectures.
Changelog:
* sysdeps/unix/sysv/linux/mips/vfork.S (__vfork): Conditionalize
hidden_def, weak_alias and strong_alias on [IS_IN (libc)].
* sysdeps/unix/sysv/linux/sparc/sparc32/vfork.S: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/vfork.S: Likewise.
TS 18661 adds nextup and nextdown functions alongside nextafter to provide
support for float128 equivalent to it. This patch adds nextupl, nextup,
nextupf, nextdownl, nextdown and nextdownf to libm before float128 support.
The nextup functions return the next representable value in the direction of
positive infinity and the nextdown functions return the next representable
value in the direction of negative infinity. These are currently enabled
as GNU extensions.
fdim suffers from double rounding on i386 because subtracting two
double values can produce an inexact long double value exactly half
way between two double values. This patch fixes this by creating an
i386-specific version of fdim - C, based on the generic version,
unlike the previous .S version - which sets the x87 precision control
to double precision for the subtraction and then restores it
afterwards. As noted in the comment added, there are no issues of
double rounding for subnormals (a case that setting precision control
does not address) because subtraction cannot produce an inexact result
in the subnormal range.
Tested for x86_64 and x86.
[BZ #20255]
* sysdeps/i386/fpu/s_fdim.c: New file. Based on math/s_fdim.c.
* math/libm-test.inc (fdim_test_data): Add another test.
Some architectures have their own versions of fdim functions, which
are missing errno setting (bug 6796) and may also return sNaN instead
of qNaN for sNaN input, in the case of the x86 / x86_64 long double
versions (bug 20256).
These versions are not actually doing anything that a compiler
couldn't generate, just straightforward comparisons / arithmetic (and,
in the x86 / x86_64 case, testing for NaNs with fxam, which isn't
actually needed once you use an unordered comparison and let the NaNs
pass through the same subtraction as non-NaN inputs). This patch
removes the x86 / x86_64 / powerpc versions, so that those
architectures use the generic C versions, which correctly handle
setting errno and deal properly with sNaN inputs. This seems better
than dealing with setting errno in lots of .S versions.
The i386 versions also return results with excess range and precision,
which is not appropriate for a function exactly defined by reference
to IEEE operations. For errno setting to work correctly on overflow,
it's necessary to remove excess range with math_narrow_eval, which
this patch duly does in the float and double versions so that the
tests can reliably pass on x86. For float, this avoids any double
rounding issues as the long double precision is more than twice that
of float. For double, double rounding issues will need to be
addressed separately, so this patch does not fully fix bug 20255.
Tested for x86_64, x86 and powerpc.
[BZ #6796]
[BZ #20255]
[BZ #20256]
* math/s_fdim.c: Include <math_private.h>.
(__fdim): Use math_narrow_eval on result.
* math/s_fdimf.c: Include <math_private.h>.
(__fdimf): Use math_narrow_eval on result.
* sysdeps/i386/fpu/s_fdim.S: Remove file.
* sysdeps/i386/fpu/s_fdimf.S: Likewise.
* sysdeps/i386/fpu/s_fdiml.S: Likewise.
* sysdeps/i386/i686/fpu/s_fdim.S: Likewise.
* sysdeps/i386/i686/fpu/s_fdimf.S: Likewise.
* sysdeps/i386/i686/fpu/s_fdiml.S: Likewise.
* sysdeps/powerpc/fpu/s_fdim.c: Likewise.
* sysdeps/powerpc/fpu/s_fdimf.c: Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_fdim.c: Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_fdim.c: Likewise.
* sysdeps/x86_64/fpu/s_fdiml.S: Likewise.
* math/libm-test.inc (fdim_test_data): Expect errno setting on
overflow. Add sNaN tests.
This implementation utilizes vectors to improve performance
compared to current byte by byte implementation for POWER7.
The performance improvement is upto 4x. This patch is tested
on powerpc64 and powerpc64le.
The dbl-64 implementation of atan2, passed arguments (sNaN, qNaN),
fails to raise the "invalid" exception. This patch fixes it to add
both arguments, rather than just adding the second argument to itself,
in the case where the second argument is a NaN (which is checked for
before checking for the first argument being a NaN). sNaN tests for
atan2 are added, along with some qNaN tests I noticed were missing but
should have been there by analogy with other tests present.
Tested for x86_64 and x86.
[BZ #20252]
* sysdeps/ieee754/dbl-64/e_atan2.c (__ieee754_atan2): Add both
arguments when second argument is a NaN.
* math/libm-test.inc (atan2_test_data): Add sNaN tests and more
qNaN tests.
Various implementations of frexp functions return sNaN for sNaN
input. This patch fixes them to add such arguments to themselves so
that qNaN is returned.
Tested for x86_64, x86, mips64 and powerpc.
[BZ #20250]
* sysdeps/i386/fpu/s_frexpl.S (__frexpl): Add non-finite input to
itself.
* sysdeps/ieee754/dbl-64/s_frexp.c (__frexp): Add non-finite or
zero input to itself.
* sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c (__frexp):
Likewise.
* sysdeps/ieee754/flt-32/s_frexpf.c (__frexpf): Likewise.
* sysdeps/ieee754/ldbl-128/s_frexpl.c (__frexpl): Likewise.
* sysdeps/ieee754/ldbl-128ibm/s_frexpl.c (__frexpl): Likewise.
* sysdeps/ieee754/ldbl-96/s_frexpl.c (__frexpl): Likewise.
* math/libm-test.inc (frexp_test_data): Add sNaN tests.
This patch removes __ASSUME_FUTEX_LOCK_PI usage and assumes that
kernel will correctly return if it supports or not
futex_atomic_cmpxchg_inatomic.
Current PI mutex code already has runtime support by calling
prio_inherit_missing and returns ENOTSUP if the futex operation fails
at initialization (it issues a FUTEX_UNLOCK_PI futex operation).
Also, current minimum supported kernel (v3.2) will return ENOSYS if
futex_atomic_cmpxchg_inatomic is not supported in the system:
kernel/futex.c:
2628 long do_futex(u32 __user *uaddr, int op, u32 val, ktime_t *timeout,
2629 u32 __user *uaddr2, u32 val2, u32 val3)
2630 {
2631 int ret = -ENOSYS, cmd = op & FUTEX_CMD_MASK;
[...]
2667 case FUTEX_UNLOCK_PI:
2668 if (futex_cmpxchg_enabled)
2669 ret = futex_unlock_pi(uaddr, flags);
[...]
2686 return ret;
2687 }
The futex_cmpxchg_enabled is initialized by calling cmpxchg_futex_value_locked,
which calls futex_atomic_cmpxchg_inatomic.
For ARM futex_atomic_cmpxchg_inatomic will be either defined (if both
CONFIG_CPU_USE_DOMAINS and CONFIG_SMP are not defined) or use the
default generic implementation that returns ENOSYS.
For m68k is uses the default generic implementation.
For mips futex_atomic_cmpxchg_inatomic will return ENOSYS if cpu has no
'cpu_has_llsc' support (defined by each chip supporte inside kernel).
For sparc, 32-bit kernel will just use default generic implementation,
while 64-bit kernel has support.
Tested on ARM (v3.8 kernel) and x86_64.
* nptl/pthread_mutex_init.c [__ASSUME_FUTEX_LOCK_PI]
(prio_inherit_missing): Remove define.
* sysdeps/unix/sysv/linux/arm/kernel-features.h
(__ASSUME_FUTEX_LOCK_PI): Likewise.
* sysdeps/unix/sysv/linux/kernel-features.h (__ASSUME_FUTEX_LOCK_PI):
Likewise.
* sysdeps/unix/sysv/linux/m68k/kernel-features.h
(__ASSUME_FUTEX_LOCK_PI): Likewise.
* sysdeps/unix/sysv/linux/mips/kernel-features.h
(__ASSUME_FUTEX_LOCK_PI): Likewise.
* sysdeps/unix/sysv/linux/sparc/kernel-features.h
(__ASSUME_FUTEX_LOCK_PI): Likewise.
After some discussion in libc-alpha about this POSIX compliance fix, I see
that GLIBC should indeed revert back to previous definition of msghdr and
cmsghdr and implementation of sendmsg, recvmsg, sendmmsg, recvmmsg due some
reasons:
* The possible issue where the syscalls wrapper add the compatibility
layer is quite limited in scope and range. And kernel current
also add some limits to the values on the internal msghdr and
cmsghdr fields:
- msghdr::msg_iovlen larger than UIO_MAXIOV (1024) returns
EMSGSIZE.
- msghdr::msg_controllen larger than INT_MAX returns ENOBUFS.
* There is a small performance hit for recvmsg/sendmsg/recmmsg which
is neglectable, but it is a big hit for sendmmsg since now instead
of calling the syscall for the packed structure, GLIBC is calling
multiple sendmsg. This defeat the very existence of the syscall.
* It currently breaks libsanitizer build on GCC [1] (I fixed on compiler-rt).
However the fix is incomplete because it does add any runtime check
since libsanitizer currently does not have any facility to intercept
symbols with multiple version [2].
This, along with incorret dlsym/dlvsym return for versioned symbol due
another bug [3], makes hard to interpose versioned symbols.
Also, current approach of fixing GCC PR#71445 leads to half-baked
solutions without versioned symbol interposing.
This patch basically reverts commits 2f0dc39029, 222c2d7f43,
af7f7c7ec8. I decided to not revert abf29edd4a (Adjust
kernel-features.h defaults for recvmsg and sendmsg) mainly because it
does not really address the POSIX compliance original issue and also
adds some cleanups.
Tested on x86, i386, s390, s390x, aarch64, and powerpc64le.
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71445
[2] https://github.com/google/sanitizers/issues/628
[3] https://sourceware.org/bugzilla/show_bug.cgi?id=14932
* conform/data/sys/socket.h-data (msghdr.msg_iovlen): Add xfail-.
(msghdr.msg_controllen): Likewise.
(cmsghdr.cmsg_len): Likewise.
* nptl/Makefile (libpthread-routines): Remove ptw-oldrecvmsg and
ptw-oldsendmsg.
(CFLAGS-oldrecvmsg.c): Remove rule.
(CFLAGS-oldsendmsg.c): Likewise.
(CFLAGS-recvmsg.c): Add rule.
(CFLAGS-sendmsg.c): Likewise.
* sysdeps/unix/sysv/linux/Makefile (sysdep_routines): Remove
oldrecvmsg, oldsendmsg, oldrecvmmsg, oldsendmmsg.
(CFLAGS-recvmsg.c): Remove rule.
(CFLAGS-sendmsg.c): Likewise.
(CFLAGS-oldrecvmsg.c): Likewise.
(CFLAGS-oldsendmsg.c): Likewise.
(CFLAGS-recvmmsg.c): Likewise.
* sysdeps/unix/sysv/linux/bits/socket.h (msghdr.msg_iovlen): Revert
to kernel defined interfaces.
(msghdr.msg_controllen): Likewise.
(cmsghdr.cmsg_len): Likewise.
(msghdr.__glibc_reserved1): Remove member.
(msghdr.__glibc_reserved2): Likewise.
(cmsghdr.__glibc_reserved1): Likewise.
* sysdeps/unix/sysv/linux/oldrecvmmsg.c: Remove file.
* sysdeps/unix/sysv/linux/oldrecvmsg.c: Likewise.
* sysdeps/unix/sysv/linux/oldsendmmsg.c: Likewise.
* sysdeps/unix/sysv/linux/oldsendmsg.c: Likewise.
* sysdeps/unix/sysv/linux/recvmmsg.c: Revert back to previous
version.
* sysdeps/unix/sysv/linux/recvmsg.c: Likewise.
* sysdeps/unix/sysv/linux/sendmmsg.c: Likewise.
* sysdeps/unix/sysv/linux/sendmsg.c: Likewise.
* sysdeps/unix/sysv/linux/aarch64/Versions [libc] (GLIBC_2.24):
Remove recvmsg and sendmsg.
* sysdeps/unix/sysv/linux/alpha/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/hppa/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/i386/Versions [libc] (GLIBC_2.24): Likewise.
* sysdeps/unix/sysv/linux/m68k/Versions [libc] (GLIBC_2.24): Likewise.
* sysdeps/unix/sysv/linux/microblaze/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/mips/mips32/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n32/Versions
[libc] (GLIBC_2.24): Likewise.
* sysdeps/unix/sysv/linux/nios2/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/powerpc/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions
[libc] (GLIBC_2.24): Likewise.
* sysdeps/unix/sysv/linux/s390/s390-32/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/s390/s390-64/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/sh/Versions [libc] (GLIBC_2.24): Likewise.
* sysdeps/unix/sysv/linux/sparc/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/tile/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/x86_64/Versions [libc] (GLIBC_2.24):
Likewise.
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx64/Versions: Remove file
* sysdeps/unix/sysv/linux/x86_64/64/Versions: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/Versions: Likewise.
* sysdeps/unix/sysv/linux/aarch64/libc.abilist: Remove new 2.24
version for {recv,send,recm,sendm}msg.
* sysdeps/unix/sysv/linux/alpha/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/arm/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/hppa/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/i386/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/ia64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/m68k/coldfire/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/m68k/m680x0/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/microblaze/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/mips/mips32/fpu/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/mips/mips32/nofpu/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n32/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/fpu/libc.abilist:
Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/nofpu/libc.abilist:
Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/libc-le.abilist: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/s390/s390-32/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/nios2/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/sh/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc32/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx32/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/tile/tilepro/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/x86_64/64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist: Likewise.
The i386/x86_64 versions of log2l return sNaN for sNaN input. This
patch fixes them to add NaN inputs to themselves so that qNaN is
returned in this case.
Tested for x86_64 and x86.
[BZ #20235]
* sysdeps/i386/fpu/e_log2l.S (__ieee754_log2l): Add NaN input to
itself.
* sysdeps/x86_64/fpu/e_log2l.S (__ieee754_log2l): Likewise.
* math/libm-test.inc (log2_test_data): Add sNaN tests.
The ldbl-128ibm version of log1pl returns sNaN for sNaN input. This
patch fixes it to add such inputs to themselves so that qNaN is
returned in this case.
Tested for powerpc.
[BZ #20234]
* sysdeps/ieee754/ldbl-128ibm/s_log1pl.c (__log1pl): Add positive
infinity or NaN input to itself.
The ldbl-128ibm version of expm1l returns sNaN for sNaN input. This
patch fixes it to add such inputs to themselves so that qNaN is
returned in this case.
Tested for powerpc.
[BZ #20233]
* sysdeps/ieee754/ldbl-128ibm/s_expm1l.c (__expm1l): Add NaN input
to itself.
The ldbl-128 version of expm1l returns sNaN for sNaN input. This
patch fixes it to add such inputs to themselves so that qNaN is
returned in this case.
Tested for mips64.
[BZ #20232]
* sysdeps/ieee754/ldbl-128/s_expm1l.c (__expm1l): Add NaN input to
itself.
Since x86-64 no longer uses memory copy functions, add dummy memcopy.h
and wordcopy.c to reduce code size. It reduces the size of libc.so by
about 1 KB.
* sysdeps/x86_64/memcopy.h: New file.
* sysdeps/x86_64/wordcopy.c: Likewise.
The i386/x86_64 versions of log1pl return sNaN for sNaN input. This
patch fixes them to add a NaN input to itself so that qNaN is returned
in this case.
Tested for x86_64 and x86.
[BZ #20229]
* sysdeps/i386/fpu/s_log1pl.S (__log1pl): Add NaN input to itself.
* sysdeps/x86_64/fpu/s_log1pl.S (__log1pl): Likewise.
* math/libm-test.inc (log1p_test_data): Add sNaN tests.
The i386/x86_64 versions of log10l return sNaN for sNaN input. This
patch fixes them to add a NaN input to itself so that qNaN is returned
in this case.
Tested for x86_64 and x86.
[BZ #20228]
* sysdeps/i386/fpu/e_log10l.S (__ieee754_log10l): Add NaN input to
itself.
* sysdeps/x86_64/fpu/e_log10l.S (__ieee754_log10l): Likewise.
* math/libm-test.inc (log10_test_data): Add sNaN tests.
The i386/x86_64 versions of logl return sNaN for sNaN input. This
patch fixes them to add a NaN input to itself so that qNaN is returned
in this case.
Tested for x86_64 and x86 (including a build for i586 to cover the
non-i686 logl version).
[BZ #20227]
* sysdeps/i386/fpu/e_logl.S (__ieee754_logl): Add NaN input to
itself.
* sysdeps/i386/i686/fpu/e_logl.S (__ieee754_logl): Likewise.
* sysdeps/x86_64/fpu/e_logl.S (__ieee754_logl): Likewise.
* math/libm-test.inc (log_test_data): Add sNaN tests.
The i386 and x86_64 implementations of expl, exp10l and expm1l (code
shared between the functions) return sNaN for sNaN input. This patch
fixes them to add NaN inputs to themselves so that qNaN is returned in
this case.
Tested for x86_64 and x86.
[BZ #20226]
* sysdeps/i386/fpu/e_expl.S (IEEE754_EXPL): Add NaN argument to
itself.
* sysdeps/x86_64/fpu/e_expl.S (IEEE754_EXPL): Likewise.
* math/libm-test.inc (exp_test_data): Add sNaN tests.
(exp10_test_data): Likewise.
(expm1_test_data): Likewise.
The i386 version of cbrtl returns sNaN (without raising any
exceptions) for sNaN input. This patch fixes it to add non-finite
arguments to themselves (the code path in question is also reached for
zero arguments, for which adding them to themselves is also harmless),
so that "invalid" is raised and qNaN returned.
Tested for x86_64 and x86.
[BZ #20224]
* sysdeps/i386/fpu/s_cbrtl.S (__cbrtl): Add non-finite or zero
argument to itself.
* math/libm-test.inc (cbrt_test_data): Add sNaN tests.
Since the new SSE2/AVX2 memcpy/memmove are faster than the previous ones,
we can remove the previous SSE2/AVX2 memcpy/memmove and replace them with
the new ones.
No change in IFUNC selection if SSE2 and AVX2 memcpy/memmove weren't used
before. If SSE2 or AVX2 memcpy/memmove were used, the new SSE2 or AVX2
memcpy/memmove optimized with Enhanced REP MOVSB will be used for
processors with ERMS. The new AVX512 memcpy/memmove will be used for
processors with AVX512 which prefer vzeroupper.
Since the new SSE2 memcpy/memmove are faster than the previous default
memcpy/memmove used in libc.a and ld.so, we also remove the previous
default memcpy/memmove and make them the default memcpy/memmove, except
that non-temporal store isn't used in ld.so.
Together, it reduces the size of libc.so by about 6 KB and the size of
ld.so by about 2 KB.
[BZ #19776]
* sysdeps/x86_64/memcpy.S: Make it dummy.
* sysdeps/x86_64/mempcpy.S: Likewise.
* sysdeps/x86_64/memmove.S: New file.
* sysdeps/x86_64/memmove_chk.S: Likewise.
* sysdeps/x86_64/multiarch/memmove.S: Likewise.
* sysdeps/x86_64/multiarch/memmove_chk.S: Likewise.
* sysdeps/x86_64/memmove.c: Removed.
* sysdeps/x86_64/multiarch/memcpy-avx-unaligned.S: Likewise.
* sysdeps/x86_64/multiarch/memcpy-sse2-unaligned.S: Likewise.
* sysdeps/x86_64/multiarch/memmove-avx-unaligned.S: Likewise.
* sysdeps/x86_64/multiarch/memmove-sse2-unaligned-erms.S:
Likewise.
* sysdeps/x86_64/multiarch/memmove.c: Likewise.
* sysdeps/x86_64/multiarch/memmove_chk.c: Likewise.
* sysdeps/x86_64/multiarch/Makefile (sysdep_routines): Remove
memcpy-sse2-unaligned, memmove-avx-unaligned,
memcpy-avx-unaligned and memmove-sse2-unaligned-erms.
* sysdeps/x86_64/multiarch/ifunc-impl-list.c
(__libc_ifunc_impl_list): Replace
__memmove_chk_avx512_unaligned_2 with
__memmove_chk_avx512_unaligned. Remove
__memmove_chk_avx_unaligned_2. Replace
__memmove_chk_sse2_unaligned_2 with
__memmove_chk_sse2_unaligned. Remove __memmove_chk_sse2 and
__memmove_avx_unaligned_2. Replace __memmove_avx512_unaligned_2
with __memmove_avx512_unaligned. Replace
__memmove_sse2_unaligned_2 with __memmove_sse2_unaligned.
Remove __memmove_sse2. Replace __memcpy_chk_avx512_unaligned_2
with __memcpy_chk_avx512_unaligned. Remove
__memcpy_chk_avx_unaligned_2. Replace
__memcpy_chk_sse2_unaligned_2 with __memcpy_chk_sse2_unaligned.
Remove __memcpy_chk_sse2. Remove __memcpy_avx_unaligned_2.
Replace __memcpy_avx512_unaligned_2 with
__memcpy_avx512_unaligned. Remove __memcpy_sse2_unaligned_2
and __memcpy_sse2. Replace __mempcpy_chk_avx512_unaligned_2
with __mempcpy_chk_avx512_unaligned. Remove
__mempcpy_chk_avx_unaligned_2. Replace
__mempcpy_chk_sse2_unaligned_2 with
__mempcpy_chk_sse2_unaligned. Remove __mempcpy_chk_sse2.
Replace __mempcpy_avx512_unaligned_2 with
__mempcpy_avx512_unaligned. Remove __mempcpy_avx_unaligned_2.
Replace __mempcpy_sse2_unaligned_2 with
__mempcpy_sse2_unaligned. Remove __mempcpy_sse2.
* sysdeps/x86_64/multiarch/memcpy.S (__new_memcpy): Support
__memcpy_avx512_unaligned_erms and __memcpy_avx512_unaligned.
Use __memcpy_avx_unaligned_erms and __memcpy_sse2_unaligned_erms
if processor has ERMS. Default to __memcpy_sse2_unaligned.
(ENTRY): Removed.
(END): Likewise.
(ENTRY_CHK): Likewise.
(libc_hidden_builtin_def): Likewise.
Don't include ../memcpy.S.
* sysdeps/x86_64/multiarch/memcpy_chk.S (__memcpy_chk): Support
__memcpy_chk_avx512_unaligned_erms and
__memcpy_chk_avx512_unaligned. Use
__memcpy_chk_avx_unaligned_erms and
__memcpy_chk_sse2_unaligned_erms if if processor has ERMS.
Default to __memcpy_chk_sse2_unaligned.
* sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
Change function suffix from unaligned_2 to unaligned.
* sysdeps/x86_64/multiarch/mempcpy.S (__mempcpy): Support
__mempcpy_avx512_unaligned_erms and __mempcpy_avx512_unaligned.
Use __mempcpy_avx_unaligned_erms and __mempcpy_sse2_unaligned_erms
if processor has ERMS. Default to __mempcpy_sse2_unaligned.
(ENTRY): Removed.
(END): Likewise.
(ENTRY_CHK): Likewise.
(libc_hidden_builtin_def): Likewise.
Don't include ../mempcpy.S.
(mempcpy): New. Add a weak alias.
* sysdeps/x86_64/multiarch/mempcpy_chk.S (__mempcpy_chk): Support
__mempcpy_chk_avx512_unaligned_erms and
__mempcpy_chk_avx512_unaligned. Use
__mempcpy_chk_avx_unaligned_erms and
__mempcpy_chk_sse2_unaligned_erms if if processor has ERMS.
Default to __mempcpy_chk_sse2_unaligned.
Since the new SSE2/AVX2 memsets are faster than the previous ones, we
can remove the previous SSE2/AVX2 memsets and replace them with the
new ones. This reduces the size of libc.so by about 900 bytes.
No change in IFUNC selection if SSE2 and AVX2 memsets weren't used
before. If SSE2 or AVX2 memset was used, the new SSE2 or AVX2 memset
optimized with Enhanced REP STOSB will be used for processors with
ERMS. The new AVX512 memset will be used for processors with AVX512
which prefer vzeroupper.
[BZ #19881]
* sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S: Folded
into ...
* sysdeps/x86_64/memset.S: This.
(__bzero): Removed.
(__memset_tail): Likewise.
(__memset_chk): Likewise.
(memset): Likewise.
(MEMSET_CHK_SYMBOL): New. Define only if MEMSET_SYMBOL isn't
defined.
(MEMSET_SYMBOL): Define only if MEMSET_SYMBOL isn't defined.
* sysdeps/x86_64/multiarch/memset-avx2.S: Removed.
(__memset_zero_constant_len_parameter): Check SHARED instead of
PIC.
* sysdeps/x86_64/multiarch/Makefile (sysdep_routines): Remove
memset-avx2 and memset-sse2-unaligned-erms.
* sysdeps/x86_64/multiarch/ifunc-impl-list.c
(__libc_ifunc_impl_list): Remove __memset_chk_sse2,
__memset_chk_avx2, __memset_sse2 and __memset_avx2_unaligned.
* sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
(__bzero): Enabled.
* sysdeps/x86_64/multiarch/memset.S (memset): Replace
__memset_sse2 and __memset_avx2 with __memset_sse2_unaligned
and __memset_avx2_unaligned. Use __memset_sse2_unaligned_erms
or __memset_avx2_unaligned_erms if processor has ERMS. Support
__memset_avx512_unaligned_erms and __memset_avx512_unaligned.
(memset): Removed.
(__memset_chk): Likewise.
(MEMSET_SYMBOL): New.
(libc_hidden_builtin_def): Replace __memset_sse2 with
__memset_sse2_unaligned.
* sysdeps/x86_64/multiarch/memset_chk.S (__memset_chk): Replace
__memset_chk_sse2 and __memset_chk_avx2 with
__memset_chk_sse2_unaligned and __memset_chk_avx2_unaligned_erms.
Use __memset_chk_sse2_unaligned_erms or
__memset_chk_avx2_unaligned_erms if processor has ERMS. Support
__memset_chk_avx512_unaligned_erms and
__memset_chk_avx512_unaligned.
The i386 version of atanhl returns sNaN for sNaN input. This patch
fixes it to add NaN arguments to themselves so it returns qNaN in this
case.
Tested for x86_64 and x86.
[BZ #20219]
* sysdeps/i386/fpu/e_atanhl.S (__ieee754_atanhl): Add NaN argument
to itself.
* math/libm-test.inc (atanh_test_data): Add sNaN tests.
The i386 version of asinhl returns sNaN (without raising any
exceptions) for sNaN input. This patch fixes it to add non-finite
arguments to themselves, so that "invalid" is raised and qNaN
returned.
Tested for x86_64 and x86.
[BZ #20218]
* sysdeps/i386/fpu/s_asinhl.S (__asinhl): Add non-finite argument
to itself.
* math/libm-test.inc (asinh_test_data): Add sNaN tests.
Since the FMA4 bit is in COMMON_CPUID_INDEX_80000001 and FMA4 requires
AVX, determine if FMA4 is usable after COMMON_CPUID_INDEX_80000001 is
available and if AVX is usable.
[BZ #20195]
* sysdeps/x86/cpu-features.c (get_common_indeces): Move FMA4
check to ...
(init_cpu_features): Here.
In: https://sourceware.org/glibc/wiki/Synchronizing_Headers
we explain how we synchronize our headers with Linux kernel
headers.
In order to synchronize with the Linux linux/in6.h and
linux/ipv6.h headers we checked for their guard macros and
then defined __USE_KERNEL_IPV6_DEFS and conditionalized code
on this macro.
In upstream kernel 56c176c9 the _UAPI prefix was stripped and
this broke our synchronized headers again. We now need to check
for _LINUX_IN6_H and _IPV6_H, and keep checking the old versions
of the header guard checks for maximum backwards compatibility
with older Linux headers (the history is actually a bit muddled
here and it appears upstream linus kernel broke this 10 months
*before* our fix was ever applied to glibc, but without glibc
testing we didn't notice and distro kernels have their own
testing to fix this).
This patch fixes synchronization with linux/in6.h and
with netinet/in.h.
In C++11 18.5.12 says "Objects shall not be destroyed as a
result of calling quick_exit." In C11 quick_exit is silent
about thread object destruction. Therefore to make glibc
C++ compliant we do not call any thread local destructors.
A new regression test verifies the fix.
I will note that C++11 18.5.3 makes it clear that C++
defines additional requirements for _Exit() to prevent it
from executing destructors.
Given that the point of _Exit() is to terminate the process
immediately it makes sense the C and C++ should line up
and avoid calling destructors.
No failures. New regtest passes.
The dbl-64 version of asin returns sNaN for sNaN arguments. This
patch fixes it to add NaN arguments to themselves so that qNaN is
returned in this case.
Tested for x86_64 and x86.
[BZ #20213]
* sysdeps/ieee754/dbl-64/e_asin.c (__ieee754_asin): Add NaN
argument to itself.
* math/libm-test.inc (asin_test_data): Add sNaN tests.
This patch consolidates all the pwritev{64} implementation for Linux
in only one (sysdeps/unix/sysv/linux/pwritev{64}.c). It also removes the
syscall from the auto-generation using assembly macros.
It was based on previous pwrite/pwrite64 consolidation patch. The new macro
SYSCALL_LL{64} is used to handle the offset argument and alias is created
for __ASSUME_OFF_DIFF_OFF64 in case of pread64.
Checked on x86_64, i386, aarch64, and powerpc64le.
* misc/Makefile (CFLAGS-pwritev.c): New variable: add cancellation
required flags.
(CFLAGS-pwritev64.c): Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pwritev.c: Remove file.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pwritev64.c: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/pwritev64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/pwritev.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/pwritev64.: Likwise.
* sysdeps/unix/sysv/linux/x86_64/x32/syscalls.list (pwritev): Remove
syscall from auto-generation.
* sysdeps/unix/sysv/linux/pwritev.c: Rewrite implementation.
[WORDSIZE == 64] (pwritev64): Remove macro.
[!PWRITEV] (PWRITEV): Likewise.
[!PWRITEV] (PWRITEV_REPLACEMENT): Likewise.
[!PWRITEV] (PWRITE): Likewise.
[!PWRITEV] (OFF_T): Likewise.
[!__ASSUME_PWRITEV] (PWRITEV_REPLACEMENT): Likewise.
(LO_HI_LONG): Remove macro.
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwritev): Add function.
* sysdeps/unix/sysv/linux/pwritev64.c: Rewrite implementation.
(PWRITEV): Remove macro.
(PWRITEV_REPLACEMENTE): Likewise.
(PWRITE): Likewise.
(OFF_T): Likewise.
(pwritev64): New function.
* nptl/tst-cancel4.c (tf_writev): Add test.
This patch consolidates all the preadv{64} implementation for Linux
in only one (sysdeps/unix/sysv/linux/preadv{64}.c). It also removes the
syscall from the auto-generation using assembly macros.
It was based on previous pread/pread64 consolidation patch. The new macro
SYSCALL_LL{64} is used to handle the offset argument and alias is created
for __ASSUME_OFF_DIFF_OFF64 in case of pread64.
Checked on x86_64, i386, aarch64, and powerpc64le.
* misc/Makefile (CFLAGS-preadv.c): New variable: add cancellation
required flags.
(CFLAGS-preadv64.c): Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/preadv.c: Remove file.
* sysdeps/unix/sysv/linux/generic/wordsize-32/preadv64.c: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/preadv64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/preadv.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/preadv64.: Likwise.
* sysdeps/unix/sysv/linux/x86_64/x32/syscalls.list (preadv): Remove
syscall from auto-generation.
* sysdeps/unix/sysv/linux/preadv.c: Rewrite implementation.
[WORDSIZE == 64] (preadv64): Remove macro.
[!PREADV] (PREADV): Likewise.
[!PREADV] (PREADV_REPLACEMENT): Likewise.
[!PREADV] (PREAD): Likewise.
[!PREADV] (OFF_T): Likewise.
[!__ASSUME_PREADV] (PREADV_REPLACEMENT): Likewise.
(LO_HI_LONG): Remove macro.
[__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (preadv): Add function.
* sysdeps/unix/sysv/linux/preadv64.c: Rewrite implementation.
(PREADV): Remove macro.
(PREADV_REPLACEMENTE): Likewise.
(PREAD): Likewise.
(OFF_T): Likewise.
(preadv64): New function.
* nptl/tst-cancel4.c (tf_preadv): Add test.
The dbl-64 version of acos returns sNaN for sNaN arguments. This
patch fixes it to add NaN arguments to themselves so that qNaN is
returned in this case.
Tested for x86_64 and x86.
[BZ #20212]
* sysdeps/ieee754/dbl-64/e_asin.c (__ieee754_acos): Add NaN
argument to itself.
* math/libm-test.inc (acos_test_data): Add sNaN tests.
The x86 / x86_64 implementation of nextafterl (also used for
nexttowardl) produces incorrect results (NaNs) when negative
subnormals, the low 32 bits of whose mantissa are zero, are
incremented towards zero. This patch fixes this by disabling the
logic to decrement the exponent in that case.
Tested for x86_64 and x86.
[BZ #20205]
* sysdeps/i386/fpu/s_nextafterl.c (__nextafterl): Do not adjust
exponent when incrementing negative subnormal with low mantissa
word zero.
* math/libm-test.inc (nextafter_test_data) [TEST_COND_intel96]:
Add another test.
The use of __USE_KERNEL_IPV6_DEFS with ifndef is bad
practice per: https://sourceware.org/glibc/wiki/Wundef.
This change moves it to use 'if' and always define the
macro.
Please note that this is not the only problem with this
code. I have a series of fixes after this one to resolve
breakage with this code and add regression tests for it
via compile-only source testing (to be discussed in another
thread).
Unfortunately __USE_KERNEL_XATTR_DEFS is set by the kernel
and not glibc, and uses 'define', so we can't fix that yet.
This patch call _exit instead of exit in failure case for the spawned
child in Linux posix_spawn{p} implementation.
Tested on x86_64.
[BZ #20178]
* sysdeps/unix/sysv/linux/spawni.c (__spawni_child): Call _exit
on failure instead of exit.
For Intel processors, when there are both L2 and L3 caches, SMT level
type should be ued to count number of available logical processors
sharing L2 cache. If there is only L2 cache, core level type should
be used to count number of available logical processors sharing L2
cache. Number of available logical processors sharing L2 cache should
be used for non-inclusive L2 and L3 caches.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Count number of
available logical processors with SMT level type sharing L2
cache for Intel processors.
The powerpc64 versions of ceil, floor, round, trunc, rint, nearbyint
and their float versions return sNaN for sNaN input when they should
return qNaN. This patch fixes them to add a NaN argument to itself to
quiet sNaNs before returning.
Tested for powerpc64.
[BZ #20160]
* sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Add NaN
argument to itself before returning the result.
* sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyint.S (__nearbyint):
Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_nearbyintf.S (__nearbyintf):
Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rint.S (__rint): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_rintf.S (__rintf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_round.S (__round): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_roundf.S (__roundf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
The powerpc32 versions of ceil, floor, round, trunc, rint, nearbyint
and their float versions return sNaN for sNaN input when they should
return qNaN. This patch fixes them to add a NaN argument to itself to
quiet sNaNs before returning. The powerpc64 versions, which have the
same bug, will be addressed separately.
Tested for powerpc32.
[BZ #20160]
* sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Add NaN
argument to itself before returning the result.
* sysdeps/powerpc/powerpc32/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_floor.S (__floor): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_nearbyint.S (__nearbyint):
Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_nearbyintf.S (__nearbyintf):
Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_rint.S (__rint): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_rintf.S (__rintf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_round.S (__round): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_roundf.S (__roundf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_trunc.S (__trunc): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_truncf.S (__truncf): Likewise.
The powerpc implementations of fabsl for ldbl-128ibm (both powerpc32
and powerpc64) wrongly raise the "invalid" exception for sNaN
arguments. fabs functions should be quiet for all inputs including
signaling NaNs. The problem is the use of a comparison instruction
fcmpu to determine if the high part of the argument is negative and so
the low part needs to be negated; such instructions raise "invalid"
for sNaNs.
There is a pure integer implementation of fabsl in
sysdeps/ieee754/ldbl-128ibm/s_fabsl.c. However, it's not necessary to
use it to avoid such exceptions. The fsel instruction does not raise
exceptions for sNaNs, and can be used in place of the original
comparison. (Note that if the high part is zero or a NaN, it does not
matter whether the low part is negated; the choice of whether the low
part of a zero is +0 or -0 does not affect the value, and the low part
of a NaN does not affect the value / payload either.)
The condition in GCC for fsel to be available is TARGET_PPC_GFXOPT,
corresponding to the _ARCH_PPCGR predefined macro. fsel is available
on all 64-bit processors supported by GCC. A few 32-bit processors
supported by GCC do not have TARGET_PPC_GFXOPT despite having hard
float support. To support those processors, integer code (similar to
that in copysignl) is included for the !_ARCH_PPCGR case for
powerpc32.
Tested for powerpc32 (configurations with and without _ARCH_PPCGR) and
powerpc64.
[BZ #20157]
* sysdeps/powerpc/powerpc32/fpu/s_fabsl.S (__fabsl): Use fsel to
determine whether to negate low half if [_ARCH_PPCGR], and integer
comparison otherwise.
* sysdeps/powerpc/powerpc64/fpu/s_fabsl.S (__fabsl): Use fsel to
determine whether to negate low half.
The ldbl-128ibm implementations of ceill, floorl, roundl, truncl,
rintl and nearbyintl wrongly return an sNaN when given an sNaN
argument. This patch fixes them to add such an argument to itself to
turn it into a quiet NaN. (The code structure means this "else" case
applies to any argument which is zero or not finite; it's OK to do
this in all such cases.)
Tested for powerpc.
[BZ #20156]
* sysdeps/ieee754/ldbl-128ibm/s_ceill.c (__ceill): Add high part
to itself when zero or not finite.
* sysdeps/ieee754/ldbl-128ibm/s_floorl.c (__floorl): Likewise.
* sysdeps/ieee754/ldbl-128ibm/s_rintl.c (__rintl): Likewise.
* sysdeps/ieee754/ldbl-128ibm/s_roundl.c (__roundl): Likewise.
* sysdeps/ieee754/ldbl-128ibm/s_truncl.c (__truncl): Likewise.
The ldbl-128ibm implementation of sqrtl wrongly returns an sNaN for
signaling NaN arguments. This patch fixes it to quiet its argument,
using the same x * x + x return for infinities and NaNs as the dbl-64
implementation uses to ensure that +Inf maps to +Inf while -Inf and
NaN map to NaN.
Tested for powerpc.
[BZ #20153]
* sysdeps/ieee754/ldbl-128ibm/e_sqrtl.c (__ieee754_sqrtl): Return
x * x + x for infinities and NaNs.
The ldbl-128 implementations of j0l, j1l, y0l, y1l (also used for
ldbl-128ibm) return an sNaN argument unchanged. This patch fixes them
to add a NaN argument to itself to quiet it before return.
Tested for mips64.
[BZ #20151]
* sysdeps/ieee754/ldbl-128/e_j0l.c (__ieee754_j0l): Add NaN
argument to itself before returning result.
(__ieee754_y0l): Likewise.
* sysdeps/ieee754/ldbl-128/e_j1l.c (__ieee754_j1l): Likewise.
(__ieee754_y1l).
This patch fixes wrong/missing bits from the Fix {recv,send}{m}msg
standard compliance (BZ#16919) patches:
* nptl/Makefile sets CFLAGS-oldrecvfrom.c, but there's no such file as
oldrecvfrom.c. It should be oldsendmsg.c as defined by ChangeLog.
* sysdeps/unix/sysv/linux/hppa/Versions and
sysdeps/unix/sysv/linux/i386/Versions list a symbol recvms instead of
recvmsg at version GLIBC_2.24.
* nptl/Makefile (CFLAGS-oldrecvfrom.c): Remove rule.
(CFLAGS-oldsendmsg.c): Add rule.
* sysdeps/unix/sysv/linux/hppa/Versions [libc] (GLIBC_2.24):
Correct recvmsg symbol name.
* sysdeps/unix/sysv/linux/i386/Versions [libc] (GLIBC_2.24):
Likewise.
POSIX specifies that both msghdr::msg_iovlen and msghdr::msg_controllen
to be of size int and socklen_t respectively, however Linux implements
it as a size_t. So for 64-bits architecture where sizeof of size_t is
larger than socklen_t, both sendmmsg and recvmmsg need to adjust the
mmsghdr::msg_hdr internal fields before issuing the syscall itself.
This patch fixes it by operating on the padding if it the case.
For recvmmsg, the most straightfoward case, only zero padding the fields
is suffice. However, for sendmmsg, where adjusting the buffer is out
of the contract (since it may point to a read-only data), the function
is rewritten to use sendmsg instead (which from previous patch
allocates a temporary msghdr to operate on).
Also for 64-bit ports that requires it, a new recvmmsg and sendmmsg
compat version is created (which uses size_t for both cmsghdr::cmsg_len
and internal
Tested on x86_64, i686, aarch64, armhf, and powerpc64le.
* sysdeps/unix/sysv/linux/Makefile
[$(subdir) = socket] (sysdep_routines): Add oldrecvmmsg and
oldsendmmsg.
* sysdeps/unix/sysv/linux/aarch64/libc.abilist: Add recvmmsg and
sendmmsg.
* sysdeps/unix/sysv/linux/alpha/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/ia64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/libc.abilist: Likewise.
* sysdeps/sysv/linux/powerpc/powerpc64/libc-le.abilist: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/s390/s390-64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/tile/tilegx/tilegx64/libc.abilist:
Likewise.
* sysdeps/unix/sysv/linux/x86_64/64/libc.abilist: Likewise.
* sysdeps/unix/sysv/linux/oldrecvmmsg.c: New file.
* sysdeps/unix/sysv/linux/oldsendmmsg.c: Likewise.
* sysdeps/unix/sysv/linux/recvmmsg.c (__recvmmsg): Adjust msghdr
iovlen and controllen fields to adjust to POSIX specification.
* sysdeps/unix/sysv/linux/sendmmsg.c (__sendmmsg): Likewise.
Continuing fixes for ceil, floor and trunc functions not to raise the
"inexact" exception, this patch fixes the versions used on older
powerpc64 processors. As was done with the round implementations some
time ago, the save of floating-point state is moved after the first
floating-point operation on the input to ensure that any "invalid"
exception from signaling NaN input is included in the saved state, and
then the whole state gets restored rather than just the rounding mode.
This has no effect on configurations using the power5+ code, since
such processors can do these operations with a single instruction (and
those instructions do not set "inexact", so are correct for TS 18661-1
semantics).
Tested for powerpc64.
[BZ #15479]
* sysdeps/powerpc/powerpc64/fpu/s_ceil.S (__ceil): Move save of
floating-point state after first floating-point operation on
input. Restore full floating-point state instead of just rounding
mode.
* sysdeps/powerpc/powerpc64/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floor.S (__floor): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_trunc.S (__trunc): Likewise.
* sysdeps/powerpc/powerpc64/fpu/s_truncf.S (__truncf): Likewise.
Continuing fixes for ceil, floor and trunc functions not to raise the
"inexact" exception, this patch fixes the versions used on older
powerpc32 processors. As was done with the round implementations some
time ago, the save of floating-point state is moved after the first
floating-point operation on the input to ensure that any "invalid"
exception from signaling NaN input is included in the saved state, and
then the whole state gets restored rather than just the rounding mode.
This has no effect on configurations using the power5+ code, since
such processors can do these operations with a single instruction (and
those instructions do not set "inexact", so are correct for TS 18661-1
semantics).
Tested for powerpc32.
[BZ #15479]
* sysdeps/powerpc/powerpc32/fpu/s_ceil.S (__ceil): Move save of
floating-point state after first floating-point operation on
input. Restore full floating-point state instead of just rounding
mode.
* sysdeps/powerpc/powerpc32/fpu/s_ceilf.S (__ceilf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_floor.S (__floor): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_floorf.S (__floorf): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_trunc.S (__trunc): Likewise.
* sysdeps/powerpc/powerpc32/fpu/s_truncf.S (__truncf): Likewise.
According to the latest Unicode standard, a conversion from/to UTF-xx has
to report an error if the character value is in range of an utf16 surrogate
(0xd800..0xdfff). See https://sourceware.org/ml/libc-help/2015-12/msg00015.html.
Thus the cu42 instruction, which converts from utf32 to utf16, has to be
disabled because it does not report an error in case of a value in range of
a low surrogate (0xdc00..0xdfff). The etf3eh variant is removed and the c,
vector variant is adjusted to handle the value in range of an utf16 low
surrogate correctly.
ChangeLog:
* sysdeps/s390/utf16-utf32-z9.c: Disable cu42 instruction and report
an error in case of a value in range of an utf16 low surrogate.
According to the latest Unicode standard, a conversion from/to UTF-xx has
to report an error if the character value is in range of an utf16 surrogate
(0xd800..0xdfff). See https://sourceware.org/ml/libc-help/2015-12/msg00015.html.
Thus the cu41 instruction, which converts from utf32 to utf8, has to be
disabled because it does not report an error in case of a value in range of
a low surrogate (0xdc00..0xdfff). The etf3eh variant is removed and the c,
vector variant is adjusted to handle the value in range of an utf16 low
surrogate correctly.
ChangeLog:
* sysdeps/s390/utf8-utf32-z9.c: Disable cu41 instruction and report
an error in case of a value in range of an utf16 low surrogate.
This patch reworks the existing s390 64bit specific iconv modules in order
to use them on s390 31bit, too.
Thus the parts for subdirectory iconvdata in sysdeps/s390/s390-64/Makefile
were moved to sysdeps/s390/Makefile so that they apply on 31bit, too.
All those modules are moved from sysdeps/s390/s390-64 directory to sysdeps/s390.
The iso-8859-1 to/from cp037 module was adjusted, to use brct (branch relative
on count) instruction on 31bit s390 instead of brctg, because the brctg is a
zarch instruction and is not available on a 31bit kernel.
The utf modules are using zarch instructions, thus the directive machinemode
zarch_nohighgprs was added to the inline assemblies to omit the high-gprs flag
in the shared libraries. Otherwise they can't be loaded on a 31bit kernel.
The ifunc resolvers were adjusted in order to call the etf3eh or vector variants
only if zarch instructions are available (64bit kernel in 31bit compat-mode).
Furthermore some variable types were changed. E.g. unsigned long long would be
a register pair on s390 31bit, but we want only one single register.
For variables of type size_t the register contents have to be enlarged from a
32bit to a 64bit value on 31bit, because the inline assemblies uses 64bit values
in such cases.
ChangeLog:
* sysdeps/s390/s390-64/Makefile (iconvdata-subdirectory):
Move to ...
* sysdeps/s390/Makefile: ... here.
* sysdeps/s390/s390-64/iso-8859-1_cp037_z900.c: Move to ...
* sysdeps/s390/iso-8859-1_cp037_z900.c: ... here.
(BRANCH_ON_COUNT): New define.
(TR_LOOP): Use BRANCH_ON_COUNT instead of brctg.
* sysdeps/s390/s390-64/utf16-utf32-z9.c: Move to ...
* sysdeps/s390/utf16-utf32-z9.c: ... here and adjust to
run on s390-32, too.
* sysdeps/s390/s390-64/utf8-utf16-z9.c: Move to ...
* sysdeps/s390/utf8-utf16-z9.c: ... here and adjust to
run on s390-32, too.
* sysdeps/s390/s390-64/utf8-utf32-z9.c: Move to ...
* sysdeps/s390/utf8-utf32-z9.c: ... here and adjust to
run on s390-32, too.
This patch reworks the s390 specific module to convert between utf16 and utf32.
Now ifunc is used to choose either the c or etf3eh (with convert utf
instruction) variants at runtime.
Furthermore a new vector variant for z13 is introduced which will be build
and chosen if vector support is available at build / runtime.
In case of converting utf 32 to utf16, the vector variant optimizes input of
2byte utf16 characters. The convert utf instruction is used if an utf16
surrogate is found.
For the other direction utf16 to utf32, the cu24 instruction can't be re-
enabled, because it does not report an error, if the input-stream consists of
a single low surrogate utf16 char (e.g. 0xdc00). This applies to the newest z13,
too. Thus there is only the c or the new vector variant, which can handle utf16
surrogate characters.
This patch also fixes some whitespace errors. Furthermore, the etf3eh variant is
handling the "UTF-xx//IGNORE" case now. Before they ignored the ignore-case and
always stopped at an error.
ChangeLog:
* sysdeps/s390/s390-64/utf16-utf32-z9.c: Use ifunc to select c,
etf3eh or new vector loop-variant.
This patch reworks the s390 specific module to convert between utf8 and utf16.
Now ifunc is used to choose either the c or etf3eh (with convert utf instruction)
variants at runtime. Furthermore a new vector variant for z13 is introduced
which will be build and chosen if vector support is available at build / runtime.
In case of converting utf 8 to utf16, the vector variant optimizes input of
1byte utf8 characters. The convert utf instruction is used if a multibyte utf8
character is found.
For the other direction utf16 to utf8, the cu21 instruction can't be re-enabled,
because it does not report an error, if the input-stream consists of a single
low surrogate utf16 char (e.g. 0xdc00). This applies to the newest z13, too.
Thus there is only the c or the new vector variant, which can handle 1..4 byte
utf8 characters.
The c variant from utf16 to utf8 has beed fixed. If a high surrogate was at the
end of the input-buffer, then errno was set to EINVAL and the input-pointer
pointed just after the high surrogate. Now it points to the beginning of the
high surrogate.
This patch also fixes some whitespace errors. The c variant from utf8 to utf16
is now checking that tail-bytes starts with 0b10... and the value is not in
range of an utf16 surrogate.
Furthermore, the etf3eh variants are handling the "UTF-xx//IGNORE" case now.
Before they ignored the ignore-case and always stopped at an error.
ChangeLog:
* sysdeps/s390/s390-64/utf8-utf16-z9.c: Use ifunc to select c,
etf3eh or new vector loop-variant.
This patch reworks the s390 specific module to convert between utf8 and utf32.
Now ifunc is used to choose either the c or etf3eh (with convert utf
instruction) variants at runtime.
Furthermore a new vector variant for z13 is introduced which will be build
and chosen if vector support is available at build / runtime.
The vector variants optimize input of 1byte utf8 characters. The convert utf
instruction is used if a multibyte utf8 character is found.
This patch also fixes some whitespace errors. The c variants are rejecting
UTF-16 surrogates and values above 0x10ffff now.
Furthermore, the etf3eh variants are handling the "UTF-xx//IGNORE" case now.
Before they ignored the ignore-case and always stopped at an error.
ChangeLog:
* sysdeps/s390/s390-64/utf8-utf32-z9.c: Use ifunc to select c, etf3eh
or new vector loop-variant.
This patch reworks the s390 specific module which used the z900
translate one to one instruction. Now the g5 translate instruction is used,
because it outperforms the troo instruction.
ChangeLog:
* sysdeps/s390/s390-64/iso-8859-1_cp037_z900.c (TROO_LOOP):
Rename to TR_LOOP and usage of tr instead of troo instruction.
This patch introduces a s390 specific gconv_simple.c file which provides
optimized versions for z13 with vector instructions, which will be chosen at
runtime via ifunc.
The optimized conversions can convert between internal and ascii, ucs4, ucs4le,
ucs2, ucs2le.
If the build-environment lacks vector support, then iconv/gconv_simple.c
is used wihtout any change. Otherwise iconvdata/gconv_simple.c is used to create
conversion loop routines without vector instructions as fallback, if vector
instructions aren't available at runtime.
ChangeLog:
* sysdeps/s390/multiarch/gconv_simple.c: New File.
* sysdeps/s390/multiarch/Makefile (sysdep_routines): Add gconv_simple.
This patch introduces a s390 specific 8bit-generic.c file which provides an
optimized version for z13 with translate-/vector-instructions, which will be
chosen at runtime via ifunc.
If the build-environment lacks vector support, then iconvdata/8bit-generic.c
is used wihtout any change. Otherwise iconvdata/8bit-generic.c is used to create
conversion loop routines without vector instructions as fallback, if vector
instructions aren't available at runtime.
The vector routines can only be used with charsets where the maximum UCS4 value
fits in 1 byte size. Then the hardware translate-instruction is used
to translate between up to 256 generic characters and "1 byte UCS4"
characters at once. The vector instructions are used to convert between
the "1 byte UCS4" and UCS4.
The gen-8bit.sh script in sysdeps/s390/multiarch generates the conversion
table to_ucs1. Therefore in sysdeps/s390/multiarch/Makefile is added an
override define generate-8bit-table, which is originally defined in
iconvdata/Makefile. This version calls the gen-8bit.sh in iconvdata folder
and the s390 one.
ChangeLog:
* sysdeps/s390/multiarch/8bit-generic.c: New File.
* sysdeps/s390/multiarch/gen-8bit.sh: New File.
* sysdeps/s390/multiarch/Makefile (generate-8bit-table):
New override define.
* sysdeps/s390/multiarch/iconv/skeleton.c: Likewise.
The S390 specific test checks if the gcc has support for vector registers
by compiling an inline assembly which clobbers vector registers.
On success the macro HAVE_S390_VX_GCC_SUPPORT is defined.
This macro can be used to determine if e.g. clobbering vector registers
is allowed or not.
ChangeLog:
* config.h.in (HAVE_S390_VX_GCC_SUPPORT): New macro undefine.
* sysdeps/s390/configure.ac: Add test for S390 vector register
support in gcc.
* sysdeps/s390/configure: Regenerated.
This patch introduces a way to provide an architecture dependent gconv-modules
file. Before this patch, the gconv-modules file was normally installed from
src-dir/iconvdata/gconv-modules. The S390 Makefile had overridden the
installation recipe (with a make warning) in order to install the
gconv-module-s390 file from build-dir.
The iconvdata/Makefile provides another recipe, which copies the gconv-modules
file from src to build dir, which are used by the testcases.
Thus the testcases does not use the currently build s390-modules.
This patch uses build-dir/iconvdata/gconv-modules for installation, which
is generated by concatenating src-dir/iconvdata/gconv-modules and the
architecture specific one. The latter one can be specified by setting the variable
sysdeps-gconv-modules in sysdeps/.../Makefile.
The architecture specific gconv-modules file is emitted before the common one
because these modules aren't used in all possible conversions. E.g. the converting
from INTERNAL to UTF-16 used the common UTF-16.so module instead of UTF16_UTF32_Z9.so.
This way, the s390-Makefile does not need to override the recipe for gconv-modules
and no warning is emitted anymore.
Since we no longer support empty objpfx the conditional test in iconvdata/Makefile
is removed.
ChangeLog:
* iconvdata/Makefile ($(inst_gconvdir)/gconv-modules):
Install file from $(objpfx)gconv-modules.
($(objpfx)gconv-modules): Concatenate architecture specific file
in variable sysdeps-gconv-modules and gconv-modules in src dir.
* sysdeps/s390/gconv-modules: New file.
* sysdeps/s390/s390-64/Makefile: ($(inst_gconvdir)/gconv-modules):
Deleted.
($(objpfx)gconv-modules-s390): Deleted.
(sysdeps-gconv-modules): New variable.
Continuing fixes for ceil and floor functions not to raise the
"inexact" exception, this patch fixes the x86_64 SSE4.1 versions. The
roundss / roundsd instructions take an immediate operand that
determines the rounding mode and whether to raise "inexact"; this just
needs bit 3 set to disable "inexact", which this patch does.
Remark: we don't have an SSE4.1 version of trunc / truncf (using this
instruction with operand 11); I'd expect one to make sense, but of
course it should be benchmarked against the existing C code. I'll
file a bug in Bugzilla for the lack of such a version.
Tested for x86_64.
[BZ #15479]
* sysdeps/x86_64/fpu/multiarch/s_ceil.S (__ceil_sse41): Set bit 3
of immediate operand to rounding instruction.
* sysdeps/x86_64/fpu/multiarch/s_ceilf.S (__ceilf_sse41):
Likewise.
* sysdeps/x86_64/fpu/multiarch/s_floor.S (__floor_sse41):
Likewise.
* sysdeps/x86_64/fpu/multiarch/s_floorf.S (__floorf_sse41):
Likewise.
C99 and C11 allow but do not require ceil, floor, round and trunc to
raise the "inexact" exception for noninteger arguments. TS 18661-1
requires that this exception not be raised by these functions. This
aligns them with general IEEE semantics, where "inexact" is only
raised if the final step of rounding the infinite-precision result to
the result type is inexact; for these functions, the
infinite-precision integer result is always representable in the
result type, so "inexact" should never be raised.
The generic implementations of ceil, floor and round functions contain
code to force "inexact" to be raised. This patch removes it for round
functions to align them with TS 18661-1 in this regard. The tests
*are* updated by this patch; there are fewer architecture-specific
versions than for ceil and floor, and I fixed the powerpc ones some
time ago. If any others still have the issue, as shown by tests for
round failing with spurious exceptions, they can be fixed separately
by architecture maintainers or others.
Tested for x86_64, x86 and mips64.
[BZ #15479]
* sysdeps/ieee754/dbl-64/s_round.c (huge): Remove variable.
(__round): Do not force "inexact" exception.
* sysdeps/ieee754/dbl-64/wordsize-64/s_round.c (huge): Remove
variable.
(__round): Do not force "inexact" exception.
* sysdeps/ieee754/flt-32/s_roundf.c (huge): Remove variable.
(__roundf): Do not force "inexact" exception.
* sysdeps/ieee754/ldbl-128/s_roundl.c (huge): Remove variable.
(__roundl): Do not force "inexact" exception.
* sysdeps/ieee754/ldbl-96/s_roundl.c (huge): Remove variable.
(__roundl): Do not force "inexact" exception.
* math/libm-test.inc (round_test_data): Do not allow spurious
"inexact" exceptions.
C99 and C11 allow but do not require ceil, floor, round and trunc to
raise the "inexact" exception for noninteger arguments. TS 18661-1
requires that this exception not be raised by these functions. This
aligns them with general IEEE semantics, where "inexact" is only
raised if the final step of rounding the infinite-precision result to
the result type is inexact; for these functions, the
infinite-precision integer result is always representable in the
result type, so "inexact" should never be raised.
The generic implementations of ceil, floor and round functions contain
code to force "inexact" to be raised. This patch removes it for floor
functions to align them with TS 18661-1 in this regard. Note that
some architecture-specific versions may still raise "inexact", so the
tests are not updated and the bug is not yet fixed.
Tested for x86_64, x86 and mips64.
[BZ #15479]
* sysdeps/ieee754/dbl-64/s_floor.c: Do not mention "inexact"
exception in comment.
(huge): Remove variable.
(__floor): Do not force "inexact" exception.
* sysdeps/ieee754/dbl-64/wordsize-64/s_floor.c: Do not mention
"inexact" exception in comment.
(huge): Remove variable.
(__floor): Do not force "inexact" exception.
* sysdeps/ieee754/flt-32/s_floorf.c: Do not mention "inexact"
exception in comment.
(huge): Remove variable.
(__floorf): Do not force "inexact" exception.
* sysdeps/ieee754/ldbl-128/s_floorl.c: Do not mention "inexact"
exception in comment.
(huge): Remove variable.
(__floorl): Do not force "inexact" exception.
C99 and C11 allow but do not require ceil, floor, round and trunc to
raise the "inexact" exception for noninteger arguments. TS 18661-1
requires that this exception not be raised by these functions. This
aligns them with general IEEE semantics, where "inexact" is only
raised if the final step of rounding the infinite-precision result to
the result type is inexact; for these functions, the
infinite-precision integer result is always representable in the
result type, so "inexact" should never be raised.
The generic implementations of ceil, floor and round functions contain
code to force "inexact" to be raised. This patch removes it for ceil
functions to align them with TS 18661-1 in this regard. Note that
some architecture-specific versions may still raise "inexact", so the
tests are not updated and the bug is not yet fixed.
Tested for x86_64, x86 and mips64.
[BZ #15479]
* sysdeps/ieee754/dbl-64/s_ceil.c: Do not mention "inexact"
exception in comment.
(huge): Remove variable.
(__ceil): Do not force "inexact" exception.
* sysdeps/ieee754/dbl-64/wordsize-64/s_ceil.c: Do not mention
"inexact" exception in comment.
(huge): Remove variable.
(__ceil): Do not force "inexact" exception.
* sysdeps/ieee754/flt-32/s_ceilf.c (huge): Remove variable.
(__ceilf): Do not force "inexact" exception.
* sysdeps/ieee754/ldbl-128/s_ceill.c: Do not mention "inexact"
exception in comment.
(huge): Remove variable.
(__ceill): Do not force "inexact" exception.
When --enable-bind-now is used to configure glibc build, we can avoid
an extra branch to the PLT entry by using indirect branch via the GOT
slot instead, which is similar to the first instructuon in the PLT
entry. Changes in the shared library sizes in text sections:
Shared library Before (bytes) After (bytes)
libm.so 1060813 1060797
libmvec.so 160881 160805
libpthread.so 94992 94984
librt.so 25064 25048
* config.h.in (BIND_NOW): New.
* configure.ac (BIND_NOW): New. Defined for --enable-bind-now.
* configure: Regenerated.
* sysdeps/x86_64/sysdep.h (JUMPTARGET)[BIND_NOW]: Defined to
indirect branch via the GOT slot.
There exist optimized memcpy functions on s390, but no optimized mempcpy.
This patch adds mempcpy entry points in memcpy.S files, which
use the memcpy implementation. Now mempcpy itself is also an IFUNC function
as memcpy is and the variants are listed in ifunc-impl-list.c.
The s390 string.h does not define _HAVE_STRING_ARCH_mempcpy.
Instead mempcpy string/string.h inlines memcpy() + n.
If n is constant and small enough, GCC emits instructions like mvi or mvc
and avoids the function call to memcpy.
If n is not constant, then memcpy is called and n is added afterwards.
If _HAVE_STRING_ARCH_mempcpy would be defined, mempcpy would be called in
every case.
According to PR70140 "Inefficient expansion of __builtin_mempcpy"
(https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70140) GCC should handle a
call to mempcpy in the same way as memcpy. Then either the mempcpy macro
in string/string.h has to be removed or _HAVE_STRING_ARCH_mempcpy has to
be defined for S390.
ChangeLog:
[BZ #19765]
* sysdeps/s390/mempcpy.S: New File.
* sysdeps/s390/multiarch/mempcpy.c: Likewise.
* sysdeps/s390/multiarch/Makefile (sysdep_routines): Add mempcpy.
* sysdeps/s390/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list):
Add mempcpy variants.
* sysdeps/s390/s390-32/memcpy.S: Add mempcpy entry point.
(memcpy): Adjust to be usable from mempcpy entry point.
(__memcpy_mvcle): Likewise.
* sysdeps/s390/s390-64/memcpy.S: Likewise.
* sysdeps/s390/s390-32/multiarch/memcpy-s390.S: Add entry points
____mempcpy_z196, ____mempcpy_z10 and add __GI_ symbols for mempcpy.
(__memcpy_z196): Adjust to be usable from mempcpy entry point.
(__memcpy_z10): Likewise.
* sysdeps/s390/s390-64/multiarch/memcpy-s390x.S: Likewise.
On s390, the memcpy, memcmp, memset functions are IFUNC symbols,
which are created with s390_libc_ifunc-macro.
This macro creates a __GI_ symbol which is set to the
ifunced symbol. Thus calls within libc.so to e.g. memcpy
result in a call to *ABS*+0x954c0@plt stub and afterwards
to the resolved memcpy-ifunc-variant.
This patch sets the __GI_ symbol to the default-ifunc-variant
to avoid the plt call. The __GI_ symbols are now created at the
default variant of ifunced function.
ChangeLog:
* sysdeps/s390/multiarch/ifunc-resolve.h (s390_libc_ifunc):
Remove __GI_ symbol.
* sysdeps/s390/s390-32/multiarch/memcmp-s390.S: Add __GI_memcmp symbol.
* sysdeps/s390/s390-64/multiarch/memcmp-s390x.S: Likewise.
* sysdeps/s390/s390-32/multiarch/memcpy-s390.S: Add __GI_memcpy symbol.
* sysdeps/s390/s390-64/multiarch/memcpy-s390x.S: Likewise.
* sysdeps/s390/s390-32/multiarch/memset-s390.S: Add __GI_memset symbol.
* sysdeps/s390/s390-64/multiarch/memset-s390x.S: Likewise.
The __memcpy_default variant on s390 64bit calculates the number of
256byte blocks in a 64bit register and checks, if they exceed 1MB
to jump to mvcle. Otherwise a mvc-loop is used. The compare-instruction
only checks a 32bit value.
This patch uses a 64bit compare.
ChangeLog:
* sysdeps/s390/s390-64/memcpy.S (memcpy):
Use cghi instead of chi to compare 64bit value.
If more than 255 bytes should be copied, the algorithm jumps away.
Before this patch, it jumps to the mvc-loop (.L_G5_12).
Now it jumps first to the "> 1MB" check, which jumps away to
__memcpy_mvcle. Otherwise, the mvc-loop (.L_G5_12) copies the bytes.
ChangeLog:
* sysdeps/s390/s390-32/memcpy.S (memcpy):
Jump to 1MB check before executing mvc-loop.
This avoids aliasing issues with GCC 6 in -fno-strict-aliasing
mode. (With implicit padding, not all data is copied.)
This change makes it explicit that struct sockaddr_storage is
only 126 bytes large on m68k (unlike elsewhere, where we end up
with the requested 128 bytes). The new test case makes sure that
this does not happen on other architectures.
This patch updates sysdeps/unix/sysv/linux/bits/socket.h for new
constants added in Linux 4.6. AF_KCM / PF_KCM are added. SOL_KCM is
new, and I added a lot of SOL_* values postdating the last one present
in the header, since I saw no apparent reason for the set in glibc to
stop at SOL_IRDA. MSG_BATCH is added; Linux also has
MSG_SENDPAGE_NOTLAST which is not in glibc, but given the comment
starts "sendpage() internal" I presume it's correct for it not to be
in glibc.
(Note that this is a case where the Linux kernel header with userspace
relevant values is *not* a uapi header but include/linux/socket.h - I
don't know why, but at least this header, as well as uapi headers,
needs reviewing for glibc-relevant changes each release.)
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by the patch).
* sysdeps/unix/sysv/linux/bits/socket.h (PF_KCM): New macro.
(PF_MAX): Update value.
(AF_KCM): New macro.
(SOL_NETBEUI): Likewise.
(SOL_LLC): Likewise.
(SOL_DCCP): Likewise.
(SOL_NETLINK): Likewise.
(SOL_TIPC): Likewise.
(SOL_RXRPC): Likewise.
(SOL_PPPOL2TP): Likewise.
(SOL_BLUETOOTH): Likewise.
(SOL_PNPIPE): Likewise.
(SOL_RDS): Likewise.
(SOL_IUCV): Likewise.
(SOL_CAIF): Likewise.
(SOL_ALG): Likewise.
(SOL_NFC): Likewise.
(SOL_KCM): Likewise.
(MSG_BATCH): New enum value and macro.
L2 cache is shared by 2 cores on Knights Landing, which has 4 threads
per core:
https://en.wikipedia.org/wiki/Xeon_Phi#Knights_Landing
So L2 cache is shared by 8 threads on Knights Landing as reported by
CPUID. We should remove special L2 cache case for Knights Landing.
[BZ #18185]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Don't limit threads
sharing L2 cache to 2 for Knights Landing.
ldbl-128ibm had an implementation of fmal that just did (x * y) + z in
most cases, with no attempt at actually being a fused operation.
This patch replaces it with a genuine fused operation. It is not
necessarily correctly rounding, but should produce a result at least
as accurate as the long double arithmetic operations in libgcc, which
I think is all that can reasonably be expected for such a non-IEEE
format where arithmetic is approximate rather than rounded according
to any particular rule for determining the exact result. Like the
libgcc arithmetic, it may produce spurious overflow and underflow
results, and it falls back to the libgcc multiplication in the case of
(finite, finite, zero).
This concludes the fixes for bug 13304; any subsequently found fma
issues should go in separate Bugzilla bugs. Various other pieces of
bug 13304 were fixed in past releases over the past several years.
Tested for powerpc.
[BZ #13304]
* sysdeps/ieee754/ldbl-128ibm/s_fmal.c: Include <fenv.h>,
<float.h>, <math_private.h> and <stdlib.h>.
(add_split): New function.
(mul_split): Likewise.
(ext_val): New typedef.
(store_ext_val): New function.
(mul_ext_val): New function.
(compare): New function.
(add_split_ext): New function.
(__fmal): After checking for Inf, NaN and zero, compute result as
an exact sum of scaled double values in round-to-nearest before
adding those up and adjusting for other rounding modes.
* math/auto-libm-test-in: Remove xfail-rounding:ldbl-128ibm from
tests of fma.
* math/auto-libm-test-out: Regenerated.
Intel CPUID with EAX == 11 returns:
ECX Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type.
^^^^^^^^^^^^^^^^^^^^^^^^ This is level type.
Bits 31 - 16: Reserved.
Intel processor level type mask should be 0xff00, not 0xff0.
[BZ #20119]
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Correct Intel
processor level type mask for CPUID with EAX == 11.
Skip counting logical threads for Intel processors if the HTT bit is 0
which indicates there is only a single logical processor.
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
logical threads if the HTT bit is 0.
* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
(index_cpu_HTT): Likewise.
(reg_HTT): Likewise.
X86-64 memset-vec-unaligned-erms.S aligns many jump targets, which
increases code sizes, but not necessarily improve performance. As
memset benchtest data of align vs no align on various Intel and AMD
processors
https://sourceware.org/bugzilla/attachment.cgi?id=9277
shows that aligning jump targets isn't necessary.
[BZ #20115]
* sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S (__memset):
Remove alignments on jump targets.
There is no need to call the internal funtion, _Unwind_Resume, which
is defined in unwind-forcedunwind.c, via PLT.
* sysdeps/unix/sysv/linux/x86_64/pthread_cond_timedwait.S
(__condvar_cleanup2): Remove JUMPTARGET from _Unwind_Resume
call.
* sysdeps/unix/sysv/linux/x86_64/pthread_cond_wait.S
(__condvar_cleanup1): Likewise.
Add PTHREAD_UNWIND to replace JUMPTARGET(__pthread_unwind) and define
it to __GI___pthread_unwind within libpthread.
* sysdeps/unix/sysv/linux/x86_64/cancellation.S (PTHREAD_UNWIND):
New
(__pthread_unwind): Renamed to ...
(PTHREAD_UNWIND): This.
(__pthread_enable_asynccancel): Replace
JUMPTARGET(__pthread_unwind) with PTHREAD_UNWIND.
This patch adds CLONE_NEWCGROUP, new in Linux 4.6, to
sysdeps/unix/sysv/linux/bits/sched.h.
Tested for x86_64 and x86 (testsuite, and that installed stripped
shared libraries are unchanged by the patch).
* sysdeps/unix/sysv/linux/bits/sched.h [__USE_GNU]
(CLONE_NEWCGROUP): New macro.
This patch adds Q_GETNEXTQUOTA, new in Linux 4.6, to
sysdeps/unix/sysv/linux/sys/quota.h.
Tested for x86_64 and x86 (testsuite, and that installed shared
libraries are unchanged by the patch).
* sysdeps/unix/sysv/linux/sys/quota.h [_LINUX_QUOTA_VERSION >= 2]
(Q_GETNEXTQUOTA): New macro.
In static executable, since init_cpu_features is called early from
__libc_start_main, there is no need to call it again in dl_platform_init.
[BZ #20072]
* sysdeps/i386/dl-machine.h (dl_platform_init): Call
init_cpu_features only if SHARED is defined.
* sysdeps/x86_64/dl-machine.h (dl_platform_init): Likewise.
small sets of up to 16 bytes, medium of 16..96 bytes which are fully unrolled.
Large memsets of more than 96 bytes align the destination and use an unrolled
loop processing 64 bytes per iteration. Memsets of zero of more than 256 use
the dc zva instruction, and there are faster versions for the common ZVA sizes
64 or 128. STP of Q registers is used to reduce codesize without loss of
performance.
The speedup on test-memset is 1% on Cortex-A57 and 8% on Cortex-A53.
* sysdeps/aarch64/memset.S (__memset):
Rewrite of optimized memset.
This provides a band-aid and addresses the scenario where fork is
called from a signal handler while the process is in the malloc
subsystem (or has acquired the libio list lock). It does not
address the general issue of async-signal-safety of fork;
multi-threaded processes are not covered, and some glibc
subsystems have fork handlers which are not async-signal-safe.
if glibc is build with -march=z900 | -march=z990,
the startup file gcrt1.o (used if you link with gcc -pg)
contains R_390_GOT12 | R_390_GOT20 relocations.
Thus, an entry in the GOT can be addressed relative to the GOT pointer
with a 12 | 20 bit displacement value.
The startup files should not contain R_390_GOT12,
R_390_GOT20 relocations, but R_390_GOTENT ones.
This patch removes the overrides of pic-ccflag and
the default pic-ccflag = -fPIC in Makeconfig
is used instead to get the R_390_GOTENT relocations in gcrt1.o.
ChangeLog:
* sysdeps/s390/s390-32/Makefile (pic-ccflag): Remove.
* sysdeps/s390/s390-64/Makefile: Likewise.
Merge x86 ifunc-defines.sym with x86 cpu-features-offsets.sym. Remove
x86 ifunc-defines.sym and rtld-global-offsets.sym. No code changes on
i686 and x86-64.
* sysdeps/i386/i686/multiarch/Makefile (gen-as-const-headers):
Remove ifunc-defines.sym.
* sysdeps/x86_64/multiarch/Makefile (gen-as-const-headers):
Likewise.
* sysdeps/i386/i686/multiarch/ifunc-defines.sym: Removed.
* sysdeps/x86/rtld-global-offsets.sym: Likewise.
* sysdeps/x86_64/multiarch/ifunc-defines.sym: Likewise.
* sysdeps/x86/Makefile (gen-as-const-headers): Remove
rtld-global-offsets.sym.
* sysdeps/x86_64/multiarch/ifunc-defines.sym: Merged with ...
* sysdeps/x86/cpu-features-offsets.sym: This.
* sysdeps/x86/cpu-features.h: Include <cpu-features-offsets.h>
instead of <ifunc-defines.h> and <rtld-global-offsets.h>.
This patch adds support for symbol __kernel_getcpu in vDSO,
which is available with kernel 4.5.
Now sched_getcpu is using this symbol if available in mapped vDSO
by defining macro HAVE_GETCPU_VSYSCALL. If not available at runtime,
the former syscall is used.
Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86. No code changes on x86
and x86_64.
* sysdeps/i386/cacheinfo.c: Include <sysdeps/x86/cacheinfo.c>
instead of <sysdeps/x86_64/cacheinfo.c>.
* sysdeps/x86_64/cacheinfo.c: Moved to ...
* sysdeps/x86/cacheinfo.c: Here.
* sysdeps/pthread/aio_misc.c (__aio_enqueue_request): Do not write
`running` field of `newp` when a thread was started to process it,
since that thread will not take `__aio_requests_mutex`, and the field
already has the proper value actually.
The file sysdeps/powerpc/sysdeps.h defines aliases for condition register
operands. E.g.: 'cr7' means condition register 7. On the one hand, this
increases readability, as it makes it easier for readers to know whether the
operand is a condition register, a general purpose register or an immediate.
On the other hand, this permits that condition registers be written as if they
were general purpose, and vice-versa, thus reducing the readability of the
code.
This commit removes some of these unintentional misuses.
The changes have no effect on the final code. Checked with objdump.
Instead, we store the data we need from the return value of
readdir in an object of the new type struct readdir_result.
This type is independent of the layout of struct dirent.
This patch fixes the clone CLONE_VM change from 0cb313f (BZ#19957)
where the commit changed the register that contains the save flags
argument to compare with (from r28 to r29). This patch changes
back to correct register.
Tested on powerpc32 (thanks to Tulio Magno Quites Machado Filho).
* sysdeps/unix/sysv/linux/powerpc/powerpc32/clone.S (__clone): Fix
flags CLONE_VM compare.
As discussed in libc-alpha [1] current clone with CLONE_VM (without
CLONE_THREAD set) will reset the pthread pid/tid fields to -1. The
issue is since memory is shared between the parent and child it will
clobber parent's cached pid/tid leading to internal inconsistencies
if the value is not restored.
And even it is restored it may lead to racy conditions when between
set/restore a thread might invoke pthread function that validate the
pthread with INVALID_TD_P/INVALID_NOT_TERMINATED_TD_P and thus get
wrong results.
As stated in BZ19957, previously reports of this behaviour was close
with EWONTFIX due the fact usage of clone outside glibc is tricky
since glibc requires consistent internal pthread, while using clone
directly may not provide it. However since now posix_spawn uses
clone (CLONE_VM) to fixes various issues related to previous vfork
usage this issue requires fixing.
The vfork implementation also does something similar, but instead
it negates and restores only the *pid* field and functions that
might access its value know to handle such case (getpid, raise
and pthread ones that uses INVALID_TD_P/INVALID_NOT_TERMINATED_TD_P
macros that check only *tid* field). Also vfork does not call
__clone directly, instead calling either __NR_vfork or __NR_clone
directly.
So this patch removes this clone behavior by avoiding setting
the pthread pid/tid field for CLONE_VM. There is no need to
check for CLONE_THREAD, since the minimum supported kernel in all
architecture implies that CLONE_VM must be used with CLONE_THREAD,
otherwise clone returns EINVAL.
Instead of current approach of:
int clone(int (*fn)(void *), void *child_stack, int flags, ...)
[...]
if (flags & CLONE_THREAD)
goto do_syscall;
pid_t new_value;
if (flags & CLONE_VM)
new_value = -1;
else
new_value = getpid ();
THREAD_SETMEM (THREAD_SELF, pid, new_value);
THREAD_SETMEM (THREAD_SELF, tid, new_value);
do_syscall:
[...]
The new approach uses:
int clone(int (*fn)(void *), void *child_stack, int flags, ...)
[...]
if (flags & CLONE_VM)
goto do_syscall;
pid_t new_value = getpid ();
THREAD_SETMEM (THREAD_SELF, pid, new_value);
THREAD_SETMEM (THREAD_SELF, tid, new_value);
do_syscall:
[...]
It also removes the linux tst-getpid2.c test which expects the previous
behavior and instead add another clone test.
Tested on x86_64, i686, x32, powerpc64le, aarch64, armhf, s390, and
s390x. I also did limited check on mips32 and sparc64 (using the new
added test).
I also got reviews from both m68k, hppa, and tile. So I presume for
these architecture the patch works.
The fixes for alpha, microblaze, sh, ia64, and nio2 have not been
tested.
[1] https://sourceware.org/ml/libc-alpha/2016-04/msg00307.html
* sysdeps/unix/sysv/linux/Makefile [$(subdir) == nptl] (test): Remove
tst-getpid2.
(test): Add tst-clone2.
* sysdeps/unix/sysv/linux/tst-clone2.c: New file.
* sysdeps/unix/sysv/linux/aarch64/clone.S (__clone): Do not change
pid/tid fields for CLONE_VM.
* sysdeps/unix/sysv/linux/arm/clone.S: Likewise.
* sysdeps/unix/sysv/linux/i386/clone.S: Likewise.
* sysdeps/unix/sysv/linux/mips/clone.S: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/clone.S: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/clone.S: Likewise.
* sysdeps/unix/sysv/linux/s390/s390-32/clone.S: Likewise.
* sysdeps/unix/sysv/linux/s390/s390-64/clone.S: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc32/clone.S: Likewise.
* sysdeps/unix/sysv/linux/sparc/sparc64/clone.S: Likewise.
* sysdeps/unix/sysv/linux/x86_64/clone.S: Likewise.
* sysdeps/unix/sysv/linux/tst-getpid2.c: Remove file.
Call __memset_power8 to pad, with zeros, the remaining bytes in the
dest string on __strncpy_power8 and __stpncpy_power8. This improves
performance when n is larger than the input string, giving ~30% gain for
larger strings without impacting much shorter strings.
When converting a struct hostent response to struct gaih_addrtuple, the
gethosts macro (which is called from gaih_inet) used alloca, without
malloc fallback for large responses. This commit changes this code to
use calloc unconditionally.
This commit also consolidated a second hostent-to-gaih_addrtuple
conversion loop (in gaih_inet) to use the new conversion function.
this patch adds the missing SOL_IUCV socket level definition
and socket options SO_IPRMDATA_MSG, SO_MSGLIMIT, SO_MSGSIZE
which can be used with get/setsockopt().
SCM_IUCV_TRGCLS is needed to send/receive ancillary data with send/recvmsg().
The defines are copied from kernel-source:
include/net/iucv/af_iucv.h
include/linux/socket.h
This patch optimizes strcasestr function for power >= 8 systems. The average
improvement of this optimization is ~40% and compares 16 bytes at a time
using vector instructions. This patch is tested on powerpc64 and powerpc64le.
Updated from the model numbers of Goldmont and Airmont processors in
Intel64 And IA-32 Processor Architectures Software Developer's Manual
Volume 3 Revision 058.
* sysdeps/x86/cpu-features.c (init_cpu_features): Detect Intel
Goldmont and Airmont processors.
This patch fixes the __ALIGNMENT_{ARG,COUNT} definition for ports that
define __ASSUME_ALIGNED_REGISTER_PAIRS by including the kernel-features.h
(where it is defined if the case).
This was shown on arm with failing cases:
FAIL: debug/tst-chk1
FAIL: debug/tst-chk2
FAIL: debug/tst-chk3
FAIL: debug/tst-chk4
FAIL: debug/tst-chk5
FAIL: debug/tst-chk6
FAIL: debug/tst-lfschk1
FAIL: debug/tst-lfschk2
FAIL: debug/tst-lfschk3
FAIL: debug/tst-lfschk4
FAIL: debug/tst-lfschk5
FAIL: debug/tst-lfschk6
FAIL: posix/tst-preadwrite
FAIL: posix/tst-preadwrite64
The patches fixes it. Tested on armhf.
* sysdeps/unix/sysv/linux/sysdep.h: Include kernel-features.h.
Previously, a thread M invoking fork would acquire locks in this order:
(M1) malloc arena locks (in the registered fork handler)
(M2) libio list lock
A thread F invoking flush (NULL) would acquire locks in this order:
(F1) libio list lock
(F2) individual _IO_FILE locks
A thread G running getdelim would use this order:
(G1) _IO_FILE lock
(G2) malloc arena lock
After executing (M1), (F1), (G1), none of the threads can make progress.
This commit changes the fork lock order to:
(M'1) libio list lock
(M'2) malloc arena locks
It explicitly encodes the lock order in the implementations of fork,
and does not rely on the registration order, thus avoiding the deadlock.
The overloading approach in the W* macros was incompatible with
integer expressions of a type different from int. Applications
using union wait and these macros will have to migrate to the
POSIX-specified int status type.
The large memcpy micro benchmark in glibc shows that there is a
regression with large data on Haswell machine. non-temporal store in
memcpy on large data can improve performance significantly. This
patch adds a threshold to use non temporal store which is 6 times of
shared cache size. When size is above the threshold, non temporal
store will be used, but avoid non-temporal store if there is overlap
between destination and source since destination may be in cache when
source is loaded.
For size below 8 vector register width, we load all data into registers
and store them together. Only forward and backward loops, which move 4
vector registers at a time, are used to support overlapping addresses.
For forward loop, we load the last 4 vector register width of data and
the first vector register width of data into vector registers before the
loop and store them after the loop. For backward loop, we load the first
4 vector register width of data and the last vector register width of
data into vector registers before the loop and store them after the loop.
[BZ #19928]
* sysdeps/x86_64/cacheinfo.c (__x86_shared_non_temporal_threshold):
New.
(init_cacheinfo): Set __x86_shared_non_temporal_threshold to 6
times of shared cache size.
* sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S
(VMOVNT): New.
* sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S
(VMOVNT): Likewise.
* sysdeps/x86_64/multiarch/memmove-sse2-unaligned-erms.S
(VMOVNT): Likewise.
(VMOVU): Changed to movups for smaller code sizes.
(VMOVA): Changed to movaps for smaller code sizes.
* sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S: Update
comments.
(PREFETCH): New.
(PREFETCH_SIZE): Likewise.
(PREFETCHED_LOAD_SIZE): Likewise.
(PREFETCH_ONE_SET): Likewise.
Rewrite to use forward and backward loops, which move 4 vector
registers at a time, to support overlapping addresses and use
non temporal store if size is above the threshold and there is
no overlap between destination and source.
This patch adds support for using the implementations of gettimeofday()
and clock_gettime() provided by the kernel in the VDSO. The VDSO will
always provide clock_gettime() as CLOCK_{REALTIME,MONOTONIC}_COARSE can
be implemented regardless of platform. CLOCK_{REALTIME,MONOTONIC}, along
with gettimeofday(), are only implemented on platforms which make use of
either the CP0 count or GIC as their clocksource. On other platforms,
the VDSO does not provide the __vdso_gettimeofday symbol, as it is
never useful.
The VDSO functions return ENOSYS when they encounter an unsupported
request, in which case glibc should fall back to the standard syscall.
Tested with upstream kernel 4.5 and QEMU emulating Malta.
./vdsotest gettimeofday bench
gettimeofday: syscall: 1021 nsec/call
gettimeofday: libc: 262 nsec/call
gettimeofday: vdso: 174 nsec/call
* sysdeps/unix/sysv/linux/mips/Makefile (sysdep_routines):
Include dl-vdso.
* sysdeps/unix/sysv/linux/mips/Versions: Add
__vdso_clock_gettime.
* sysdeps/unix/sysv/linux/mips/init-first.c: New file.
* sysdeps/unix/sysv/linux/mips/libc-vdso.h: New file.
* sysdeps/unix/sysv/linux/mips/mips32/sysdep.h:
(INTERNAL_VSYSCALL_CALL): Define to be compatible with MIPS
definitions of INTERNAL_SYSCALL_{ERROR_P,ERRNO}.
(HAVE_CLOCK_GETTIME_VSYSCALL): Define.
(HAVE_GETTIMEOFDAY_VSYSCALL): Define.
* sysdeps/unix/sysv/linux/mips/mips64/n32/sysdep.h: Likewise.
* sysdeps/unix/sysv/linux/mips/mips64/n64/sysdep.h: Likewise.
This patch consolidates all the pwrite/pwrite64 implementation for Linux
in only one (sysdeps/unix/sysv/linux/pwrite{64}.c). It also removes the
syscall from the auto-generation using assembly macros.
For pwrite{64} offset argument placement the new SYSCALL_LL{64} macro
is used. For pwrite ports that do not define __NR_pwrite will use
__NR_pwrite64 and for pwrite64 ports that dot define __NR_pwrite64 will
use __NR_pwrite for the syscall.
Checked on x86_64, x32, i386, aarch64, and ppc64le.
* sysdeps/unix/sysv/linux/arm/pwrite.c: Remove file.
* sysdeps/unix/sysv/linux/arm/pwrite64.c: Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pwrite.c: Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pwrite64.c: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/pwrite.c: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/pwrite64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/pwrite64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/syscalls.list (prite): Remove
syscalls generation.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/sysdep.h
[__NR_pwrite64] (__NR_write): Remove define.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/sysdep.h
[__NR_pwrite64] (__NR_write): Remove define.
* sysdeps/unix/sysv/linux/pwrite.c [__NR_pwrite64] (__NR_pwrite):
Remove define.
(__libc_pwrite): Use SYSCALL_LL macro on offset argument.
* sysdeps/unix/sysv/linux/pwrite64.c [__NR_pwrite64] (__NR_pwrite):
Remove define.
(__libc_pwrite64): Use SYSCALL_LL64 macro on offset argument.
* sysdeps/unix/sysv/linux/sh/pwrite.c: Rewrite using default
Linux implementation as base.
* sysdeps/unix/sysv/linux/sh/pwrite64.c: Likewise.
* sysdeps/unix/sysv/linux/mips/pwrite.c: Likewise.
* sysdeps/unix/sysv/linux/mips/pwrite64.c: Likewise.
This patch consolidates all the pread/pread64 implementation for Linux
in only one (sysdeps/unix/sysv/linux/pread.c). It also removes the
syscall from the auto-generation using assembly macros.
For pread{64} offset argument placement the new SYSCALL_LL{64} macro
is used. For pread ports that do not define __NR_pread will use
__NR_pread64 and for pread64 ports that dot define __NR_pread64 will
use __NR_pread for the syscall.
Checked on x86_64, x32, i386, aarch64, and ppc64le.
* sysdeps/unix/sysv/linux/arm/pread.c: Remove file.
* sysdeps/unix/sysv/linux/arm/pread64.c: Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pread.c: Likewise.
* sysdeps/unix/sysv/linux/generic/wordsize-32/pread64.c: Likewise.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/pread.c: Likewise,
* sysdeps/unix/sysv/linux/powerpc/powerpc32/pread64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/pread64.c: Likewise.
* sysdeps/unix/sysv/linux/wordsize-64/syscalls.list (pread): Remove
syscall generation.
* sysdeps/unix/sysv/linux/powerpc/powerpc32/sysdep.h
[__NR_pread64] (__NR_pread): Remove define.
* sysdeps/unix/sysv/linux/powerpc/powerpc64/sysdep.h:
[__NR_pread64] (__NR_pread): Likewise.
* sysdeps/unix/sysv/linux/pread.c [__NR_pread64] (__NR_pread): Remove
define.
(__libc_pread): Use SYSCALL_LL macro on offset argument.
* sysdeps/unix/sysv/linux/pread64.c [__NR_pread64] (__NR_pread):
Remove define.
(__libc_pread64): Use SYSCALL_LL64 macro on offset argument.
* sysdeps/unix/sysv/linux/sh/pread.c: Rewrite using default
Linux implementation as base.
* sysdeps/unix/sysv/linux/sh/pread64.c: Likewise.
* sysdeps/unix/sysv/linux/mips/pread.c: Likewise.
* sysdeps/unix/sysv/linux/mips/pread64.c: Likewise.
This patch add three new macros (SYSCALL_LL, SYSCALL_LL64, and
__ASSUME_WORDSIZE64_ILP32) to use along with off_t and off64_t argument
syscalls. The rationale for this change is:
1. Remove multiple implementations for the same syscall for different
architectures (for instance, pread have 6 different implementations).
2. Also remove the requirement to use syscall wrappers for cancellable
entrypoints.
The macro usage should be used along __ALIGNMENT_ARG to follow ABI constrains
for architecture where it applies. For instance, pread can be rewritten as:
return SYSCALL_CANCEL (pread, fd, buf, count,
__ALIGNMENT_ARG SYSCALL_LL (offset));
Another macro, SYSCALL_LL64, is provided for off64_t. The macro
__ASSUME_WORDSIZE64_ILP32 is used by the ABI to define is uses 64-bit register
even if ABI is ILP32 (for instance x32 and mips64-n32).
The changes itself are not currently used in any implementation, so no
code change is expected.
* sysdeps/unix/sysv/linux/generic/sysdep.h (__ALIGNMENT_ARG): Move
definition.
(__ALIGNMENT_COUNT): Likewise.
* sysdeps/unix/sysv/linux/sysdep.h (__ALIGNMENT_ARG): To here.
(__ALIGNMENT_COUNT): Likewise.
(SYSCALL_LL): New define.
(SYSCALL_LL64): Likewise.
* sysdeps/unix/sysv/linux/mips/kernel-features.h:
[_MIPS_SIM == _ABIO32] (__ASSUME_WORDSIZE64_ILP32): Define.
* sysdeps/unix/sysv/linux/x86_64/kernel-features.h:
[ILP32] (__ASUME_WORDSIZE64_ILP32): Likewise.
This patch defines __ASSUME_ALIGNED_REGISTER_PAIRS for the missing
ports that require 64-bit value (e.g., long long) to be aligned to
an even register pair in argument passing.
No code change is expected, tested with builds for powerpc32,
mips-o32, and armhf.
* sysdeps/unix/sysv/linux/arm/kernel-features.h
(__ASSUME_ALIGNED_REGISTER_PAIRS): Define.
* sysdeps/unix/sysv/linux/mips/kernel-features.h
[_MIPS_SIM == _ABIO32] (__ASSUME_ALIGNED_REGISTER_PAIRS): Likewise.
* sysdeps/unix/sysv/linux/powerpc/kernel-features.h
[!__powerpc64__] (__ASSUME_ALIGNED_REGISTER_PAIRS): Likewise.
* sysdeps/generic/ldsodefs.h (struct rtld_global_ro)
[!HAVE_AUX_VECTOR]: Do not define _dl_auxv field.
* misc/getauxval.c (__getauxval) [!HAVE_AUX_VECTOR]: Do not go through
GLRO(dl_auxv) list.
This fixes errors when we inject sse options through CFLAGS and now
that we have -Werror turned on by default this warning turns into an
error on x86:
$ gcc -m32 -march=core2 -mtune=core2 -msse3 -mfpmath=sse -x c /dev/null -S -mno-sse -mno-mmx
/dev/null:1:0: warning: SSE instruction set disabled, using 387 arithmetics
Where as:
$ gcc -m32 -march=core2 -mtune=core2 -msse3 -mfpmath=sse -x c /dev/null -S -mno-sse -mno-mmx -mfpmath=387
Generates no warnings.
bits/termios.h (various versions under sysdeps/unix/sysv/linux)
defines XCASE if defined __USE_MISC || defined __USE_XOPEN. This
macro was removed in the 2001 edition of POSIX, and is not otherwise
reserved, so should not be defined for 2001 and later versions of
POSIX. This patch fixes the conditions accordingly (leaving the macro
defined for __USE_MISC, so still in the default namespace).
Tested for x86_64 and x86 (testsuite, and that installed shared
libraries are unchanged by the patch).
[BZ #19925]
* sysdeps/unix/sysv/linux/alpha/bits/termios.h (XCASE): Do not
define if [!__USE_MISC && __USE_XOPEN2K].
* sysdeps/unix/sysv/linux/bits/termios.h (XCASE): Likewise.
* sysdeps/unix/sysv/linux/mips/bits/termios.h (XCASE): Likewise.
* sysdeps/unix/sysv/linux/powerpc/bits/termios.h (XCASE):
Likewise.
* sysdeps/unix/sysv/linux/sparc/bits/termios.h (XCASE): Likewise.
* conform/Makefile (test-xfail-XOPEN2K/termios.h/conform): Remove
variable.
(test-xfail-XOPEN2K8/termios.h/conform): Likewise.
This utilizes vectors and bitmasks. For small needle, large
haystack, the performance improvement is upto 8x. For short
strings (0-4B), the cost of computing the bitmask dominates,
and is a tad slower.
Prepare memmove-vec-unaligned-erms.S to make the SSE2 version as the
default memcpy, mempcpy and memmove.
* sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S
(MEMCPY_SYMBOL): New.
(MEMPCPY_SYMBOL): Likewise.
(MEMMOVE_CHK_SYMBOL): Likewise.
Replace MEMMOVE_SYMBOL with MEMMOVE_CHK_SYMBOL on __mempcpy_chk
symbols. Replace MEMMOVE_SYMBOL with MEMPCPY_SYMBOL on
__mempcpy symbols. Provide alias for __memcpy_chk in libc.a.
Provide alias for memcpy in libc.a and ld.so.
Prepare memset-vec-unaligned-erms.S to make the SSE2 version as the
default memset.
* sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
(MEMSET_CHK_SYMBOL): New. Define if not defined.
(__bzero): Check VEC_SIZE == 16 instead of USE_MULTIARCH.
Disabled fro now.
Replace MEMSET_SYMBOL with MEMSET_CHK_SYMBOL on __memset_chk
symbols. Properly check USE_MULTIARCH on __memset symbols.
Since memmove and memset in ld.so don't use IFUNC, don't put SSE2, AVX
and AVX512 memmove and memset in ld.so.
* sysdeps/x86_64/multiarch/memmove-avx-unaligned-erms.S: Skip
if not in libc.
* sysdeps/x86_64/multiarch/memmove-avx512-unaligned-erms.S:
Likewise.
* sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S:
Likewise.
* sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S:
Likewise.
__mempcpy_erms and __memmove_erms can't be placed between __memmove_chk
and __memmove it breaks __memmove_chk.
Don't check source == destination first since it is less common.
* sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S:
(__mempcpy_erms, __memmove_erms): Moved before __mempcpy_chk
with unaligned_erms.
(__memmove_erms): Skip if source == destination.
(__memmove_unaligned_erms): Don't check source == destination
first.
Zack Weinberg
Paul E. Murphy
Florian Weimer
Joseph Myers
Aurelien Jarno
David S. Miller
Andrew Senkevich
H.J. Lu
Chung-Lin Tang
Gustavo Romero
Szabolcs Nagy
Stefan Liebler
Mike Frysinger
Siddhesh Poyarekar
Adhemerval Zanella
Chris Metcalf
John David Anglin
Rajalakshmi Srinivasaraghavan
Andreas Schwab
Maciej W. Rozycki
Anton Blanchard
Tulio Magno Quites Machado Filho
Andreas Schwab
Torvald Riegel
Wilco Dijkstra
Carlos O'Donell
raji
Samuel Thibault
Gabriel F. T. Gomes
Carlos Eduardo Seo
Matthew Fortune
Adhemerval Zanella
Khem Raj