2021-07-14 00:44:10 +02:00
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#ifndef __ASM_L_EPIC_REGS_H
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#define __ASM_L_EPIC_REGS_H
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#include <asm/types.h>
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#ifndef __ASSEMBLY__
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#ifdef __LITTLE_ENDIAN
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union cepic_ctrl {
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u32 raw;
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struct {
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u32 __reserved1 : 8,
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bsp_core : 1,
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__reserved2 : 1,
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soft_en : 1,
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__reserved3 : 21;
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} __packed bits;
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};
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/* Ignore 4 bits of CEPIC (core) ID so that physical core ID is <= 64 */
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union cepic_id {
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u32 raw;
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struct {
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u32 cepicn : 4,
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cepicn_reserved : 4,
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prepicn : 2,
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__reserved2 : 22;
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} __packed bits;
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};
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union cepic_ctrl2 {
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u32 raw;
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struct {
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u32 mi_gst_blk : 1,
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nmi_gst_blk : 1,
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int_hv : 1,
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__reserved1 : 1,
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clear_gst : 1,
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__reserved2 : 3,
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timer_stop : 1,
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__reserved3 : 23;
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} __packed bits;
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};
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union cepic_dat {
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u64 raw;
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struct {
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u64 __reserved1 : 6,
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dat_cop : 2,
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__reserved2 : 4,
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stat : 1,
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__reserved3 : 7,
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index : 10,
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__reserved4 : 2,
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__reserved5 : 8,
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gst_dst : 10,
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__reserved6 : 2,
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gst_id : 12;
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} __packed bits;
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};
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union cepic_epic_int {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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__reserved2 : 3,
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mask : 1,
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__reserved3 : 15;
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} __packed bits;
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};
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union cepic_epic_int2 {
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u64 raw;
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struct {
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u64 vect : 10,
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dst_sh : 2,
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__reserved1 : 1,
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dlvm : 3,
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__reserved2 : 4,
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gst_id : 12,
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2021-08-26 00:47:50 +02:00
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__reserved3 : 8,
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2021-07-14 00:44:10 +02:00
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gst_dst : 10,
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2021-08-26 00:47:50 +02:00
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__reserved4 : 14;
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2021-07-14 00:44:10 +02:00
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} __packed bits;
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};
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union cepic_cpr {
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u32 raw;
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struct {
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u32 __reserved1 : 8,
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cpr : 3,
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__reserved2 : 21;
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} __packed bits;
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};
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union cepic_esr {
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u32 raw;
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struct {
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u32 __reserved1 : 5,
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rq_addr_err : 1,
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rq_virt_err : 1,
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rq_cop_err : 1,
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ms_gstid_err : 1,
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ms_virt_err : 1,
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ms_err : 1,
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ms_icr_err : 1,
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__reserved2 : 20;
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} __packed bits;
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};
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union cepic_esr2 {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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__reserved2 : 3,
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mask : 1,
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__reserved3 : 15;
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} __packed bits;
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};
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union cepic_eoi {
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u32 raw;
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struct {
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u32 __reserved1 : 16,
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rcpr : 3,
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__reserved2 : 13;
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} __packed bits;
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};
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union cepic_cir {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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__reserved2 : 19;
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} __packed bits;
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};
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union cepic_gstbase_hi {
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u32 raw;
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struct {
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u32 gstbase_hi : 4,
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__reserved : 28;
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} __packed bits;
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};
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union cepic_gstid {
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u32 raw;
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struct {
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u32 gstid : 12,
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__reserved : 20;
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} __packed bits;
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};
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union cepic_pnmirr {
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u32 raw;
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struct {
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u32 startup_entry : 8,
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__reserved1 : 1,
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smi : 1,
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nmi : 1,
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init : 1,
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startup : 1,
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int_violat : 1,
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__reserved2 : 2,
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nm_timer : 1,
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nm_special : 1,
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__reserved3 : 14;
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} __packed bits;
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};
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union cepic_icr {
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u64 raw;
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struct {
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u64 vect : 10,
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dst_sh : 2,
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stat : 1,
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dlvm : 3,
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__reserved1 : 4,
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gst_id : 12,
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__reserved2 : 8,
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dst : 10,
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__reserved3 : 14;
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} __packed bits;
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};
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union cepic_timer_lvtt {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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__reserved2 : 3,
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mask : 1,
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mode : 1,
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__reserved3 : 14;
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} __packed bits;
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};
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union cepic_timer_div {
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u32 raw;
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struct {
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u32 divider : 4,
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__reserved1 : 28;
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} __packed bits;
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};
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union cepic_nm_timer_lvtt {
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u32 raw;
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struct {
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u32 __reserved1 : 17,
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mode : 1,
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__reserved2 : 14;
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} __packed bits;
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};
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union cepic_nm_timer_div {
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u32 raw;
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struct {
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u32 divider : 4,
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__reserved1 : 28;
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} __packed bits;
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};
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union cepic_svr {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 22;
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} __packed bits;
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};
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union cepic_pnmirr_mask {
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u32 raw;
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struct {
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u32 __reserved1 : 9,
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smi : 1,
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nmi : 1,
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__reserved2 : 2,
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int_violat : 1,
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__reserved3 : 2,
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nm_timer : 1,
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nm_special : 1,
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__reserved4 : 14;
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} __packed bits;
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};
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union cepic_vect_inta {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 6,
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cpr : 3,
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__reserved2 : 13;
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} __packed bits;
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};
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union prepic_ctrl {
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u32 raw;
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struct {
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u32 __reserved1 : 8,
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bsp : 1,
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__reserved2 : 2,
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epic_en : 1,
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__reserved3 : 20;
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} __packed bits;
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};
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union prepic_id {
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u32 raw;
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struct {
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u32 __reserved1 : 8,
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prepicn : 2,
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__reserved2 : 22;
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} __packed bits;
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};
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union prepic_ctrl2 {
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u32 raw;
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struct {
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u32 __reserved1 : 9,
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bgi_mode : 1,
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__reserved2 : 2,
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virt_en : 1,
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__reserved3 : 19;
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} __packed bits;
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};
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union prepic_err_int {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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dlvm : 3,
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mask : 1,
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__reserved2 : 3,
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dst : 10,
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__reserved3 : 2;
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} __packed bits;
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};
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union prepic_linpn {
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u32 raw;
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struct {
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u32 vect : 10,
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__reserved1 : 2,
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stat : 1,
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dlvm : 3,
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mask : 1,
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__reserved2 : 3,
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dst : 10,
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__reserved3 : 2;
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} __packed bits;
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};
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typedef struct kvm_epic_page {
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/*000*/ u32 ctrl;
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u32 id;
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u32 cpr;
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u32 esr;
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2021-08-26 00:47:50 +02:00
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union cepic_esr2 esr2;
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union cepic_cir cir;
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2021-07-14 00:44:10 +02:00
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atomic_t esr_new;
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u32 svr;
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2021-08-26 00:47:50 +02:00
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union cepic_icr icr;
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union cepic_timer_lvtt timer_lvtt;
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2021-07-14 00:44:10 +02:00
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u32 timer_init;
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u32 timer_cur;
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u32 timer_div;
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u32 nm_timer_lvtt;
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u32 nm_timer_init;
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u32 nm_timer_cur;
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u32 nm_timer_div;
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u32 pnmirr_mask;
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/*04c*/ u32 __reserved1[45];
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/*100*/ atomic64_t pmirr[CEPIC_PMIRR_NR_DREGS];
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2021-07-14 00:44:10 +02:00
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/*180*/ u32 __reserved2[24];
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/*1e0*/ atomic_t pnmirr;
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u32 __reserved3[263];
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/*600*/ u8 pnmirr_byte[16];
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/*610*/ u32 __reserved4[124];
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2021-08-26 00:47:50 +02:00
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/*800*/ u8 pmirr_byte[CEPIC_PMIRR_NR_BITS];
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2021-07-14 00:44:10 +02:00
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} epic_page_t;
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#elif defined(__BIG_ENDIAN)
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union cepic_ctrl {
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u32 raw;
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struct {
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u32 __reserved3 : 21,
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soft_en : 1,
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__reserved2 : 1,
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bsp_core : 1,
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__reserved1 : 8;
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} __packed bits;
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};
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/* Ignore 4 bits of CEPIC (core) ID so that physical core ID is <= 64 */
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union cepic_id {
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u32 raw;
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struct {
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u32 __reserved2 : 22,
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prepicn : 2,
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cepicn_reserved : 4,
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cepicn : 4;
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} __packed bits;
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};
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union cepic_ctrl2 {
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u32 raw;
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struct {
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u32 __reserved3 : 23,
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timer_stop : 1,
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__reserved2 : 3,
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clear_gst : 1,
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__reserved1 : 1,
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int_hv : 1,
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nmi_gst_blk : 1,
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mi_gst_blk : 1;
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} __packed bits;
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};
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union cepic_dat {
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u64 raw;
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struct {
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u64 gst_id : 12,
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__reserved6 : 2,
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gst_dst : 10,
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__reserved5 : 8,
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__reserved4 : 2,
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index : 10,
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__reserved3 : 7,
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stat : 1,
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__reserved2 : 4,
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dat_cop : 2,
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__reserved1 : 6;
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} __packed bits;
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};
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union cepic_epic_int {
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u32 raw;
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struct {
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u32 __reserved3 : 15,
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mask : 1,
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__reserved2 : 3,
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stat : 1,
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__reserved1 : 2,
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vect : 10;
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} __packed bits;
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};
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union cepic_epic_int2 {
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|
|
u64 raw;
|
|
|
|
struct {
|
2021-08-26 00:47:50 +02:00
|
|
|
u64 __reserved4 : 14,
|
2021-07-14 00:44:10 +02:00
|
|
|
gst_dst : 10,
|
2021-08-26 00:47:50 +02:00
|
|
|
__reserved3 : 8,
|
2021-07-14 00:44:10 +02:00
|
|
|
gst_id : 12,
|
|
|
|
__reserved2 : 4,
|
|
|
|
dlvm : 3,
|
|
|
|
__reserved1 : 1,
|
|
|
|
dst_sh : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_cpr {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 21,
|
|
|
|
cpr : 3,
|
|
|
|
__reserved1 : 8;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_esr {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 20,
|
|
|
|
ms_icr_err : 1,
|
|
|
|
ms_err : 1,
|
|
|
|
ms_virt_err : 1,
|
|
|
|
ms_gstid_err : 1,
|
|
|
|
rq_cop_err : 1,
|
|
|
|
rq_virt_err : 1,
|
|
|
|
rq_addr_err : 1,
|
|
|
|
__reserved1 : 5;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_esr2 {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 15,
|
|
|
|
mask : 1,
|
|
|
|
__reserved2 : 3,
|
|
|
|
stat : 1,
|
|
|
|
__reserved1 : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_eoi {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 13,
|
|
|
|
rcpr : 3,
|
|
|
|
__reserved1 : 16;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_cir {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 19,
|
|
|
|
stat : 1,
|
|
|
|
__reserved1 : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_gstbase_hi {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved : 28,
|
|
|
|
gstbase_hi : 4;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_gstid {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved : 20,
|
|
|
|
gstid : 12;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_pnmirr {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 14,
|
|
|
|
nm_special : 1,
|
|
|
|
nm_timer : 1,
|
|
|
|
__reserved2 : 2,
|
|
|
|
int_violat : 1,
|
|
|
|
startup : 1,
|
|
|
|
init : 1,
|
|
|
|
nmi : 1,
|
|
|
|
smi : 1,
|
|
|
|
__reserved1 : 1,
|
|
|
|
startup_entry : 8;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_icr {
|
|
|
|
u64 raw;
|
|
|
|
struct {
|
|
|
|
u64 __reserved3 : 14,
|
|
|
|
dst : 10,
|
|
|
|
__reserved2 : 8,
|
|
|
|
gst_id : 12,
|
|
|
|
__reserved1 : 4,
|
|
|
|
dlvm : 3,
|
|
|
|
stat : 1,
|
|
|
|
dst_sh : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_timer_lvtt {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 14,
|
|
|
|
mode : 1,
|
|
|
|
mask : 1,
|
|
|
|
__reserved2 : 3,
|
|
|
|
stat : 1,
|
|
|
|
__reserved1 : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_timer_div {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved1 : 28,
|
|
|
|
divider : 4;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_nm_timer_lvtt {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 14,
|
|
|
|
mode : 1,
|
|
|
|
__reserved1 : 17;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_nm_timer_div {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved1 : 28,
|
|
|
|
divider : 4;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_svr {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved1 : 22,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_pnmirr_mask {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved4 : 14,
|
|
|
|
nm_special : 1,
|
|
|
|
nm_timer : 1,
|
|
|
|
__reserved3 : 2,
|
|
|
|
int_violat : 1,
|
|
|
|
__reserved2 : 2,
|
|
|
|
nmi : 1,
|
|
|
|
smi : 1,
|
|
|
|
__reserved1 : 9;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union cepic_vect_inta {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 13,
|
|
|
|
cpr : 3,
|
|
|
|
__reserved1 : 6,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union prepic_ctrl {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 20,
|
|
|
|
epic_en : 1,
|
|
|
|
__reserved2 : 2,
|
|
|
|
bsp : 1,
|
|
|
|
__reserved1 : 8;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union prepic_id {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved2 : 22,
|
|
|
|
prepicn : 2,
|
|
|
|
__reserved1 : 8;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union prepic_ctrl2 {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 19,
|
|
|
|
virt_en : 1,
|
|
|
|
__reserved2 : 2,
|
|
|
|
bgi_mode : 1,
|
|
|
|
__reserved1 : 9;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union prepic_err_int {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 2,
|
|
|
|
dst : 10,
|
|
|
|
__reserved2 : 3,
|
|
|
|
mask : 1,
|
|
|
|
dlvm : 3,
|
|
|
|
stat : 1,
|
|
|
|
__reserved1 : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
union prepic_linpn {
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
|
|
u32 __reserved3 : 2,
|
|
|
|
dst : 10,
|
|
|
|
__reserved2 : 3,
|
|
|
|
mask : 1,
|
|
|
|
dlvm : 3,
|
|
|
|
stat : 1,
|
|
|
|
__reserved1 : 2,
|
|
|
|
vect : 10;
|
|
|
|
} __packed bits;
|
|
|
|
};
|
|
|
|
|
|
|
|
#else /*__BIG_ENDIAN*/
|
|
|
|
# error FIXME
|
|
|
|
#endif
|
|
|
|
#endif /* !(__ASSEMBLY__) */
|
|
|
|
#endif /* __ASM_L_EPIC_REGS_H */
|