2021-07-14 00:44:10 +02:00
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#ifndef _ASM_E8C_H_
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#define _ASM_E8C_H_
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/*
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* Machine (based on E8C processor) topology:
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* E8C is NUMA system on distributed memory and can have several nodes.
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* Each node can have some memory (faster to access) and max 8 CPUs (cores)
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* Node number is the same as chip-processor number
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* Some nodes (CPUs) can be without memory
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* LAPIC cluster number is the same as node number
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*/
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#ifndef __ASSEMBLY__
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struct pt_regs;
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extern void boot_e8c_setup_arch(void);
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extern void e8c_setup_machine(void);
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extern void sic_error_interrupt(struct pt_regs *regs);
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#endif
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#define E8C_NR_NODE_CPUS 8
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#define E8C_MAX_NR_NODE_CPUS 16
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#define E8C_NODE_IOLINKS 1
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2022-01-17 12:36:48 +01:00
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#define E8C_PCICFG_AREA_PHYS_BASE E2S_PCICFG_AREA_PHYS_BASE
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#define E8C_PCICFG_AREA_SIZE E2S_PCICFG_AREA_SIZE
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2021-07-14 00:44:10 +02:00
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2022-01-17 12:36:48 +01:00
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#define E8C_NSR_AREA_PHYS_BASE E2S_NSR_AREA_PHYS_BASE
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2021-07-14 00:44:10 +02:00
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#define E8C_SIC_MC_SIZE 0xe4
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#define E8C_SIC_MC_COUNT 4
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#define E8C_L3_CACHE_SHIFT 6
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#define E8C_L3_CACHE_BYTES (1 << E8C_L3_CACHE_SHIFT)
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#endif /* _ASM_E8C_H_ */
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