linux-headers-5.4.0-3.13

This commit is contained in:
Alibek Omarov 2022-01-17 14:36:48 +03:00
parent 000d6cbdce
commit 2013552b5f
198 changed files with 4011 additions and 3435 deletions

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@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 4
SUBLEVEL = 143
EXTRAVERSION = -3.9
SUBLEVEL = 154
EXTRAVERSION = -3.13
NAME = Kleptomaniac Octopus
# *DOCUMENTATION*

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@ -44,12 +44,7 @@ CFLAGS += -pipe -D__linux__
KBUILD_CFLAGS += $(CFLAGS)
ifdef CONFIG_SMP_DAM_BUG
KBUILD_CFLAGS += -fno-dam-call
endif
CFLAGS_GENERIC := -march=elbrus-v2
CFLAGS_ES2 := -mtune=elbrus-2c+
CFLAGS_GENERIC := -march=elbrus-v3
CFLAGS_E2S := -mtune=elbrus-4c
CFLAGS_E8C := -mtune=elbrus-8c
CFLAGS_E1CP := -mtune=elbrus-1c+
@ -58,71 +53,56 @@ CFLAGS_E12C := -mtune=elbrus-12c
CFLAGS_E16C := -mtune=elbrus-16c
CFLAGS_E2C3 := -mtune=elbrus-2c3
CFLAGS_ALL_CPUS := $(CFLAGS_ES2) $(CFLAGS_E2S) $(CFLAGS_E8C) $(CFLAGS_E1CP) \
$(CFLAGS_E8C2) $(CFLAGS_E12C) $(CFLAGS_E16C) $(CFLAGS_E2C3)
export CFLAGS_ALL_CPUS
CFLAGS_ALL_CPUS := $(CFLAGS_E2S) $(CFLAGS_E8C) $(CFLAGS_E1CP) $(CFLAGS_E8C2) \
$(CFLAGS_E12C) $(CFLAGS_E16C) $(CFLAGS_E2C3)
CFLAGS_E2K_SIC := $(CFLAGS_ES2)
export CFLAGS_ES2 CFLAGS_E2S CFLAGS_E8C CFLAGS_E1CP CFLAGS_E8C2 CFLAGS_E2C3 \
CFLAGS_E12C CFLAGS_E16C CFLAGS_E2K_SIC
export CFLAGS_E2S CFLAGS_E8C CFLAGS_E1CP CFLAGS_E8C2 CFLAGS_E2C3 CFLAGS_E12C \
CFLAGS_E16C CFLAGS_ALL_CPUS
ifeq ($(CONFIG_E2K_MACHINE),y)
ifeq ($(CONFIG_E2K_ES2_DSP),y)
KBUILD_CFLAGS += $(CFLAGS_ES2)
KBUILD_AFLAGS += $(CFLAGS_ES2)
TARGET_MDL := 04
ifeq ($(CONFIG_E2K_E2S),y)
KBUILD_CFLAGS += $(CFLAGS_E2S)
KBUILD_AFLAGS += $(CFLAGS_E2S)
TARGET_MDL := 03
else
ifeq ($(CONFIG_E2K_ES2_RU),y)
KBUILD_CFLAGS += $(CFLAGS_ES2)
KBUILD_AFLAGS += $(CFLAGS_ES2)
TARGET_MDL := 06
ifeq ($(CONFIG_E2K_E8C),y)
KBUILD_CFLAGS += $(CFLAGS_E8C)
KBUILD_AFLAGS += $(CFLAGS_E8C)
TARGET_MDL := 07
else
ifeq ($(CONFIG_E2K_E2S),y)
KBUILD_CFLAGS += $(CFLAGS_E2S)
KBUILD_AFLAGS += $(CFLAGS_E2S)
TARGET_MDL := 03
ifeq ($(CONFIG_E2K_E1CP),y)
KBUILD_CFLAGS += $(CFLAGS_E1CP)
KBUILD_AFLAGS += $(CFLAGS_E1CP)
TARGET_MDL := 08
else
ifeq ($(CONFIG_E2K_E8C),y)
KBUILD_CFLAGS += $(CFLAGS_E8C)
KBUILD_AFLAGS += $(CFLAGS_E8C)
TARGET_MDL := 07
ifeq ($(CONFIG_E2K_E8C2),y)
KBUILD_CFLAGS += $(CFLAGS_E8C2)
KBUILD_AFLAGS += $(CFLAGS_E8C2)
TARGET_MDL := 09
else
ifeq ($(CONFIG_E2K_E1CP),y)
KBUILD_CFLAGS += $(CFLAGS_E1CP)
KBUILD_AFLAGS += $(CFLAGS_E1CP)
TARGET_MDL := 08
ifeq ($(CONFIG_E2K_E12C),y)
KBUILD_CFLAGS += $(CFLAGS_E12C)
KBUILD_AFLAGS += $(CFLAGS_E12C)
TARGET_MDL := 0a
else
ifeq ($(CONFIG_E2K_E8C2),y)
KBUILD_CFLAGS += $(CFLAGS_E8C2)
KBUILD_AFLAGS += $(CFLAGS_E8C2)
TARGET_MDL := 09
ifeq ($(CONFIG_E2K_E16C),y)
KBUILD_CFLAGS += $(CFLAGS_E16C)
KBUILD_AFLAGS += $(CFLAGS_E16C)
TARGET_MDL := 0b
else
ifeq ($(CONFIG_E2K_E12C),y)
KBUILD_CFLAGS += $(CFLAGS_E12C)
KBUILD_AFLAGS += $(CFLAGS_E12C)
TARGET_MDL := 0a
ifeq ($(CONFIG_E2K_E2C3),y)
KBUILD_CFLAGS += $(CFLAGS_E2C3)
KBUILD_AFLAGS += $(CFLAGS_E2C3)
TARGET_MDL := 0c
else
ifeq ($(CONFIG_E2K_E16C),y)
KBUILD_CFLAGS += $(CFLAGS_E16C)
KBUILD_AFLAGS += $(CFLAGS_E16C)
TARGET_MDL := 0b
else
ifeq ($(CONFIG_E2K_E2C3),y)
KBUILD_CFLAGS += $(CFLAGS_E2C3)
KBUILD_AFLAGS += $(CFLAGS_E2C3)
TARGET_MDL := 0c
else
error "Invalid e2k machine type"
endif # ifeq ($(CONFIG_E2K_E2C3),y)
endif # ifeq ($(CONFIG_E2K_E16C),y)
endif # ifeq ($(CONFIG_E2K_E12C),y)
endif # ifeq ($(CONFIG_E2K_E8C2),y)
endif # ifeq ($(CONFIG_E2K_E1CP),y)
endif # ifeq ($(CONFIG_E2K_E8C),y)
endif # ifeq ($(CONFIG_E2K_E2S),y)
endif # ifeq ($(CONFIG_E2K_ES2_RU),y)
endif # ifeq ($(CONFIG_E2K_ES2_DSP),y)
error "Invalid e2k machine type"
endif # ifeq ($(CONFIG_E2K_E2C3),y)
endif # ifeq ($(CONFIG_E2K_E16C),y)
endif # ifeq ($(CONFIG_E2K_E12C),y)
endif # ifeq ($(CONFIG_E2K_E8C2),y)
endif # ifeq ($(CONFIG_E2K_E1CP),y)
endif # ifeq ($(CONFIG_E2K_E8C),y)
endif # ifeq ($(CONFIG_E2K_E2S),y)
else # ! ifeq ($(CONFIG_E2K_MACHINE),y)
KBUILD_CFLAGS += $(CFLAGS_GENERIC)
KBUILD_AFLAGS += $(CFLAGS_GENERIC)
@ -153,15 +133,12 @@ core-y += arch/l/
drivers-$(CONFIG_PCI) += arch/l/pci/
boot := arch/e2k/boot
all: es2boot
all: e2sboot
MAKEBOOT = $(MAKE) -C arch/$(ARCH)/boot
.PHONY: clean archclean archmrproper archdep bootimage image zImage
es2boot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_ES2=y boot
e2sboot: vmlinux
$(Q)$(MAKE) $(build)=$(boot) CONFIG_E2S=y boot
@ -240,7 +217,6 @@ define archhelp
echo ' zImage - Compressed kernel boot image (image.boot)'
echo ' install-headers - Install kernel headers in '
echo ' <basedir>/usr/include'
echo ' es2boot - Build kernel boot image with small embedded boot for es2 simulator'
echo ' e2sboot - Build kernel boot image with small embedded boot for e2s simulator'
echo ' e8cboot - Build kernel boot image with small embedded boot for e8c simulator'
echo ' e1cpboot - Build kernel boot image with small embedded boot for e1cp simulator'

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@ -267,7 +267,7 @@ extern bootblock_struct_t *bootblock_virt; /* bootblock structure */
#define SIMULATOR_MACH_FLAG 0x0001 /* system is running on */
/* simulator */
#define PROTOTYPE_MACH_FLAG_DEPRECATED 0x0002 /* machine is prototype */
#define IOHUB_MACH_FLAG 0x0004 /* machine has IOHUB */
#define IOHUB_MACH_FLAG_DEPRECATED 0x0004 /* machine has IOHUB */
#define OLDMGA_MACH_FLAG 0x0008 /* MGA card has old firmware */
#define MULTILINK_MACH_FLAG 0x0010 /* some nodes are connected */
/* by sevral IP links */

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@ -1,6 +0,0 @@
#ifndef _ASM_L_CLKR_H
#define _ASM_L_CLKR_H
extern struct clocksource clocksource_clkr;
#endif

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@ -95,7 +95,6 @@ extern __visible void epic_smp_timer_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_spurious_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_error_interrupt(struct pt_regs *regs);
extern __visible void prepic_smp_error_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_irq_move_cleanup_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_irq_work_interrupt(struct pt_regs *regs);
extern __visible void cepic_epic_interrupt(struct pt_regs *regs);
extern __visible void epic_hc_emerg_interrupt(struct pt_regs *regs);
@ -108,6 +107,7 @@ extern __visible void epic_pcs_interrupt(struct pt_regs *regs);
extern __visible void epic_pv_apf_wake(struct pt_regs *regs);
#endif /* CONFIG_KVM_ASYNC_PF */
#ifdef CONFIG_SMP
extern __visible void epic_smp_irq_move_cleanup_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_reschedule_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_call_function_interrupt(struct pt_regs *regs);
extern __visible void epic_smp_call_function_single_interrupt(

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@ -28,11 +28,6 @@ typedef struct {
IS_ENABLED(CONFIG_RDMA_NET))
unsigned int irq_rdma_count;
#endif
#ifdef CONFIG_E2K
#if IS_ENABLED(CONFIG_ELDSP)
unsigned int irq_eldsp_count;
#endif
#endif
} ____cacheline_aligned irq_cpustat_t;
DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);

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@ -134,7 +134,7 @@ extern void smp_trace_call_function_single_interrupt(struct pt_regs *regs);
extern void do_nmi(struct pt_regs * regs);
extern void l_init_system_handlers_table(void);
extern void epic_init_system_handlers_table(void);
extern void setup_APIC_vector_handler(int vector,
extern void setup_PIC_vector_handler(int vector,
void (*handler)(struct pt_regs *), bool system, char *name);
extern void do_IRQ(struct pt_regs * regs, unsigned int vector);

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@ -59,6 +59,16 @@ static inline void __pic_setup_vector_irq(int cpu)
__apic_setup_vector_irq(cpu);
}
extern void fixup_irqs_epic(void);
extern void fixup_irqs_apic(void);
static inline void fixup_irqs_pic(void)
{
if (nr_ioepics)
fixup_irqs_epic();
if (nr_ioapics)
fixup_irqs_apic();
}
extern void print_IO_APICs(void);
extern void print_IO_EPICs(void);
static inline void print_IO_PICs(void)
@ -96,6 +106,12 @@ static inline void __pic_setup_vector_irq(int cpu)
__apic_setup_vector_irq(cpu);
}
extern void fixup_irqs_apic(void);
static inline void fixup_irqs_pic(void)
{
fixup_irqs_apic();
}
extern void print_IO_APICs(void);
static inline void print_IO_PICs(void)
{

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@ -487,12 +487,10 @@ static inline int __iolinklist_parse(const char *buf, iolinkmask_t *dstp, int nb
(link) = iolink_domain_to_link((domain)))
#else /* MAX_NUMIOLINKS == 1 */
#define for_each_iolink_mask(domain, mask) \
if (HAS_MACHINE_E2K_IOHUB) \
for ((domain) = 0; (domain) < 1; (domain)++)
for ((domain) = 0; (domain) < 1; (domain)++)
#define for_each_node_iolink_mask(domain, node, link, mask) \
if (HAS_MACHINE_E2K_IOHUB) \
for ((domain) = 0, (node) = 0, (link) = 0; \
(domain) < 1; (domain)++)
for ((domain) = 0, (node) = 0, (link) = 0; \
(domain) < 1; (domain)++)
#endif /* MAX_NUMIOLINKS */
/*

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@ -371,6 +371,7 @@ typedef struct mpc_gpio_act {
struct iohub_sysdata;
void mp_pci_add_resources(struct list_head *resources,
struct iohub_sysdata *sd);
extern int __init mp_ioepic_find_bus(int ioepic_id);
#ifdef CONFIG_IOHUB_DOMAINS
struct iohub_sysdata;
extern int mp_find_iolink_root_busnum(int node, int link);

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@ -15,6 +15,13 @@ extern int apic_get_vector(void);
#include <asm/epic.h>
#include <asm/machdep.h>
#define pic_printk(v, s, a...) \
do { \
if (cpu_has_epic()) \
epic_printk(s, a); \
else \
apic_printk(v, s, a); \
} while (0)
static inline unsigned int read_pic_id(void)
{
@ -117,6 +124,17 @@ static inline void pic_send_reschedule(int cpu)
else
apic_smp_send_reschedule(cpu);
}
struct irq_desc;
extern void apic_irq_force_complete_move(struct irq_desc *desc);
extern void epic_irq_force_complete_move(struct irq_desc *desc);
static inline void pic_irq_force_complete_move(struct irq_desc *desc)
{
if (cpu_has_epic())
epic_irq_force_complete_move(desc);
else
apic_irq_force_complete_move(desc);
}
#endif
struct pt_regs;
@ -273,6 +291,7 @@ static inline void pic_irq_work_raise(void)
apic_irq_work_raise();
}
#ifdef CONFIG_SMP
extern void apic_send_call_function_ipi_mask(const struct cpumask *mask);
static inline void pic_send_call_function_ipi_mask(const struct cpumask *mask)
{
@ -291,6 +310,14 @@ static inline void pic_send_reschedule(int cpu)
apic_smp_send_reschedule(cpu);
}
struct irq_desc;
extern void apic_irq_force_complete_move(struct irq_desc *desc);
static inline void pic_irq_force_complete_move(struct irq_desc *desc)
{
apic_irq_force_complete_move(desc);
}
#endif /* CONFIG_SMP */
struct pt_regs;
extern noinline notrace void apic_do_nmi(struct pt_regs *regs);
static inline void pic_do_nmi(struct pt_regs *regs)

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@ -7,6 +7,7 @@ generic-y += emergency-restart.h
generic-y += ioctl.h
generic-y += irq_regs.h
generic-y += kmap_types.h
generic-y += kvm_para.h
generic-y += local64.h
generic-y += mcs_spinlock.h
generic-y += mm-arch-hooks.h

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@ -69,9 +69,9 @@ typedef union e2k_fapb_aps {
#define get_vlc(reg) ((reg >> LSR_VLC_SHIFT) & LSR_VLC_MASK)
static inline void
native_get_array_descriptors_v2(e2k_aau_t *context)
native_get_array_descriptors_v3(e2k_aau_t *context)
{
NATIVE_GET_ARRAY_DESCRIPTORS_V2(context);
NATIVE_GET_ARRAY_DESCRIPTORS_V3(context);
}
static inline void
native_get_array_descriptors_v5(e2k_aau_t *context)
@ -86,9 +86,9 @@ native_set_array_descriptors(const e2k_aau_t *context)
}
static inline void
native_get_synchronous_part_v2(e2k_aau_t *context)
native_get_synchronous_part_v3(e2k_aau_t *context)
{
NATIVE_GET_SYNCHRONOUS_PART_V2(context);
NATIVE_GET_SYNCHRONOUS_PART_V3(context);
}
static inline void
native_get_synchronous_part_v5(e2k_aau_t *context)
@ -130,9 +130,9 @@ static __always_inline void native_set_aau_aaldis_aaldas(
* and comparison with aasr.iab was taken.
*/
static inline void
native_get_aau_context_v2(e2k_aau_t *context, e2k_aasr_t aasr)
native_get_aau_context_v3(e2k_aau_t *context, e2k_aasr_t aasr)
{
NATIVE_GET_AAU_CONTEXT_V2(context, aasr);
NATIVE_GET_AAU_CONTEXT_V3(context, aasr);
}
static inline void
native_get_aau_context_v5(e2k_aau_t *context, e2k_aasr_t aasr)
@ -160,24 +160,24 @@ static __always_inline void native_set_aau_context(const e2k_aau_t *context,
/* native kernel without virtualization */
/* or native host kernel with virtualization support */
#define GET_ARRAY_DESCRIPTORS_V2(aau_context) \
#define GET_ARRAY_DESCRIPTORS_V3(aau_context) \
({ \
native_get_array_descriptors_v2(aau_context); \
native_get_array_descriptors_v3(aau_context); \
})
#define GET_ARRAY_DESCRIPTORS_V5(aau_context) \
({ \
native_get_array_descriptors_v5(aau_context); \
})
#define GET_SYNCHRONOUS_PART_V2(aau_context) \
#define GET_SYNCHRONOUS_PART_V3(aau_context) \
({ \
native_get_synchronous_part_v2(aau_context); \
native_get_synchronous_part_v3(aau_context); \
})
#define GET_SYNCHRONOUS_PART_V5(aau_context) \
({ \
native_get_synchronous_part_v5(aau_context); \
})
#define GET_AAU_CONTEXT_V2(cntx, aasr) native_get_aau_context_v2(cntx, aasr)
#define GET_AAU_CONTEXT_V3(cntx, aasr) native_get_aau_context_v3(cntx, aasr)
#define GET_AAU_CONTEXT_V5(cntx, aasr) native_get_aau_context_v5(cntx, aasr)
#define SAVE_AAU_MASK_REGS(aau_context, aasr) \
@ -193,7 +193,7 @@ static __always_inline void native_set_aau_context(const e2k_aau_t *context,
NATIVE_RESTORE_AADS(aau_regs)
#define SAVE_AALDIS_V2(regs) NATIVE_SAVE_AALDIS_V2(regs)
#define SAVE_AALDIS_V3(regs) NATIVE_SAVE_AALDIS_V3(regs)
#define SAVE_AALDIS_V5(regs) NATIVE_SAVE_AALDIS_V5(regs)
#define SAVE_AALDA(aaldas) \

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@ -148,21 +148,21 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
PV_TYPE##_READ_AALDI_REG_VALUE_##ISET(30, regs[30], regs[62]); \
PV_TYPE##_READ_AALDI_REG_VALUE_##ISET(31, regs[31], regs[63]); \
})
#define PREFIX_SAVE_AALDIS_V2(PV_TYPE, pv_type, regs) \
PREFIX_SAVE_AALDIS(PV_TYPE, pv_type, V2, v2, regs)
#define PREFIX_SAVE_AALDIS_V3(PV_TYPE, pv_type, regs) \
PREFIX_SAVE_AALDIS(PV_TYPE, pv_type, V3, v3, regs)
#define PREFIX_SAVE_AALDIS_V5(PV_TYPE, pv_type, regs) \
PREFIX_SAVE_AALDIS(PV_TYPE, pv_type, V5, v5, regs)
#define NATIVE_SAVE_AALDIS_V2(regs) \
PREFIX_SAVE_AALDIS_V2(NATIVE, native, regs)
#define NATIVE_SAVE_AALDIS_V3(regs) \
PREFIX_SAVE_AALDIS_V3(NATIVE, native, regs)
#define NATIVE_SAVE_AALDIS_V5(regs) \
PREFIX_SAVE_AALDIS_V5(NATIVE, native, regs)
#define NATIVE_SAVE_AALDIS(regs) \
({ \
if (IS_AAU_ISET_V5()) { \
NATIVE_SAVE_AALDIS_V5(regs); \
} else if (IS_AAU_ISET_V2()) { \
NATIVE_SAVE_AALDIS_V2(regs); \
} else if (IS_AAU_ISET_V3()) { \
NATIVE_SAVE_AALDIS_V3(regs); \
} else if (IS_AAU_ISET_GENERIC()) { \
machine.save_aaldi(regs); \
} else { \
@ -170,7 +170,7 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
} \
})
#define PREFIX_GET_ARRAY_DESCRIPTORS_V2(PV_TYPE, pv_type, aau_context) \
#define PREFIX_GET_ARRAY_DESCRIPTORS_V3(PV_TYPE, pv_type, aau_context) \
({ \
u64 *const aainds = (aau_context)->aainds; \
u64 *const aaincrs = (aau_context)->aaincrs; \
@ -186,14 +186,14 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
ind13, ind14, ind15; \
register u32 tags; \
\
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(1, ind1, ind2); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(3, ind3, ind4); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(5, ind5, ind6); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(7, ind7, ind8); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(9, ind9, ind10); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(11, ind11, ind12); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V2(13, ind13, ind14); \
PV_TYPE##_READ_AAIND_REG15_AND_TAGS_VALUE_V2(ind15, tags); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(1, ind1, ind2); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(3, ind3, ind4); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(5, ind5, ind6); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(7, ind7, ind8); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(9, ind9, ind10); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(11, ind11, ind12); \
PV_TYPE##_READ_AAINDS_PAIR_VALUE_V3(13, ind13, ind14); \
PV_TYPE##_READ_AAIND_REG15_AND_TAGS_VALUE_V3(ind15, tags); \
aainds[0] = 0; \
aainds[1] = ind1; \
aainds[2] = ind2; \
@ -222,10 +222,10 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
incr5, incr6, incr7; \
register u32 tags; \
\
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V2(1, incr1, incr2); \
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V2(3, incr3, incr4); \
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V2(5, incr5, incr6); \
PV_TYPE##_READ_AAINCR_REG7_AND_TAGS_VALUE_V2(incr7, tags); \
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V3(1, incr1, incr2); \
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V3(3, incr3, incr4); \
PV_TYPE##_READ_AAINCRS_PAIR_VALUE_V3(5, incr5, incr6); \
PV_TYPE##_READ_AAINCR_REG7_AND_TAGS_VALUE_V3(incr7, tags); \
aaincrs[0] = 1; \
aaincrs[1] = (s64) (s32) incr1; \
aaincrs[2] = (s64) (s32) incr2; \
@ -237,8 +237,8 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
context->aaincr_tags = tags; \
} \
})
#define NATIVE_GET_ARRAY_DESCRIPTORS_V2(aau_context) \
PREFIX_GET_ARRAY_DESCRIPTORS_V2(NATIVE, native, aau_context)
#define NATIVE_GET_ARRAY_DESCRIPTORS_V3(aau_context) \
PREFIX_GET_ARRAY_DESCRIPTORS_V3(NATIVE, native, aau_context)
#define PREFIX_GET_ARRAY_DESCRIPTORS_V5(PV_TYPE, pv_type, aau_context) \
({ \
@ -344,7 +344,7 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
#define NATIVE_SET_ARRAY_DESCRIPTORS(aau_context) \
PREFIX_SET_ARRAY_DESCRIPTORS(NATIVE, native, aau_context)
#define PREFIX_GET_SYNCHRONOUS_PART_V2(PV_TYPE, pv_type, aau_context) \
#define PREFIX_GET_SYNCHRONOUS_PART_V3(PV_TYPE, pv_type, aau_context) \
({ \
u64 *const aastis = (aau_context)->aastis; \
register u32 sti0, sti1, sti2, sti3, \
@ -353,14 +353,14 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
sti12, sti13, sti14, sti15; \
\
/* get AASTIs */ \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(0, sti0, sti1); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(2, sti2, sti3); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(4, sti4, sti5); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(6, sti6, sti7); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(8, sti8, sti9); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(10, sti10, sti11); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(12, sti12, sti13); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V2(14, sti14, sti15); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(0, sti0, sti1); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(2, sti2, sti3); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(4, sti4, sti5); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(6, sti6, sti7); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(8, sti8, sti9); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(10, sti10, sti11); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(12, sti12, sti13); \
PV_TYPE##_READ_AASTIS_PAIR_VALUE_V3(14, sti14, sti15); \
\
aastis[0] = sti0; \
aastis[1] = sti1; \
@ -419,8 +419,8 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
(aau_context)->aasti_tags = \
pv_type##_read_aasti_tags_reg_value(); \
})
#define NATIVE_GET_SYNCHRONOUS_PART_V2(aau_context) \
PREFIX_GET_SYNCHRONOUS_PART_V2(NATIVE, native, aau_context)
#define NATIVE_GET_SYNCHRONOUS_PART_V3(aau_context) \
PREFIX_GET_SYNCHRONOUS_PART_V3(NATIVE, native, aau_context)
#define NATIVE_GET_SYNCHRONOUS_PART_V5(aau_context) \
PREFIX_GET_SYNCHRONOUS_PART_V5(NATIVE, native, aau_context)
@ -508,20 +508,20 @@ static inline e2k_aasr_t aasr_parse(e2k_aasr_t aasr)
if (aasr.stb) \
PV_TYPE##_GET_SYNCHRONOUS_PART_##ISET(aau_context); \
})
#define PREFIX_GET_AAU_CONTEXT_V2(PV_TYPE, pv_type, aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT(PV_TYPE, pv_type, V2, v2, aau_context, aasr)
#define PREFIX_GET_AAU_CONTEXT_V3(PV_TYPE, pv_type, aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT(PV_TYPE, pv_type, V3, v3, aau_context, aasr)
#define PREFIX_GET_AAU_CONTEXT_V5(PV_TYPE, pv_type, aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT(PV_TYPE, pv_type, V5, v5, aau_context, aasr)
#define NATIVE_GET_AAU_CONTEXT_V2(aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT_V2(NATIVE, native, aau_context, aasr)
#define NATIVE_GET_AAU_CONTEXT_V3(aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT_V3(NATIVE, native, aau_context, aasr)
#define NATIVE_GET_AAU_CONTEXT_V5(aau_context, aasr) \
PREFIX_GET_AAU_CONTEXT_V5(NATIVE, native, aau_context, aasr)
#define NATIVE_GET_AAU_CONTEXT(aau_context, aasr) \
do { \
if (IS_AAU_ISET_V5()) { \
NATIVE_GET_AAU_CONTEXT_V5(aau_context, aasr); \
} else if (IS_AAU_ISET_V2()) { \
NATIVE_GET_AAU_CONTEXT_V2(aau_context, aasr); \
} else if (IS_AAU_ISET_V3()) { \
NATIVE_GET_AAU_CONTEXT_V3(aau_context, aasr); \
} else if (IS_AAU_ISET_GENERIC()) { \
machine.get_aau_context(aau_context, aasr); \
} else { \

View File

@ -22,20 +22,20 @@
#if CONFIG_CPU_ISET >= 5
# define IS_AAU_ISET_V5() true
# define IS_AAU_ISET_V2() false
# define IS_AAU_ISET_V3() false
# define IS_AAU_ISET_GENERIC() false
#elif CONFIG_CPU_ISET >= 1
# define IS_AAU_ISET_V2() true
# define IS_AAU_ISET_V3() true
# define IS_AAU_ISET_V5() false
# define IS_AAU_ISET_GENERIC() false
#elif CONFIG_CPU_ISET == 0
# define IS_AAU_ISET_GENERIC() true
# define IS_AAU_ISET_V2() false
# define IS_AAU_ISET_V3() false
# define IS_AAU_ISET_V5() false
#else /* CONFIG_CPU_ISET undefined or negative */
# warning "Undefined CPU ISET VERSION #, IS_AAU_ISET_Vx is defined dinamicaly"
# define IS_AAU_ISET_GENERIC() true
# define IS_AAU_ISET_V2() false
# define IS_AAU_ISET_V3() false
# define IS_AAU_ISET_V5() false
#endif /* CONFIG_CPU_ISET 0-6 */

View File

@ -35,7 +35,7 @@ register unsigned long long __cpu_preempt_reg DO_ASM_GET_GREG_MEMONIC(SMP_CPU_ID
#elif defined(E2K_P2V)
# define NATIVE_HWBUG_AFTER_LD_ACQ_ADDRESS \
(NATIVE_NV_READ_IP_REG_VALUE() & ~0x3fUL)
(NATIVE_READ_IP_REG_VALUE() & ~0x3fUL)
# define NATIVE_HWBUG_AFTER_LD_ACQ_CPU 0
# if !defined(CONFIG_E2K_MACHINE) || defined(CONFIG_E2K_E8C)
# define NATIVE_HAS_HWBUG_AFTER_LD_ACQ_ADDRESS 1
@ -46,7 +46,7 @@ register unsigned long long __cpu_preempt_reg DO_ASM_GET_GREG_MEMONIC(SMP_CPU_ID
#else /* CONFIG_BOOT_E2K */
# define NATIVE_HWBUG_AFTER_LD_ACQ_ADDRESS \
(NATIVE_NV_READ_IP_REG_VALUE() & ~0x3fUL)
(NATIVE_READ_IP_REG_VALUE() & ~0x3fUL)
# define NATIVE_HAS_HWBUG_AFTER_LD_ACQ_ADDRESS 0
# define NATIVE_HWBUG_AFTER_LD_ACQ_CPU 0

View File

@ -78,7 +78,7 @@ do { \
/*
* store_release() - same as __smp_store_release but acts on device accesses too
*/
#define store_release_v2 __smp_store_release
#define store_release_v3 __smp_store_release
#define store_release_v6(p, v) \
do { \
__typeof__(*(p)) __sr6_v = (v); \
@ -95,7 +95,7 @@ do { \
if (cpu_has(CPU_FEAT_ISET_V6)) \
store_release_v6((p), (v)); \
else \
store_release_v2((p), (v)); \
store_release_v3((p), (v)); \
} while (0)
#if CONFIG_CPU_ISET >= 6

View File

@ -1,7 +1,6 @@
#ifndef _E2K_CACHE_H_
#define _E2K_CACHE_H_
#include <asm/es2.h>
#include <asm/e2s.h>
#include <asm/e8c.h>
#include <asm/e8c2.h>
@ -10,54 +9,30 @@
#include <asm/e12c.h>
#include <asm/e2c3.h>
#define _max_(a, b) ((a) > (b) ? (a) : (b))
#define _max_(a, b) ((a) > (b) ? (a) : (b))
#define _max3_(a, b, c) _max_((a), _max_((b), (c)))
#define L1_CACHE_SHIFT 5
#define L2_CACHE_SHIFT 6
#ifdef CONFIG_E2K_MACHINE
# if defined(CONFIG_E2K_ES2_DSP) || defined(CONFIG_E2K_ES2_RU)
# define L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
# elif defined(CONFIG_E2K_E2S)
# define L1_CACHE_SHIFT E2S_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E2S_L2_CACHE_SHIFT
# elif defined(CONFIG_E2K_E8C)
# define L1_CACHE_SHIFT E8C_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E8C_L2_CACHE_SHIFT
# if defined(CONFIG_E2K_E8C)
# define L3_CACHE_SHIFT E8C_L3_CACHE_SHIFT
# elif defined(CONFIG_E2K_E1CP)
# define L1_CACHE_SHIFT E1CP_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E1CP_L2_CACHE_SHIFT
# elif defined(CONFIG_E2K_E8C2)
# define L1_CACHE_SHIFT E8C2_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E8C2_L2_CACHE_SHIFT
# define L3_CACHE_SHIFT E8C2_L3_CACHE_SHIFT
# elif defined(CONFIG_E2K_E12C)
# define L1_CACHE_SHIFT E12C_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E12C_L2_CACHE_SHIFT
# define L3_CACHE_SHIFT E12C_L3_CACHE_SHIFT
# elif defined(CONFIG_E2K_E16C)
# define L1_CACHE_SHIFT E16C_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E16C_L2_CACHE_SHIFT
# define L3_CACHE_SHIFT E16C_L3_CACHE_SHIFT
# elif defined(CONFIG_E2K_E2C3)
# define L1_CACHE_SHIFT E2C3_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT E2C3_L2_CACHE_SHIFT
# else
# error "E2K MACHINE type does not defined"
# endif
# ifndef L3_CACHE_SHIFT
# define L3_CACHE_SHIFT 0
# define L3_CACHE_SHIFT 0
# endif
#else /* ! CONFIG_E2K_MACHINE */
/*
* FIXME: Take it in mind while adding new cpu type
*/
# define L1_CACHE_SHIFT_MAX ES2_L1_CACHE_SHIFT
# define L2_CACHE_SHIFT_MAX ES2_L2_CACHE_SHIFT
# define L3_CACHE_SHIFT_MAX E8C_L3_CACHE_SHIFT
# define L1_CACHE_SHIFT L1_CACHE_SHIFT_MAX
# define L2_CACHE_SHIFT L2_CACHE_SHIFT_MAX
# define L3_CACHE_SHIFT L3_CACHE_SHIFT_MAX
#endif /* CONFIG_E2K_MACHINE */

View File

@ -64,13 +64,11 @@ extern void native_flush_icache_page(struct vm_area_struct *vma,
#define flush_icache_page(vma, page) __flush_icache_page(vma, page)
#define smp_flush_icache_all()
#define native_smp_flush_icache_range(start, end)
#define native_smp_flush_icache_range_array(icache_range_arr)
#define native_smp_flush_icache_page(vma, page)
#define native_smp_flush_icache_kernel_line(addr)
#else /* CONFIG_SMP */
extern void smp_flush_icache_all(void);
extern void native_smp_flush_icache_range(e2k_addr_t start, e2k_addr_t end);
extern void native_smp_flush_icache_range_array(
icache_range_array_t *icache_range_arr);
extern void native_smp_flush_icache_page(struct vm_area_struct *vma,
@ -78,24 +76,9 @@ extern void native_smp_flush_icache_page(struct vm_area_struct *vma,
extern void native_smp_flush_icache_kernel_line(e2k_addr_t addr);
#define flush_icache_all() smp_flush_icache_all()
#define flush_icache_range(start, end) \
({ \
if (cpu_has(CPU_FEAT_FLUSH_DC_IC)) \
__flush_icache_range(start, end); \
else \
smp_flush_icache_range(start, end); \
})
#define flush_icache_range(start, end) __flush_icache_range(start, end);
#define flush_icache_range_array smp_flush_icache_range_array
#define flush_icache_page(vma, page) \
({ \
if (cpu_has(CPU_FEAT_FLUSH_DC_IC)) \
__flush_icache_page(vma, page); \
else \
smp_flush_icache_page(vma, page); \
})
#define flush_icache_page(vma, page) __flush_icache_page(vma, page);
#endif /* ! (CONFIG_SMP) */
@ -162,11 +145,6 @@ native_clear_DCACHE_L1_range(void *virt_addr, size_t len)
/* it is native kernel without virtualization support */
/* or native kernel with virtualization support */
static inline void
smp_flush_icache_range(e2k_addr_t start, e2k_addr_t end)
{
native_smp_flush_icache_range(start, end);
}
static inline void
smp_flush_icache_range_array(icache_range_array_t *icache_range_arr)
{
native_smp_flush_icache_range_array(icache_range_arr);

View File

@ -46,12 +46,7 @@ static inline __wsum ip_fast_csum_nofold_maybe_unaligned(const void *iph, unsign
#define ip_fast_csum ip_fast_csum
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
if (cpu_has(CPU_HWBUG_UNALIGNED_LOADS) &&
!IS_ALIGNED((unsigned long) iph, 4))
return (__force __sum16) ~e2k_do_csum(iph, ihl*4);
else
return csum_fold(ip_fast_csum_nofold_maybe_unaligned(iph, ihl));
return csum_fold(ip_fast_csum_nofold_maybe_unaligned(iph, ihl));
}
static inline u32 add32_with_carry(u32 a, u32 b)
@ -86,8 +81,7 @@ __wsum __csum_partial(const void *buff, int len, __wsum sum);
static inline __wsum csum_partial(const void *buff, int len, __wsum sum)
{
if (__builtin_constant_p(len) && len <= 16 && (len & 1) == 0 &&
!cpu_has(CPU_HWBUG_UNALIGNED_LOADS)) {
if (__builtin_constant_p(len) && len <= 16 && (len & 1) == 0) {
u64 sum_64 = (__force u32) sum;
if (len == 2)
@ -108,8 +102,7 @@ static inline __wsum csum_partial(const void *buff, int len, __wsum sum)
sum_64 += *(const u32 *) (buff + 12);
sum = from64to32(sum_64);
} else if (__builtin_constant_p(len) && (len & 3) == 0 &&
!cpu_has(CPU_HWBUG_UNALIGNED_LOADS)) {
} else if (__builtin_constant_p(len) && (len & 3) == 0) {
sum = csum_add(sum, ip_fast_csum_nofold_maybe_unaligned(buff, len >> 2));
} else {
prefetch((__force void *) buff);

View File

@ -2,12 +2,6 @@
#define _ASM_E2K_CLKR_H
#include <asm/cpu.h>
#include <asm-l/clkr.h>
extern __interrupt u64 fast_syscall_read_clkr(void);
extern u64 last_clkr;
DECLARE_PER_CPU(u64, clkr_offset);
#if defined(CONFIG_PARAVIRT_GUEST)
/* it is paravirtualized guest and host kernel */

View File

@ -11,24 +11,13 @@
static inline char mc146818_cmos_read(char addr)
{
if (HAS_MACHINE_E2K_IOHUB) {
WARN_ONCE(1, "Warning: CMOS_READ attempted on a machine without a functioning CMOS\n");
return 0;
}
outb_p((addr),RTC_PORT(0));
return inb_p(RTC_PORT(1));
WARN_ONCE(1, "Warning: CMOS_READ attempted on a machine without a functioning CMOS\n");
return 0;
}
static inline void mc146818_cmos_write(char val, char addr)
{
if (HAS_MACHINE_E2K_IOHUB) {
WARN_ONCE(1, "Warning: CMOS_WRITE attempted on a machine without a functioning CMOS\n");
return;
}
outb_p(addr, RTC_PORT(0));
outb_p(val, RTC_PORT(1));
WARN_ONCE(1, "Warning: CMOS_WRITE attempted on a machine without a functioning CMOS\n");
}
#define CMOS_READ(addr) mc146818_cmos_read(addr)

View File

@ -139,7 +139,7 @@ native_kernel_hw_stack_frames_copy(u64 *dst, const u64 *src, unsigned long size)
} else {
#pragma loop count (5)
for (i = 0; i < size / 128; i++)
E2K_TAGGED_MEMMOVE_128_RF_V2(&dst[16 * i],
E2K_TAGGED_MEMMOVE_128_RF_V3(&dst[16 * i],
&src[16 * i]);
copied = round_down(size, 128);
@ -619,7 +619,7 @@ static inline void collapse_kernel_hw_stacks(struct e2k_stacks *stacks)
* we will have pcshtp = pcsp_hi.ind = 0. But situation
* with pcsp_hi.ind != 0 and pcshtp = 0 is impossible. */
if (WARN_ON_ONCE(spilled_pc_size < SZ_OF_CR &&
AS(stacks->pcsp_hi).ind != 0))
AS(stacks->pcsp_hi).ind != 0 && !paravirt_enabled()))
do_exit(SIGKILL);
/* Keep the last user frame (see user_hw_stacks_copy_full()) */

View File

@ -4,16 +4,9 @@
#ifndef __ASSEMBLY__
enum {
/* Hardware bugs */
CPU_HWBUG_LARGE_PAGES,
CPU_HWBUG_LAPIC_TIMER,
CPU_HWBUG_PIO_READS,
CPU_HWBUG_ATOMIC,
CPU_HWBUG_CLW,
CPU_HWBUG_PAGE_A,
CPU_HWBUG_SPURIOUS_EXC_ILL_INSTR_ADDR,
CPU_HWBUG_UNALIGNED_LOADS,
CPU_HWBUG_CANNOT_DO_DMA_IN_NEIGHBOUR_NODE,
CPU_HWBUG_DMA_AT_APIC_ADDR,
CPU_HWBUG_KERNEL_DATA_MONITOR,
CPU_HWBUG_WRITE_MEMORY_BARRIER,
CPU_HWBUG_BAD_RESET,
@ -43,8 +36,6 @@ enum {
CPU_HWBUG_C3,
/* Features, not bugs */
CPU_FEAT_WC_PCI_PREFETCH,
CPU_FEAT_FLUSH_DC_IC,
CPU_FEAT_EPIC,
CPU_FEAT_TRAP_V5,
CPU_FEAT_TRAP_V6,
@ -53,7 +44,6 @@ enum {
CPU_FEAT_SEPARATE_TLU_CACHE,
CPU_FEAT_FILLR,
CPU_FEAT_FILLC,
CPU_FEAT_ISET_V3,
CPU_FEAT_ISET_V5,
CPU_FEAT_ISET_V6,

View File

@ -547,11 +547,6 @@ write_OSGD_hi_reg(e2k_osgd_hi_t OSGD_hi)
* from the high & low word structure
*/
#define WRITE_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value) \
({ \
WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value); \
WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value); \
})
#define BOOT_WRITE_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value) \
({ \
BOOT_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value); \

View File

@ -134,6 +134,8 @@
NATIVE_WRITE_OSGD_LO_REG_VALUE(OSGD_lo_value)
#define BOOT_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value) \
NATIVE_WRITE_OSGD_HI_REG_VALUE(OSGD_hi_value)
#define WRITE_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value) \
NATIVE_WRITE_OSGD_REG_VALUE(OSGD_hi_value, OSGD_lo_value)
/*
* Read/write low/high double-word Compilation Unit Register (CUD)
@ -393,7 +395,7 @@
/*
* Read double-word CPU current Instruction Pointer register (IP)
*/
#define READ_IP_REG_VALUE() NATIVE_NV_READ_IP_REG_VALUE()
#define READ_IP_REG_VALUE() NATIVE_READ_IP_REG_VALUE()
/*
* Read debug and monitors regigisters

View File

@ -1379,7 +1379,7 @@ typedef union e2k_dst {
#define AS_WORD(x) ((x).word)
#define AS_STRUCT(x) ((x).fields)
#define AS_V2_STRUCT(x) ((x).v2_fields)
#define AS_V3_STRUCT(x) ((x).v3_fields)
#define AS_V6_STRUCT(x) ((x).v6_fields)
#define AS_SAP_STRUCT(x) ((x).sap_fields)
#define AS_AP_STRUCT(x) ((x).ap_fields)
@ -1920,13 +1920,13 @@ typedef union e2k_tsd {
#define CUD_CFLAG_SET 1 /* ISV have passed */
/* Hardware procedure stack memory mapping (one quad-register record, LE) */
/* Istruction sets from V2 to V4 */
typedef struct e2k_mem_ps_v2 {
/* Istruction sets from V3 to V4 */
typedef struct e2k_mem_ps_v3 {
unsigned long word_lo; /* low word value */
unsigned long word_hi; /* high word value */
unsigned long ext_lo; /* extention of low word */
unsigned long ext_hi; /* extention of hagh word */
} e2k_mem_ps_v2_t;
} e2k_mem_ps_v3_t;
/* Istruction sets from V5 to V6 */
typedef struct e2k_mem_ps_v5 {
unsigned long word_lo; /* low word value */
@ -1935,7 +1935,7 @@ typedef struct e2k_mem_ps_v5 {
unsigned long ext_hi; /* extention of hagh word */
} e2k_mem_ps_v5_t;
typedef union e2k_mem_ps {
e2k_mem_ps_v2_t v2;
e2k_mem_ps_v3_t v3;
e2k_mem_ps_v5_t v5;
} e2k_mem_ps_t;
@ -2079,7 +2079,7 @@ typedef struct e2k_upsr_fields {
u32 a20 : 1; /* emulation of 1 Mb memory (only for Intel) */
/* should be 0 for Elbrus */
u32 nmie : 1; /* not masked interrupt enable */
/* next field of register exist only on ES2/E2S/E8C/E1C+ CPUs */
/* next field of register exist only on E2S/E8C/E1C+ CPUs */
u32 fsm : 1; /* floating comparison mode flag */
/* 1 - compatible with x86/x87 */
u32 impt : 1; /* ignore Memory Protection Table flag */
@ -2113,7 +2113,7 @@ typedef union e2k_upsr {
#define UPSR_IE 0x20U
#define UPSR_A20 0x40U
#define UPSR_NMIE 0x80U
/* next field of register exist only on ES2/E2S/E8C/E1C+ CPUs */
/* next field of register exist only on E2S/E8C/E1C+ CPUs */
#define UPSR_FSM 0x100U
#define UPSR_IMPT 0x200U
#define UPSR_IUC 0x400U
@ -2169,10 +2169,7 @@ typedef union e2k_idr {
/* CPU model numbers */
#define IDR_NONE 0x00 /* No such hardware exists */
#define IDR_E2S_MDL 0x03 /* Elbrus-4C (Elbrus-2S) */
#define IDR_ES2_DSP_MDL 0x04 /* Elbrus-2C+ */
#define IDR_E4S_MDL 0x05 /* reserve */
#define IDR_ES2_RU_MDL 0x06 /* Elbrus-2CM (without DSP) */
/* russian MICRON release */
#define IDR_E8C_MDL 0x07 /* Elbrus-8C */
#define IDR_E1CP_MDL 0x08 /* Elbrus-1C+ one processor e2s */
/* + graphic */

View File

@ -15,8 +15,6 @@ struct pt_regs;
extern void boot_e12c_setup_arch(void);
extern void e12c_setup_machine(void);
extern void setup_APIC_vector_handler(int vector,
void (*handler)(struct pt_regs *), bool system, char *name);
#endif
#define E12C_NR_NODE_CPUS 12
@ -24,35 +22,14 @@ extern void setup_APIC_vector_handler(int vector,
#define E12C_NODE_IOLINKS 1
#define E12C_PCICFG_AREA_PHYS_BASE ES2_PCICFG_AREA_PHYS_BASE
#define E12C_PCICFG_AREA_SIZE ES2_PCICFG_AREA_SIZE
#define E12C_PCICFG_AREA_PHYS_BASE E2S_PCICFG_AREA_PHYS_BASE
#define E12C_PCICFG_AREA_SIZE E2S_PCICFG_AREA_SIZE
#define E12C_NSR_AREA_PHYS_BASE ES2_NSR_AREA_PHYS_BASE
#define E12C_NBSR_AREA_OFFSET ES2_NBSR_AREA_OFFSET
#define E12C_NBSR_AREA_SIZE ES2_NBSR_AREA_SIZE
#define E12C_COPSR_AREA_PHYS_BASE ES2_COPSR_AREA_PHYS_BASE
#define E12C_COPSR_AREA_SIZE ES2_COPSR_AREA_SIZE
#define E12C_MLT_SIZE ES2_MLT_SIZE
#define E12C_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
#define E12C_TLB_ADDR_LINE_NUM E2S_TLB_ADDR_LINE_NUM
#define E12C_TLB_ADDR_LINE_NUM2 E2S_TLB_ADDR_LINE_NUM2
#define E12C_TLB_ADDR_LINE_NUM_SHIFT2 E2S_TLB_ADDR_LINE_NUM_SHIFT2
#define E12C_TLB_ADDR_SET_NUM E2S_TLB_ADDR_SET_NUM
#define E12C_TLB_ADDR_SET_NUM_SHIFT E2S_TLB_ADDR_SET_NUM_SHIFT
#define E12C_NSR_AREA_PHYS_BASE E2S_NSR_AREA_PHYS_BASE
#define E12C_SIC_MC_SIZE E16C_SIC_MC_SIZE
#define E12C_SIC_MC_COUNT 2
#define E12C_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
#define E12C_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
#define E12C_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
#define E12C_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
#define E12C_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
#define E12C_L3_CACHE_SHIFT E8C_L3_CACHE_SHIFT
#define E12C_L3_CACHE_BYTES E8C_L3_CACHE_BYTES

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@ -15,8 +15,6 @@ struct pt_regs;
extern void boot_e16c_setup_arch(void);
extern void e16c_setup_machine(void);
extern void setup_APIC_vector_handler(int vector,
void (*handler)(struct pt_regs *), bool system, char *name);
#endif
#define E16C_NR_NODE_CPUS 16
@ -24,35 +22,14 @@ extern void setup_APIC_vector_handler(int vector,
#define E16C_NODE_IOLINKS 1
#define E16C_PCICFG_AREA_PHYS_BASE ES2_PCICFG_AREA_PHYS_BASE
#define E16C_PCICFG_AREA_SIZE ES2_PCICFG_AREA_SIZE
#define E16C_PCICFG_AREA_PHYS_BASE E2S_PCICFG_AREA_PHYS_BASE
#define E16C_PCICFG_AREA_SIZE E2S_PCICFG_AREA_SIZE
#define E16C_NSR_AREA_PHYS_BASE ES2_NSR_AREA_PHYS_BASE
#define E16C_NBSR_AREA_OFFSET ES2_NBSR_AREA_OFFSET
#define E16C_NBSR_AREA_SIZE ES2_NBSR_AREA_SIZE
#define E16C_COPSR_AREA_PHYS_BASE ES2_COPSR_AREA_PHYS_BASE
#define E16C_COPSR_AREA_SIZE ES2_COPSR_AREA_SIZE
#define E16C_MLT_SIZE ES2_MLT_SIZE
#define E16C_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
#define E16C_TLB_ADDR_LINE_NUM E2S_TLB_ADDR_LINE_NUM
#define E16C_TLB_ADDR_LINE_NUM2 E2S_TLB_ADDR_LINE_NUM2
#define E16C_TLB_ADDR_LINE_NUM_SHIFT2 E2S_TLB_ADDR_LINE_NUM_SHIFT2
#define E16C_TLB_ADDR_SET_NUM E2S_TLB_ADDR_SET_NUM
#define E16C_TLB_ADDR_SET_NUM_SHIFT E2S_TLB_ADDR_SET_NUM_SHIFT
#define E16C_NSR_AREA_PHYS_BASE E2S_NSR_AREA_PHYS_BASE
#define E16C_SIC_MC_SIZE 0x60
#define E16C_SIC_MC_COUNT 8
#define E16C_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
#define E16C_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
#define E16C_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
#define E16C_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
#define E16C_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
#define E16C_L3_CACHE_SHIFT E8C_L3_CACHE_SHIFT
#define E16C_L3_CACHE_BYTES E8C_L3_CACHE_BYTES

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@ -21,26 +21,6 @@ extern void e1cp_setup_machine(void);
#define E1CP_PCICFG_AREA_PHYS_BASE 0x000000ff10000000UL
#define E1CP_PCICFG_AREA_SIZE 0x0000000010000000UL
#define E1CP_NBSR_AREA_OFFSET E2S_NBSR_AREA_OFFSET
#define E1CP_NBSR_AREA_SIZE E2S_NBSR_AREA_SIZE
#define E1CP_MLT_SIZE ES2_MLT_SIZE
#define E1CP_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
#define E1CP_TLB_ADDR_LINE_NUM E2S_TLB_ADDR_LINE_NUM
#define E1CP_TLB_ADDR_LINE_NUM2 E2S_TLB_ADDR_LINE_NUM2
#define E1CP_TLB_ADDR_LINE_NUM_SHIFT2 E2S_TLB_ADDR_LINE_NUM_SHIFT2
#define E1CP_TLB_ADDR_SET_NUM E2S_TLB_ADDR_SET_NUM
#define E1CP_TLB_ADDR_SET_NUM_SHIFT E2S_TLB_ADDR_SET_NUM_SHIFT
#define E1CP_SIC_MC_COUNT ES2_SIC_MC_COUNT
#define E1CP_SIC_MC1_ECC E2S_SIC_MC1_ECC
#define E1CP_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
#define E1CP_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
#define E1CP_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
#define E1CP_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
#define E1CP_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
#define E1CP_SIC_MC_COUNT 2
#endif /* _ASM_E1CP_H_ */

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@ -15,8 +15,6 @@ struct pt_regs;
extern void boot_e2c3_setup_arch(void);
extern void e2c3_setup_machine(void);
extern void setup_APIC_vector_handler(int vector,
void (*handler)(struct pt_regs *), bool system, char *name);
#endif
#define E2C3_NR_NODE_CPUS 2
@ -24,34 +22,12 @@ extern void setup_APIC_vector_handler(int vector,
#define E2C3_NODE_IOLINKS 1
#define E2C3_PCICFG_AREA_PHYS_BASE ES2_PCICFG_AREA_PHYS_BASE
#define E2C3_PCICFG_AREA_SIZE ES2_PCICFG_AREA_SIZE
#define E2C3_PCICFG_AREA_PHYS_BASE E2S_PCICFG_AREA_PHYS_BASE
#define E2C3_PCICFG_AREA_SIZE E2S_PCICFG_AREA_SIZE
#define E2C3_NSR_AREA_PHYS_BASE ES2_NSR_AREA_PHYS_BASE
#define E2C3_NBSR_AREA_OFFSET ES2_NBSR_AREA_OFFSET
#define E2C3_NBSR_AREA_SIZE ES2_NBSR_AREA_SIZE
#define E2C3_COPSR_AREA_PHYS_BASE ES2_COPSR_AREA_PHYS_BASE
#define E2C3_COPSR_AREA_SIZE ES2_COPSR_AREA_SIZE
#define E2C3_MLT_SIZE ES2_MLT_SIZE
#define E2C3_TLB_LINES_BITS_NUM ES2_TLB_LINES_BITS_NUM
#define E2C3_TLB_ADDR_LINE_NUM E2S_TLB_ADDR_LINE_NUM
#define E2C3_TLB_ADDR_LINE_NUM2 E2S_TLB_ADDR_LINE_NUM2
#define E2C3_TLB_ADDR_LINE_NUM_SHIFT2 E2S_TLB_ADDR_LINE_NUM_SHIFT2
#define E2C3_TLB_ADDR_SET_NUM E2S_TLB_ADDR_SET_NUM
#define E2C3_TLB_ADDR_SET_NUM_SHIFT E2S_TLB_ADDR_SET_NUM_SHIFT
#define E2C3_NSR_AREA_PHYS_BASE E2S_NSR_AREA_PHYS_BASE
#define E2C3_SIC_MC_SIZE E16C_SIC_MC_SIZE
#define E2C3_SIC_MC_COUNT E12C_SIC_MC_COUNT
#define E2C3_CLOCK_TICK_RATE ES2_CLOCK_TICK_RATE
#define E2C3_L1_CACHE_SHIFT ES2_L1_CACHE_SHIFT
#define E2C3_L1_CACHE_BYTES ES2_L1_CACHE_BYTES
#define E2C3_L2_CACHE_SHIFT ES2_L2_CACHE_SHIFT
#define E2C3_L2_CACHE_BYTES ES2_L2_CACHE_BYTES
#endif /* _ASM_E2C3_H_ */

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@ -8,7 +8,6 @@
#include <asm/e2k_api.h>
#include <asm/sections.h>
#include <asm/e2s.h>
#include <asm/es2.h>
#include <asm/e8c.h>
#include <asm/e1cp.h>
#include <asm/e8c2.h>
@ -20,37 +19,26 @@
#define MACHINE_ID_CPU_TYPE_MASK 0x000f
#define MACHINE_ID_SIMUL 0x0010
#define MACHINE_ID_E2K_FULL_SIC 0x0020
#define MACHINE_ID_E2K_IOHUB 0x0040
#define MACHINE_ID_L_IOMMU 0x0080
#define MACHINE_ID_E2K_LEGACY_SIC 0x0100 /* host bridge & legacy NBSR */
#define MACHINE_ID_E2K_VIRT_IO 0x0400 /* machine is virtual and */
#define MACHINE_ID_L_IOMMU 0x0040
#define MACHINE_ID_E2K_LEGACY_SIC 0x0080 /* host bridge & legacy NBSR */
#define MACHINE_ID_E2K_VIRT_IO 0x0100 /* machine is virtual and */
/* IO simulates on user level */
/* (for example by QEMU) */
#define MACHINE_ID_HW_VIRT 0x4000 /* hardware virtualized VM */
#define MACHINE_ID_VIRT 0x8000 /* soft paravirtualized VM */
#define MACHINE_ID_E2K_IOMMU 0x10000
#define MACHINE_ID_HW_VIRT 0x0200 /* hardware virtualized VM */
#define MACHINE_ID_VIRT 0x0400 /* soft paravirtualized VM */
#define MACHINE_ID_E2K_IOMMU 0x0800
#define MACHINE_ID_ES2_DSP (IDR_ES2_DSP_MDL | \
MACHINE_ID_E2K_FULL_SIC | \
MACHINE_ID_E2K_IOHUB)
#define MACHINE_ID_ES2_RU (IDR_ES2_RU_MDL | \
MACHINE_ID_E2K_FULL_SIC | \
MACHINE_ID_E2K_IOHUB)
#define MACHINE_ID_E2S (IDR_E2S_MDL | \
MACHINE_ID_E2K_FULL_SIC | \
MACHINE_ID_E2K_IOHUB | \
MACHINE_ID_L_IOMMU)
#define MACHINE_ID_E8C (IDR_E8C_MDL | \
MACHINE_ID_E2K_FULL_SIC | \
MACHINE_ID_E2K_IOHUB | \
MACHINE_ID_L_IOMMU)
#define MACHINE_ID_E1CP (IDR_E1CP_MDL | \
MACHINE_ID_E2K_LEGACY_SIC | \
MACHINE_ID_E2K_IOHUB | \
MACHINE_ID_L_IOMMU)
#define MACHINE_ID_E8C2 (IDR_E8C2_MDL | \
MACHINE_ID_E2K_FULL_SIC | \
MACHINE_ID_E2K_IOHUB | \
MACHINE_ID_L_IOMMU)
/*
* IO_* NBSRs are absent in models with EIOHub. Using LEGACY_SIC with FULL_SIC