2007-09-16 23:08:06 +02:00
|
|
|
/*
|
2006-04-28 01:15:07 +02:00
|
|
|
* ARM kernel loader.
|
|
|
|
*
|
2007-11-11 01:04:49 +01:00
|
|
|
* Copyright (c) 2006-2007 CodeSourcery.
|
2006-04-28 01:15:07 +02:00
|
|
|
* Written by Paul Brook
|
|
|
|
*
|
2011-06-26 04:21:35 +02:00
|
|
|
* This code is licensed under the GPL.
|
2006-04-28 01:15:07 +02:00
|
|
|
*/
|
|
|
|
|
2012-03-02 12:56:38 +01:00
|
|
|
#include "config.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/hw.h"
|
2013-04-09 16:26:55 +02:00
|
|
|
#include "hw/arm/arm.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/boards.h"
|
|
|
|
#include "hw/loader.h"
|
2009-09-20 16:58:02 +02:00
|
|
|
#include "elf.h"
|
2012-12-17 18:20:04 +01:00
|
|
|
#include "sysemu/device_tree.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/config-file.h"
|
2013-11-28 10:13:41 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2006-04-28 01:15:07 +02:00
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
/* Kernel boot protocol is specified in the kernel docs
|
|
|
|
* Documentation/arm/Booting and Documentation/arm64/booting.txt
|
|
|
|
* They have different preferred image load offsets from system RAM base.
|
|
|
|
*/
|
2006-04-28 01:15:07 +02:00
|
|
|
#define KERNEL_ARGS_ADDR 0x100
|
|
|
|
#define KERNEL_LOAD_ADDR 0x00010000
|
2013-12-17 20:42:30 +01:00
|
|
|
#define KERNEL64_LOAD_ADDR 0x00080000
|
2006-04-28 01:15:07 +02:00
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
typedef enum {
|
|
|
|
FIXUP_NONE = 0, /* do nothing */
|
|
|
|
FIXUP_TERMINATOR, /* end of insns */
|
|
|
|
FIXUP_BOARDID, /* overwrite with board ID number */
|
|
|
|
FIXUP_ARGPTR, /* overwrite with pointer to kernel args */
|
|
|
|
FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */
|
|
|
|
FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
|
|
|
|
FIXUP_BOOTREG, /* overwrite with boot register address */
|
|
|
|
FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
|
|
|
|
FIXUP_MAX,
|
|
|
|
} FixupType;
|
|
|
|
|
|
|
|
typedef struct ARMInsnFixup {
|
|
|
|
uint32_t insn;
|
|
|
|
FixupType fixup;
|
|
|
|
} ARMInsnFixup;
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
static const ARMInsnFixup bootloader_aarch64[] = {
|
|
|
|
{ 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
|
|
|
|
{ 0xaa1f03e1 }, /* mov x1, xzr */
|
|
|
|
{ 0xaa1f03e2 }, /* mov x2, xzr */
|
|
|
|
{ 0xaa1f03e3 }, /* mov x3, xzr */
|
|
|
|
{ 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
|
|
|
|
{ 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
|
|
|
|
{ 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */
|
|
|
|
{ 0 }, /* .word @DTB Higher 32-bits */
|
|
|
|
{ 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */
|
|
|
|
{ 0 }, /* .word @Kernel Entry Higher 32-bits */
|
|
|
|
{ 0, FIXUP_TERMINATOR }
|
|
|
|
};
|
|
|
|
|
2006-04-28 01:15:07 +02:00
|
|
|
/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
|
2013-12-17 20:42:30 +01:00
|
|
|
static const ARMInsnFixup bootloader[] = {
|
|
|
|
{ 0xe3a00000 }, /* mov r0, #0 */
|
|
|
|
{ 0xe59f1004 }, /* ldr r1, [pc, #4] */
|
|
|
|
{ 0xe59f2004 }, /* ldr r2, [pc, #4] */
|
|
|
|
{ 0xe59ff004 }, /* ldr pc, [pc, #4] */
|
|
|
|
{ 0, FIXUP_BOARDID },
|
|
|
|
{ 0, FIXUP_ARGPTR },
|
|
|
|
{ 0, FIXUP_ENTRYPOINT },
|
|
|
|
{ 0, FIXUP_TERMINATOR }
|
2006-04-28 01:15:07 +02:00
|
|
|
};
|
|
|
|
|
2012-01-26 12:43:48 +01:00
|
|
|
/* Handling for secondary CPU boot in a multicore system.
|
|
|
|
* Unlike the uniprocessor/primary CPU boot, this is platform
|
|
|
|
* dependent. The default code here is based on the secondary
|
|
|
|
* CPU boot protocol used on realview/vexpress boards, with
|
|
|
|
* some parameterisation to increase its flexibility.
|
|
|
|
* QEMU platform models for which this code is not appropriate
|
|
|
|
* should override write_secondary_boot and secondary_cpu_reset_hook
|
|
|
|
* instead.
|
|
|
|
*
|
|
|
|
* This code enables the interrupt controllers for the secondary
|
|
|
|
* CPUs and then puts all the secondary CPUs into a loop waiting
|
|
|
|
* for an interprocessor interrupt and polling a configurable
|
|
|
|
* location for the kernel secondary CPU entry point.
|
|
|
|
*/
|
2012-12-11 12:30:37 +01:00
|
|
|
#define DSB_INSN 0xf57ff04f
|
|
|
|
#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
static const ARMInsnFixup smpboot[] = {
|
|
|
|
{ 0xe59f2028 }, /* ldr r2, gic_cpu_if */
|
|
|
|
{ 0xe59f0028 }, /* ldr r0, bootreg_addr */
|
|
|
|
{ 0xe3a01001 }, /* mov r1, #1 */
|
|
|
|
{ 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
|
|
|
|
{ 0xe3a010ff }, /* mov r1, #0xff */
|
|
|
|
{ 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
|
|
|
|
{ 0, FIXUP_DSB }, /* dsb */
|
|
|
|
{ 0xe320f003 }, /* wfi */
|
|
|
|
{ 0xe5901000 }, /* ldr r1, [r0] */
|
|
|
|
{ 0xe1110001 }, /* tst r1, r1 */
|
|
|
|
{ 0x0afffffb }, /* beq <wfi> */
|
|
|
|
{ 0xe12fff11 }, /* bx r1 */
|
|
|
|
{ 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
|
|
|
|
{ 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
|
|
|
|
{ 0, FIXUP_TERMINATOR }
|
2007-11-11 01:04:49 +01:00
|
|
|
};
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
static void write_bootloader(const char *name, hwaddr addr,
|
|
|
|
const ARMInsnFixup *insns, uint32_t *fixupcontext)
|
|
|
|
{
|
|
|
|
/* Fix up the specified bootloader fragment and write it into
|
|
|
|
* guest memory using rom_add_blob_fixed(). fixupcontext is
|
|
|
|
* an array giving the values to write in for the fixup types
|
|
|
|
* which write a value into the code array.
|
|
|
|
*/
|
|
|
|
int i, len;
|
|
|
|
uint32_t *code;
|
|
|
|
|
|
|
|
len = 0;
|
|
|
|
while (insns[len].fixup != FIXUP_TERMINATOR) {
|
|
|
|
len++;
|
|
|
|
}
|
|
|
|
|
|
|
|
code = g_new0(uint32_t, len);
|
|
|
|
|
|
|
|
for (i = 0; i < len; i++) {
|
|
|
|
uint32_t insn = insns[i].insn;
|
|
|
|
FixupType fixup = insns[i].fixup;
|
|
|
|
|
|
|
|
switch (fixup) {
|
|
|
|
case FIXUP_NONE:
|
|
|
|
break;
|
|
|
|
case FIXUP_BOARDID:
|
|
|
|
case FIXUP_ARGPTR:
|
|
|
|
case FIXUP_ENTRYPOINT:
|
|
|
|
case FIXUP_GIC_CPU_IF:
|
|
|
|
case FIXUP_BOOTREG:
|
|
|
|
case FIXUP_DSB:
|
|
|
|
insn = fixupcontext[fixup];
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
code[i] = tswap32(insn);
|
|
|
|
}
|
|
|
|
|
|
|
|
rom_add_blob_fixed(name, code, len * sizeof(uint32_t), addr);
|
|
|
|
|
|
|
|
g_free(code);
|
|
|
|
}
|
|
|
|
|
2012-05-14 00:08:10 +02:00
|
|
|
static void default_write_secondary(ARMCPU *cpu,
|
2012-01-26 12:43:48 +01:00
|
|
|
const struct arm_boot_info *info)
|
|
|
|
{
|
2013-12-17 20:42:30 +01:00
|
|
|
uint32_t fixupcontext[FIXUP_MAX];
|
|
|
|
|
|
|
|
fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
|
|
|
|
fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
|
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
|
|
|
|
fixupcontext[FIXUP_DSB] = DSB_INSN;
|
|
|
|
} else {
|
|
|
|
fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
|
2012-01-26 12:43:48 +01:00
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
|
|
|
|
write_bootloader("smpboot", info->smp_loader_start,
|
|
|
|
smpboot, fixupcontext);
|
2012-01-26 12:43:48 +01:00
|
|
|
}
|
|
|
|
|
2012-05-14 01:05:40 +02:00
|
|
|
static void default_reset_secondary(ARMCPU *cpu,
|
2012-01-26 12:43:48 +01:00
|
|
|
const struct arm_boot_info *info)
|
|
|
|
{
|
2012-05-14 01:05:40 +02:00
|
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
|
2013-11-28 10:13:41 +01:00
|
|
|
stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0);
|
2012-01-26 12:43:48 +01:00
|
|
|
env->regs[15] = info->smp_loader_start;
|
|
|
|
}
|
|
|
|
|
2014-01-31 15:47:32 +01:00
|
|
|
static inline bool have_dtb(const struct arm_boot_info *info)
|
|
|
|
{
|
|
|
|
return info->dtb_filename || info->get_dtb;
|
|
|
|
}
|
|
|
|
|
2009-04-09 19:19:47 +02:00
|
|
|
#define WRITE_WORD(p, value) do { \
|
2013-11-28 10:13:41 +01:00
|
|
|
stl_phys_notdirty(&address_space_memory, p, value); \
|
2009-04-09 19:19:47 +02:00
|
|
|
p += 4; \
|
|
|
|
} while (0)
|
|
|
|
|
2012-01-29 08:52:15 +01:00
|
|
|
static void set_kernel_args(const struct arm_boot_info *info)
|
2006-04-28 01:15:07 +02:00
|
|
|
{
|
2012-01-29 08:52:15 +01:00
|
|
|
int initrd_size = info->initrd_size;
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr base = info->loader_start;
|
|
|
|
hwaddr p;
|
2006-04-28 01:15:07 +02:00
|
|
|
|
2009-04-09 19:19:47 +02:00
|
|
|
p = base + KERNEL_ARGS_ADDR;
|
2006-04-28 01:15:07 +02:00
|
|
|
/* ATAG_CORE */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 5);
|
|
|
|
WRITE_WORD(p, 0x54410001);
|
|
|
|
WRITE_WORD(p, 1);
|
|
|
|
WRITE_WORD(p, 0x1000);
|
|
|
|
WRITE_WORD(p, 0);
|
2006-04-28 01:15:07 +02:00
|
|
|
/* ATAG_MEM */
|
2008-04-14 22:27:51 +02:00
|
|
|
/* TODO: handle multiple chips on one ATAG list */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 4);
|
|
|
|
WRITE_WORD(p, 0x54410002);
|
|
|
|
WRITE_WORD(p, info->ram_size);
|
|
|
|
WRITE_WORD(p, info->loader_start);
|
2006-04-28 01:15:07 +02:00
|
|
|
if (initrd_size) {
|
|
|
|
/* ATAG_INITRD2 */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 4);
|
|
|
|
WRITE_WORD(p, 0x54420005);
|
2012-10-26 17:29:38 +02:00
|
|
|
WRITE_WORD(p, info->initrd_start);
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, initrd_size);
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|
2008-04-14 22:27:51 +02:00
|
|
|
if (info->kernel_cmdline && *info->kernel_cmdline) {
|
2006-04-28 01:15:07 +02:00
|
|
|
/* ATAG_CMDLINE */
|
|
|
|
int cmdline_size;
|
|
|
|
|
2008-04-14 22:27:51 +02:00
|
|
|
cmdline_size = strlen(info->kernel_cmdline);
|
2013-04-12 20:53:58 +02:00
|
|
|
cpu_physical_memory_write(p + 8, info->kernel_cmdline,
|
2009-04-09 19:19:47 +02:00
|
|
|
cmdline_size + 1);
|
2006-04-28 01:15:07 +02:00
|
|
|
cmdline_size = (cmdline_size >> 2) + 1;
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, cmdline_size + 2);
|
|
|
|
WRITE_WORD(p, 0x54410009);
|
|
|
|
p += cmdline_size * 4;
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|
2008-04-14 22:27:51 +02:00
|
|
|
if (info->atag_board) {
|
|
|
|
/* ATAG_BOARD */
|
|
|
|
int atag_board_len;
|
2009-04-09 19:19:47 +02:00
|
|
|
uint8_t atag_board_buf[0x1000];
|
2008-04-14 22:27:51 +02:00
|
|
|
|
2009-04-09 19:19:47 +02:00
|
|
|
atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
|
|
|
|
WRITE_WORD(p, (atag_board_len + 8) >> 2);
|
|
|
|
WRITE_WORD(p, 0x414f4d50);
|
|
|
|
cpu_physical_memory_write(p, atag_board_buf, atag_board_len);
|
2008-04-14 22:27:51 +02:00
|
|
|
p += atag_board_len;
|
|
|
|
}
|
2006-04-28 01:15:07 +02:00
|
|
|
/* ATAG_END */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
WRITE_WORD(p, 0);
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|
|
|
|
|
2012-01-29 08:52:15 +01:00
|
|
|
static void set_kernel_args_old(const struct arm_boot_info *info)
|
2007-07-28 00:08:46 +02:00
|
|
|
{
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr p;
|
2009-04-09 19:19:47 +02:00
|
|
|
const char *s;
|
2012-01-29 08:52:15 +01:00
|
|
|
int initrd_size = info->initrd_size;
|
2012-10-23 12:30:10 +02:00
|
|
|
hwaddr base = info->loader_start;
|
2007-07-28 00:08:46 +02:00
|
|
|
|
|
|
|
/* see linux/include/asm-arm/setup.h */
|
2009-04-09 19:19:47 +02:00
|
|
|
p = base + KERNEL_ARGS_ADDR;
|
2007-07-28 00:08:46 +02:00
|
|
|
/* page_size */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 4096);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* nr_pages */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, info->ram_size / 4096);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* ramdisk_size */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
#define FLAG_READONLY 1
|
|
|
|
#define FLAG_RDLOAD 4
|
|
|
|
#define FLAG_RDPROMPT 8
|
|
|
|
/* flags */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* rootdev */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
|
2007-07-28 00:08:46 +02:00
|
|
|
/* video_num_cols */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* video_num_rows */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* video_x */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* video_y */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* memc_control_reg */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* unsigned char sounddefault */
|
|
|
|
/* unsigned char adfsdrives */
|
|
|
|
/* unsigned char bytes_per_char_h */
|
|
|
|
/* unsigned char bytes_per_char_v */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* pages_in_bank[4] */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* pages_in_vram */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* initrd_start */
|
2012-10-26 17:29:38 +02:00
|
|
|
if (initrd_size) {
|
|
|
|
WRITE_WORD(p, info->initrd_start);
|
|
|
|
} else {
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2012-10-26 17:29:38 +02:00
|
|
|
}
|
2007-07-28 00:08:46 +02:00
|
|
|
/* initrd_size */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, initrd_size);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* rd_start */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* system_rev */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* system_serial_low */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* system_serial_high */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* mem_fclk_21285 */
|
2009-04-09 19:19:47 +02:00
|
|
|
WRITE_WORD(p, 0);
|
2007-07-28 00:08:46 +02:00
|
|
|
/* zero unused fields */
|
2009-04-09 19:19:47 +02:00
|
|
|
while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
|
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
}
|
|
|
|
s = info->kernel_cmdline;
|
|
|
|
if (s) {
|
2013-04-12 20:53:58 +02:00
|
|
|
cpu_physical_memory_write(p, s, strlen(s) + 1);
|
2009-04-09 19:19:47 +02:00
|
|
|
} else {
|
|
|
|
WRITE_WORD(p, 0);
|
|
|
|
}
|
2007-07-28 00:08:46 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo)
|
2012-03-02 12:56:38 +01:00
|
|
|
{
|
|
|
|
void *fdt = NULL;
|
|
|
|
int size, rc;
|
2013-07-16 14:25:06 +02:00
|
|
|
uint32_t acells, scells;
|
2012-03-02 12:56:38 +01:00
|
|
|
|
2013-11-22 18:17:10 +01:00
|
|
|
if (binfo->dtb_filename) {
|
|
|
|
char *filename;
|
|
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
|
|
|
|
if (!filename) {
|
|
|
|
fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
|
|
|
|
goto fail;
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
|
2013-11-22 18:17:10 +01:00
|
|
|
fdt = load_device_tree(filename, &size);
|
|
|
|
if (!fdt) {
|
|
|
|
fprintf(stderr, "Couldn't open dtb file %s\n", filename);
|
|
|
|
g_free(filename);
|
|
|
|
goto fail;
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
g_free(filename);
|
2013-11-22 18:17:10 +01:00
|
|
|
} else if (binfo->get_dtb) {
|
|
|
|
fdt = binfo->get_dtb(binfo, &size);
|
|
|
|
if (!fdt) {
|
|
|
|
fprintf(stderr, "Board was unable to create a dtb blob\n");
|
|
|
|
goto fail;
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
|
2013-11-11 09:14:41 +01:00
|
|
|
acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells");
|
|
|
|
scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells");
|
2012-07-20 14:34:50 +02:00
|
|
|
if (acells == 0 || scells == 0) {
|
|
|
|
fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-07-20 14:34:50 +02:00
|
|
|
}
|
|
|
|
|
2013-07-16 14:25:06 +02:00
|
|
|
if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
|
|
|
|
/* This is user error so deserves a friendlier error message
|
|
|
|
* than the failure of setprop_sized_cells would provide
|
|
|
|
*/
|
2012-07-20 14:34:50 +02:00
|
|
|
fprintf(stderr, "qemu: dtb file not compatible with "
|
|
|
|
"RAM size > 4GB\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-07-20 14:34:50 +02:00
|
|
|
}
|
|
|
|
|
2013-11-11 09:14:41 +01:00
|
|
|
rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
|
|
|
|
acells, binfo->loader_start,
|
|
|
|
scells, binfo->ram_size);
|
2012-03-02 12:56:38 +01:00
|
|
|
if (rc < 0) {
|
|
|
|
fprintf(stderr, "couldn't set /memory/reg\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
|
2012-06-17 17:35:36 +02:00
|
|
|
if (binfo->kernel_cmdline && *binfo->kernel_cmdline) {
|
2013-11-11 09:14:41 +01:00
|
|
|
rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
|
|
|
|
binfo->kernel_cmdline);
|
2012-06-17 17:35:36 +02:00
|
|
|
if (rc < 0) {
|
|
|
|
fprintf(stderr, "couldn't set /chosen/bootargs\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-06-17 17:35:36 +02:00
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (binfo->initrd_size) {
|
2013-11-11 09:14:41 +01:00
|
|
|
rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
|
|
|
|
binfo->initrd_start);
|
2012-03-02 12:56:38 +01:00
|
|
|
if (rc < 0) {
|
|
|
|
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
|
2013-11-11 09:14:41 +01:00
|
|
|
rc = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
|
|
|
|
binfo->initrd_start + binfo->initrd_size);
|
2012-03-02 12:56:38 +01:00
|
|
|
if (rc < 0) {
|
|
|
|
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
|
2013-06-25 19:34:13 +02:00
|
|
|
goto fail;
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
}
|
2013-07-16 14:25:10 +02:00
|
|
|
|
|
|
|
if (binfo->modify_dtb) {
|
|
|
|
binfo->modify_dtb(binfo, fdt);
|
|
|
|
}
|
|
|
|
|
2013-11-11 09:14:41 +01:00
|
|
|
qemu_fdt_dumpdtb(fdt, size);
|
2012-03-02 12:56:38 +01:00
|
|
|
|
|
|
|
cpu_physical_memory_write(addr, fdt, size);
|
|
|
|
|
2013-06-25 19:34:13 +02:00
|
|
|
g_free(fdt);
|
|
|
|
|
2012-03-02 12:56:38 +01:00
|
|
|
return 0;
|
2013-06-25 19:34:13 +02:00
|
|
|
|
|
|
|
fail:
|
|
|
|
g_free(fdt);
|
|
|
|
return -1;
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
|
|
|
|
2011-03-05 13:51:45 +01:00
|
|
|
static void do_cpu_reset(void *opaque)
|
2009-11-11 19:07:53 +01:00
|
|
|
{
|
2012-05-05 12:40:39 +02:00
|
|
|
ARMCPU *cpu = opaque;
|
|
|
|
CPUARMState *env = &cpu->env;
|
2011-06-23 17:53:48 +02:00
|
|
|
const struct arm_boot_info *info = env->boot_info;
|
2009-11-11 19:07:53 +01:00
|
|
|
|
2012-05-05 12:40:39 +02:00
|
|
|
cpu_reset(CPU(cpu));
|
2009-11-11 19:07:53 +01:00
|
|
|
if (info) {
|
|
|
|
if (!info->is_linux) {
|
|
|
|
/* Jump to the entry point. */
|
|
|
|
env->regs[15] = info->entry & 0xfffffffe;
|
|
|
|
env->thumb = info->entry & 1;
|
|
|
|
} else {
|
2013-05-29 22:29:20 +02:00
|
|
|
if (CPU(cpu) == first_cpu) {
|
2013-12-17 20:42:30 +01:00
|
|
|
if (env->aarch64) {
|
|
|
|
env->pc = info->loader_start;
|
|
|
|
} else {
|
|
|
|
env->regs[15] = info->loader_start;
|
|
|
|
}
|
|
|
|
|
2014-01-31 15:47:32 +01:00
|
|
|
if (!have_dtb(info)) {
|
2012-03-02 12:56:38 +01:00
|
|
|
if (old_param) {
|
|
|
|
set_kernel_args_old(info);
|
|
|
|
} else {
|
|
|
|
set_kernel_args(info);
|
|
|
|
}
|
2011-03-05 13:51:45 +01:00
|
|
|
}
|
2009-11-11 19:07:53 +01:00
|
|
|
} else {
|
2012-05-14 01:05:40 +02:00
|
|
|
info->secondary_cpu_reset_hook(cpu, info);
|
2009-11-11 19:07:53 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-05-14 02:39:57 +02:00
|
|
|
void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
|
2006-04-28 01:15:07 +02:00
|
|
|
{
|
2013-05-29 22:29:20 +02:00
|
|
|
CPUState *cs = CPU(cpu);
|
2006-04-28 01:15:07 +02:00
|
|
|
int kernel_size;
|
|
|
|
int initrd_size;
|
2007-03-07 00:52:01 +01:00
|
|
|
int is_linux = 0;
|
|
|
|
uint64_t elf_entry;
|
2014-03-21 19:44:36 +01:00
|
|
|
int elf_machine;
|
2013-12-17 20:42:30 +01:00
|
|
|
hwaddr entry, kernel_load_offset;
|
2009-09-20 16:58:02 +02:00
|
|
|
int big_endian;
|
2013-12-17 20:42:30 +01:00
|
|
|
static const ARMInsnFixup *primary_loader;
|
2006-04-28 01:15:07 +02:00
|
|
|
|
|
|
|
/* Load the kernel. */
|
2008-04-14 22:27:51 +02:00
|
|
|
if (!info->kernel_filename) {
|
2013-10-25 16:44:38 +02:00
|
|
|
/* If no kernel specified, do nothing; we will start from address 0
|
|
|
|
* (typically a boot ROM image) in the same way as hardware.
|
|
|
|
*/
|
|
|
|
return;
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|
2007-01-16 19:54:31 +01:00
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
|
|
primary_loader = bootloader_aarch64;
|
|
|
|
kernel_load_offset = KERNEL64_LOAD_ADDR;
|
2014-03-21 19:44:36 +01:00
|
|
|
elf_machine = EM_AARCH64;
|
2013-12-17 20:42:30 +01:00
|
|
|
} else {
|
|
|
|
primary_loader = bootloader;
|
|
|
|
kernel_load_offset = KERNEL_LOAD_ADDR;
|
2014-03-21 19:44:36 +01:00
|
|
|
elf_machine = EM_ARM;
|
2013-12-17 20:42:30 +01:00
|
|
|
}
|
|
|
|
|
2013-07-04 15:09:22 +02:00
|
|
|
info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
|
2012-03-02 12:56:38 +01:00
|
|
|
|
2012-01-26 12:43:48 +01:00
|
|
|
if (!info->secondary_cpu_reset_hook) {
|
|
|
|
info->secondary_cpu_reset_hook = default_reset_secondary;
|
|
|
|
}
|
|
|
|
if (!info->write_secondary_boot) {
|
|
|
|
info->write_secondary_boot = default_write_secondary;
|
|
|
|
}
|
|
|
|
|
2009-11-11 19:07:53 +01:00
|
|
|
if (info->nb_cpus == 0)
|
|
|
|
info->nb_cpus = 1;
|
2008-04-14 22:27:51 +02:00
|
|
|
|
2009-09-20 16:58:02 +02:00
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
|
|
big_endian = 1;
|
|
|
|
#else
|
|
|
|
big_endian = 0;
|
|
|
|
#endif
|
|
|
|
|
2012-10-26 17:29:38 +02:00
|
|
|
/* We want to put the initrd far enough into RAM that when the
|
|
|
|
* kernel is uncompressed it will not clobber the initrd. However
|
|
|
|
* on boards without much RAM we must ensure that we still leave
|
|
|
|
* enough room for a decent sized initrd, and on boards with large
|
|
|
|
* amounts of RAM we must avoid the initrd being so far up in RAM
|
|
|
|
* that it is outside lowmem and inaccessible to the kernel.
|
|
|
|
* So for boards with less than 256MB of RAM we put the initrd
|
|
|
|
* halfway into RAM, and for boards with 256MB of RAM or more we put
|
|
|
|
* the initrd at 128MB.
|
|
|
|
*/
|
|
|
|
info->initrd_start = info->loader_start +
|
|
|
|
MIN(info->ram_size / 2, 128 * 1024 * 1024);
|
|
|
|
|
2007-03-07 00:52:01 +01:00
|
|
|
/* Assume that raw images are linux kernels, and ELF images are not. */
|
2010-03-14 21:20:59 +01:00
|
|
|
kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
|
2014-03-21 19:44:36 +01:00
|
|
|
NULL, NULL, big_endian, elf_machine, 1);
|
2007-03-07 00:52:01 +01:00
|
|
|
entry = elf_entry;
|
|
|
|
if (kernel_size < 0) {
|
2008-11-20 23:14:40 +01:00
|
|
|
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
|
|
|
|
&is_linux);
|
2007-03-07 00:52:01 +01:00
|
|
|
}
|
|
|
|
if (kernel_size < 0) {
|
2013-12-17 20:42:30 +01:00
|
|
|
entry = info->loader_start + kernel_load_offset;
|
2009-04-09 19:30:32 +02:00
|
|
|
kernel_size = load_image_targphys(info->kernel_filename, entry,
|
2013-12-17 20:42:30 +01:00
|
|
|
info->ram_size - kernel_load_offset);
|
2007-03-07 00:52:01 +01:00
|
|
|
is_linux = 1;
|
|
|
|
}
|
|
|
|
if (kernel_size < 0) {
|
2008-04-14 22:27:51 +02:00
|
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
|
|
|
info->kernel_filename);
|
2007-03-07 00:52:01 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
2009-11-11 19:07:53 +01:00
|
|
|
info->entry = entry;
|
|
|
|
if (is_linux) {
|
2013-12-17 20:42:30 +01:00
|
|
|
uint32_t fixupcontext[FIXUP_MAX];
|
|
|
|
|
2008-04-14 22:27:51 +02:00
|
|
|
if (info->initrd_filename) {
|
2013-07-09 00:40:02 +02:00
|
|
|
initrd_size = load_ramdisk(info->initrd_filename,
|
|
|
|
info->initrd_start,
|
|
|
|
info->ram_size -
|
|
|
|
info->initrd_start);
|
|
|
|
if (initrd_size < 0) {
|
|
|
|
initrd_size = load_image_targphys(info->initrd_filename,
|
|
|
|
info->initrd_start,
|
|
|
|
info->ram_size -
|
|
|
|
info->initrd_start);
|
|
|
|
}
|
2007-01-16 19:54:31 +01:00
|
|
|
if (initrd_size < 0) {
|
|
|
|
fprintf(stderr, "qemu: could not load initrd '%s'\n",
|
2008-04-14 22:27:51 +02:00
|
|
|
info->initrd_filename);
|
2007-01-16 19:54:31 +01:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
initrd_size = 0;
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
info->initrd_size = initrd_size;
|
|
|
|
|
2013-12-17 20:42:30 +01:00
|
|
|
fixupcontext[FIXUP_BOARDID] = info->board_id;
|
2012-03-02 12:56:38 +01:00
|
|
|
|
|
|
|
/* for device tree boot, we pass the DTB directly in r2. Otherwise
|
|
|
|
* we point to the kernel args.
|
|
|
|
*/
|
2014-01-31 15:47:32 +01:00
|
|
|
if (have_dtb(info)) {
|
2013-01-24 20:02:28 +01:00
|
|
|
/* Place the DTB after the initrd in memory. Note that some
|
|
|
|
* kernels will trash anything in the 4K page the initrd
|
|
|
|
* ends in, so make sure the DTB isn't caught up in that.
|
|
|
|
*/
|
|
|
|
hwaddr dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
|
|
|
|
4096);
|
2012-03-02 12:56:38 +01:00
|
|
|
if (load_dtb(dtb_start, info)) {
|
|
|
|
exit(1);
|
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
fixupcontext[FIXUP_ARGPTR] = dtb_start;
|
2012-03-02 12:56:38 +01:00
|
|
|
} else {
|
2013-12-17 20:42:30 +01:00
|
|
|
fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
|
2012-07-20 14:34:50 +02:00
|
|
|
if (info->ram_size >= (1ULL << 32)) {
|
|
|
|
fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
|
|
|
|
" Linux kernel using ATAGS (try passing a device tree"
|
|
|
|
" using -dtb)\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2012-03-02 12:56:38 +01:00
|
|
|
}
|
2013-12-17 20:42:30 +01:00
|
|
|
fixupcontext[FIXUP_ENTRYPOINT] = entry;
|
|
|
|
|
|
|
|
write_bootloader("bootloader", info->loader_start,
|
2013-12-17 20:42:30 +01:00
|
|
|
primary_loader, fixupcontext);
|
2013-12-17 20:42:30 +01:00
|
|
|
|
2009-04-09 19:19:47 +02:00
|
|
|
if (info->nb_cpus > 1) {
|
2012-05-14 00:08:10 +02:00
|
|
|
info->write_secondary_boot(cpu, info);
|
2009-04-09 19:19:47 +02:00
|
|
|
}
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|
2009-11-11 19:07:53 +01:00
|
|
|
info->is_linux = is_linux;
|
2011-03-05 13:51:45 +01:00
|
|
|
|
2013-06-24 23:50:24 +02:00
|
|
|
for (; cs; cs = CPU_NEXT(cs)) {
|
2013-05-29 22:29:20 +02:00
|
|
|
cpu = ARM_CPU(cs);
|
|
|
|
cpu->env.boot_info = info;
|
2012-05-05 12:40:39 +02:00
|
|
|
qemu_register_reset(do_cpu_reset, cpu);
|
2011-03-05 13:51:45 +01:00
|
|
|
}
|
2006-04-28 01:15:07 +02:00
|
|
|
}
|