2007-04-02 03:10:46 +02:00
|
|
|
/*
|
|
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|
* QEMU VMware-SVGA "chipset".
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*
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* Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
|
2016-01-26 19:17:13 +01:00
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#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2013-02-04 15:40:22 +01:00
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|
|
#include "hw/hw.h"
|
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|
|
#include "hw/loader.h"
|
2013-11-10 14:20:16 +01:00
|
|
|
#include "trace.h"
|
2012-11-28 12:06:30 +01:00
|
|
|
#include "ui/console.h"
|
2014-03-17 18:38:58 +01:00
|
|
|
#include "ui/vnc.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/pci/pci.h"
|
2007-04-02 03:10:46 +02:00
|
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|
|
2011-08-22 19:12:09 +02:00
|
|
|
#undef VERBOSE
|
2007-04-02 03:10:46 +02:00
|
|
|
#define HW_RECT_ACCEL
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|
|
#define HW_FILL_ACCEL
|
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|
|
#define HW_MOUSE_ACCEL
|
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|
|
2013-03-18 17:36:02 +01:00
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|
#include "vga_int.h"
|
2012-11-03 12:47:08 +01:00
|
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|
|
/* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
struct vmsvga_state_s {
|
2009-05-03 21:25:16 +02:00
|
|
|
VGACommonState vga;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
int invalidated;
|
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|
|
int enable;
|
|
|
|
int config;
|
|
|
|
struct {
|
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|
|
int id;
|
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|
|
int x;
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|
|
int y;
|
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|
|
int on;
|
|
|
|
} cursor;
|
|
|
|
|
|
|
|
int index;
|
|
|
|
int scratch_size;
|
|
|
|
uint32_t *scratch;
|
|
|
|
int new_width;
|
|
|
|
int new_height;
|
2013-03-25 11:44:21 +01:00
|
|
|
int new_depth;
|
2007-04-02 03:10:46 +02:00
|
|
|
uint32_t guest;
|
|
|
|
uint32_t svgaid;
|
|
|
|
int syncing;
|
|
|
|
|
2011-08-08 15:08:57 +02:00
|
|
|
MemoryRegion fifo_ram;
|
2009-12-17 23:08:06 +01:00
|
|
|
uint8_t *fifo_ptr;
|
|
|
|
unsigned int fifo_size;
|
|
|
|
|
2016-05-30 09:09:20 +02:00
|
|
|
uint32_t *fifo;
|
|
|
|
uint32_t fifo_min;
|
|
|
|
uint32_t fifo_max;
|
|
|
|
uint32_t fifo_next;
|
|
|
|
uint32_t fifo_stop;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define REDRAW_FIFO_LEN 512
|
2007-04-02 03:10:46 +02:00
|
|
|
struct vmsvga_rect_s {
|
|
|
|
int x, y, w, h;
|
|
|
|
} redraw_fifo[REDRAW_FIFO_LEN];
|
|
|
|
int redraw_fifo_first, redraw_fifo_last;
|
|
|
|
};
|
|
|
|
|
2013-06-24 08:58:45 +02:00
|
|
|
#define TYPE_VMWARE_SVGA "vmware-svga"
|
|
|
|
|
|
|
|
#define VMWARE_SVGA(obj) \
|
|
|
|
OBJECT_CHECK(struct pci_vmsvga_state_s, (obj), TYPE_VMWARE_SVGA)
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
struct pci_vmsvga_state_s {
|
2013-06-30 15:01:36 +02:00
|
|
|
/*< private >*/
|
|
|
|
PCIDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
struct vmsvga_state_s chip;
|
2011-08-08 15:08:57 +02:00
|
|
|
MemoryRegion io_bar;
|
2007-04-02 03:10:46 +02:00
|
|
|
};
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_MAGIC 0x900000UL
|
|
|
|
#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
|
|
|
|
#define SVGA_ID_0 SVGA_MAKE_ID(0)
|
|
|
|
#define SVGA_ID_1 SVGA_MAKE_ID(1)
|
|
|
|
#define SVGA_ID_2 SVGA_MAKE_ID(2)
|
2007-04-02 03:10:46 +02:00
|
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|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_LEGACY_BASE_PORT 0x4560
|
|
|
|
#define SVGA_INDEX_PORT 0x0
|
|
|
|
#define SVGA_VALUE_PORT 0x1
|
|
|
|
#define SVGA_BIOS_PORT 0x2
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
#define SVGA_VERSION_2
|
|
|
|
|
|
|
|
#ifdef SVGA_VERSION_2
|
2012-11-03 12:47:08 +01:00
|
|
|
# define SVGA_ID SVGA_ID_2
|
|
|
|
# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
|
|
|
|
# define SVGA_IO_MUL 1
|
|
|
|
# define SVGA_FIFO_SIZE 0x10000
|
|
|
|
# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
|
2007-04-02 03:10:46 +02:00
|
|
|
#else
|
2012-11-03 12:47:08 +01:00
|
|
|
# define SVGA_ID SVGA_ID_1
|
|
|
|
# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
|
|
|
|
# define SVGA_IO_MUL 4
|
|
|
|
# define SVGA_FIFO_SIZE 0x10000
|
|
|
|
# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
|
2007-04-02 03:10:46 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
enum {
|
|
|
|
/* ID 0, 1 and 2 registers */
|
|
|
|
SVGA_REG_ID = 0,
|
|
|
|
SVGA_REG_ENABLE = 1,
|
|
|
|
SVGA_REG_WIDTH = 2,
|
|
|
|
SVGA_REG_HEIGHT = 3,
|
|
|
|
SVGA_REG_MAX_WIDTH = 4,
|
|
|
|
SVGA_REG_MAX_HEIGHT = 5,
|
|
|
|
SVGA_REG_DEPTH = 6,
|
2012-11-03 12:47:08 +01:00
|
|
|
SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
|
2007-04-02 03:10:46 +02:00
|
|
|
SVGA_REG_PSEUDOCOLOR = 8,
|
|
|
|
SVGA_REG_RED_MASK = 9,
|
|
|
|
SVGA_REG_GREEN_MASK = 10,
|
|
|
|
SVGA_REG_BLUE_MASK = 11,
|
|
|
|
SVGA_REG_BYTES_PER_LINE = 12,
|
|
|
|
SVGA_REG_FB_START = 13,
|
|
|
|
SVGA_REG_FB_OFFSET = 14,
|
|
|
|
SVGA_REG_VRAM_SIZE = 15,
|
|
|
|
SVGA_REG_FB_SIZE = 16,
|
|
|
|
|
|
|
|
/* ID 1 and 2 registers */
|
|
|
|
SVGA_REG_CAPABILITIES = 17,
|
2012-11-03 12:47:08 +01:00
|
|
|
SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
|
2007-04-02 03:10:46 +02:00
|
|
|
SVGA_REG_MEM_SIZE = 19,
|
2012-11-03 12:47:08 +01:00
|
|
|
SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
|
|
|
|
SVGA_REG_SYNC = 21, /* Write to force synchronization */
|
|
|
|
SVGA_REG_BUSY = 22, /* Read to check if sync is done */
|
|
|
|
SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
|
|
|
|
SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
|
|
|
|
SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
|
|
|
|
SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
|
|
|
|
SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
|
|
|
|
SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
|
|
|
|
SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
|
|
|
|
SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
|
|
|
|
SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
|
|
|
|
SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
|
|
|
|
|
|
|
|
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
|
2007-04-02 03:10:46 +02:00
|
|
|
SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
|
|
|
|
SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
|
|
|
|
};
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_CAP_NONE 0
|
|
|
|
#define SVGA_CAP_RECT_FILL (1 << 0)
|
|
|
|
#define SVGA_CAP_RECT_COPY (1 << 1)
|
|
|
|
#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
|
|
|
|
#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
|
|
|
|
#define SVGA_CAP_RASTER_OP (1 << 4)
|
|
|
|
#define SVGA_CAP_CURSOR (1 << 5)
|
|
|
|
#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
|
|
|
|
#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
|
|
|
|
#define SVGA_CAP_8BIT_EMULATION (1 << 8)
|
|
|
|
#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
|
|
|
|
#define SVGA_CAP_GLYPH (1 << 10)
|
|
|
|
#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
|
|
|
|
#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
|
|
|
|
#define SVGA_CAP_ALPHA_BLEND (1 << 13)
|
|
|
|
#define SVGA_CAP_3D (1 << 14)
|
|
|
|
#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
|
|
|
|
#define SVGA_CAP_MULTIMON (1 << 16)
|
|
|
|
#define SVGA_CAP_PITCHLOCK (1 << 17)
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* FIFO offsets (seen as an array of 32-bit words)
|
|
|
|
*/
|
|
|
|
enum {
|
|
|
|
/*
|
|
|
|
* The original defined FIFO offsets
|
|
|
|
*/
|
|
|
|
SVGA_FIFO_MIN = 0,
|
2012-11-03 12:47:08 +01:00
|
|
|
SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
|
2016-05-30 09:09:20 +02:00
|
|
|
SVGA_FIFO_NEXT,
|
2007-04-02 03:10:46 +02:00
|
|
|
SVGA_FIFO_STOP,
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
|
|
|
|
*/
|
|
|
|
SVGA_FIFO_CAPABILITIES = 4,
|
|
|
|
SVGA_FIFO_FLAGS,
|
|
|
|
SVGA_FIFO_FENCE,
|
|
|
|
SVGA_FIFO_3D_HWVERSION,
|
|
|
|
SVGA_FIFO_PITCHLOCK,
|
|
|
|
};
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_FIFO_CAP_NONE 0
|
|
|
|
#define SVGA_FIFO_CAP_FENCE (1 << 0)
|
|
|
|
#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
|
|
|
|
#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_FIFO_FLAG_NONE 0
|
|
|
|
#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
/* These values can probably be changed arbitrarily. */
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_SCRATCH_SIZE 0x8000
|
2014-03-17 18:38:58 +01:00
|
|
|
#define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_MAX_HEIGHT 1770
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
#ifdef VERBOSE
|
2012-11-03 12:47:08 +01:00
|
|
|
# define GUEST_OS_BASE 0x5001
|
2007-04-02 03:10:46 +02:00
|
|
|
static const char *vmsvga_guest_id[] = {
|
2007-05-13 15:26:49 +02:00
|
|
|
[0x00] = "Dos",
|
|
|
|
[0x01] = "Windows 3.1",
|
|
|
|
[0x02] = "Windows 95",
|
|
|
|
[0x03] = "Windows 98",
|
|
|
|
[0x04] = "Windows ME",
|
|
|
|
[0x05] = "Windows NT",
|
|
|
|
[0x06] = "Windows 2000",
|
|
|
|
[0x07] = "Linux",
|
|
|
|
[0x08] = "OS/2",
|
2009-03-07 16:32:56 +01:00
|
|
|
[0x09] = "an unknown OS",
|
2007-05-13 15:26:49 +02:00
|
|
|
[0x0a] = "BSD",
|
|
|
|
[0x0b] = "Whistler",
|
2009-03-07 16:32:56 +01:00
|
|
|
[0x0c] = "an unknown OS",
|
|
|
|
[0x0d] = "an unknown OS",
|
|
|
|
[0x0e] = "an unknown OS",
|
|
|
|
[0x0f] = "an unknown OS",
|
|
|
|
[0x10] = "an unknown OS",
|
|
|
|
[0x11] = "an unknown OS",
|
|
|
|
[0x12] = "an unknown OS",
|
|
|
|
[0x13] = "an unknown OS",
|
|
|
|
[0x14] = "an unknown OS",
|
2007-05-13 15:26:49 +02:00
|
|
|
[0x15] = "Windows 2003",
|
2007-04-02 03:10:46 +02:00
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
enum {
|
|
|
|
SVGA_CMD_INVALID_CMD = 0,
|
|
|
|
SVGA_CMD_UPDATE = 1,
|
|
|
|
SVGA_CMD_RECT_FILL = 2,
|
|
|
|
SVGA_CMD_RECT_COPY = 3,
|
|
|
|
SVGA_CMD_DEFINE_BITMAP = 4,
|
|
|
|
SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
|
|
|
|
SVGA_CMD_DEFINE_PIXMAP = 6,
|
|
|
|
SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
|
|
|
|
SVGA_CMD_RECT_BITMAP_FILL = 8,
|
|
|
|
SVGA_CMD_RECT_PIXMAP_FILL = 9,
|
|
|
|
SVGA_CMD_RECT_BITMAP_COPY = 10,
|
|
|
|
SVGA_CMD_RECT_PIXMAP_COPY = 11,
|
|
|
|
SVGA_CMD_FREE_OBJECT = 12,
|
|
|
|
SVGA_CMD_RECT_ROP_FILL = 13,
|
|
|
|
SVGA_CMD_RECT_ROP_COPY = 14,
|
|
|
|
SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
|
|
|
|
SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
|
|
|
|
SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
|
|
|
|
SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
|
|
|
|
SVGA_CMD_DEFINE_CURSOR = 19,
|
|
|
|
SVGA_CMD_DISPLAY_CURSOR = 20,
|
|
|
|
SVGA_CMD_MOVE_CURSOR = 21,
|
|
|
|
SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
|
|
|
|
SVGA_CMD_DRAW_GLYPH = 23,
|
|
|
|
SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
|
|
|
|
SVGA_CMD_UPDATE_VERBOSE = 25,
|
|
|
|
SVGA_CMD_SURFACE_FILL = 26,
|
|
|
|
SVGA_CMD_SURFACE_COPY = 27,
|
|
|
|
SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
|
|
|
|
SVGA_CMD_FRONT_ROP_FILL = 29,
|
|
|
|
SVGA_CMD_FENCE = 30,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
|
|
|
|
enum {
|
|
|
|
SVGA_CURSOR_ON_HIDE = 0,
|
|
|
|
SVGA_CURSOR_ON_SHOW = 1,
|
|
|
|
SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
|
|
|
|
SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
|
|
|
|
};
|
|
|
|
|
2014-10-06 11:51:54 +02:00
|
|
|
static inline bool vmsvga_verify_rect(DisplaySurface *surface,
|
|
|
|
const char *name,
|
|
|
|
int x, int y, int w, int h)
|
|
|
|
{
|
|
|
|
if (x < 0) {
|
|
|
|
fprintf(stderr, "%s: x was < 0 (%d)\n", name, x);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (x > SVGA_MAX_WIDTH) {
|
|
|
|
fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (w < 0) {
|
|
|
|
fprintf(stderr, "%s: w was < 0 (%d)\n", name, w);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (w > SVGA_MAX_WIDTH) {
|
|
|
|
fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (x + w > surface_width(surface)) {
|
|
|
|
fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n",
|
|
|
|
name, surface_width(surface), x, w);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (y < 0) {
|
|
|
|
fprintf(stderr, "%s: y was < 0 (%d)\n", name, y);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (y > SVGA_MAX_HEIGHT) {
|
|
|
|
fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (h < 0) {
|
|
|
|
fprintf(stderr, "%s: h was < 0 (%d)\n", name, h);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (h > SVGA_MAX_HEIGHT) {
|
|
|
|
fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
if (y + h > surface_height(surface)) {
|
|
|
|
fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n",
|
|
|
|
name, surface_height(surface), y, h);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
|
2014-10-06 11:51:54 +02:00
|
|
|
int x, int y, int w, int h)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->vga.con);
|
2008-03-06 21:43:34 +01:00
|
|
|
int line;
|
|
|
|
int bypl;
|
|
|
|
int width;
|
|
|
|
int start;
|
|
|
|
uint8_t *src;
|
|
|
|
uint8_t *dst;
|
|
|
|
|
2014-10-06 11:58:22 +02:00
|
|
|
if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
|
|
|
|
/* go for a fullscreen update as fallback */
|
vmware_vga: fix out of bounds and invalid rects updating
This is a follow up for several attempts to fix this issue.
Previous incarnations:
1. http://thread.gmane.org/gmane.linux.ubuntu.bugs.general/3156089
https://bugs.launchpad.net/bugs/918791
"qemu-kvm dies when using vmvga driver and unity in the guest" bug.
Fix by Serge Hallyn:
https://launchpadlibrarian.net/94916786/qemu-vmware.debdiff
This fix is incomplete, since it does not check width and height
for being negative. Serge weren't sure if that's the right place
to fix it, maybe the fix should be up the stack somewhere.
2. http://thread.gmane.org/gmane.comp.emulators.qemu/166064
by Marek Vasut: "vmware_vga: Redraw only visible area"
This one adds the (incomplete) check to vmsvga_update_rect_delayed(),
the routine just queues the rect updating but does no interesting
stuff. It is also incomplete in the same way as patch by Serge,
but also does not touch width&height at all after adjusting x&y,
which is wrong.
As far as I can see, when processing guest requests, the device
places them into a queue (vmsvga_update_rect_delayed()) and
processes this queue in different place/time, namely, in
vmsvga_update_rect(). Sometimes, vmsvga_update_rect() is
called directly, without placing the request to the gueue.
This is the place this patch changes, which is the last
(deepest) in the stack. I'm not sure if this is the right
place still, since it is possible we have some queue optimization
(or may have in the future) which will be upset by negative/wrong
values here, so maybe we should check for validity of input
right when receiving request from the guest (and maybe even
use unsigned types there). But I don't know the protocol
and implementation enough to have a definitive answer.
But since vmsvga_update_rect() has other sanity checks already,
I'm adding the missing ones there as well.
Cc'ing BALATON Zoltan and Andrzej Zaborowski who shows in `git blame'
output and may know something in this area.
If this patch is accepted, it should be applied to all active
stable branches (at least since 1.1, maybe even before), with
minor context change (ds_get_*(s->vga.ds) => s->*). I'm not
Cc'ing -stable yet, will do it explicitly once the patch is
accepted.
BTW, these checks use fprintf(stderr) -- it should be converted
to something more appropriate, since stderr will most likely
disappear somewhere.
Cc: Marek Vasut <marex@denx.de>
CC: Serge Hallyn <serge.hallyn@ubuntu.com>
Cc: BALATON Zoltan <balaton@eik.bme.hu>
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Serge Hallyn <serge.hallyn@ubuntu.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-01-25 18:23:24 +01:00
|
|
|
x = 0;
|
|
|
|
y = 0;
|
2014-10-06 11:58:22 +02:00
|
|
|
w = surface_width(surface);
|
|
|
|
h = surface_height(surface);
|
2008-03-06 21:43:34 +01:00
|
|
|
}
|
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
bypl = surface_stride(surface);
|
|
|
|
width = surface_bytes_per_pixel(surface) * w;
|
|
|
|
start = surface_bytes_per_pixel(surface) * x + bypl * y;
|
2009-05-03 21:25:16 +02:00
|
|
|
src = s->vga.vram_ptr + start;
|
2013-03-05 15:24:14 +01:00
|
|
|
dst = surface_data(surface) + start;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
for (line = h; line > 0; line--, src += bypl, dst += bypl) {
|
2007-04-02 03:10:46 +02:00
|
|
|
memcpy(dst, src, width);
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(s->vga.con, x, y, w, h);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
|
|
|
|
int x, int y, int w, int h)
|
|
|
|
{
|
2012-11-03 12:47:08 +01:00
|
|
|
struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
|
|
|
|
rect->x = x;
|
|
|
|
rect->y = y;
|
|
|
|
rect->w = w;
|
|
|
|
rect->h = h;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
|
|
|
|
{
|
|
|
|
struct vmsvga_rect_s *rect;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
if (s->invalidated) {
|
|
|
|
s->redraw_fifo_first = s->redraw_fifo_last;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
/* Overlapping region updates can be optimised out here - if someone
|
|
|
|
* knows a smart algorithm to do that, please share. */
|
|
|
|
while (s->redraw_fifo_first != s->redraw_fifo_last) {
|
2012-11-03 12:47:08 +01:00
|
|
|
rect = &s->redraw_fifo[s->redraw_fifo_first++];
|
2007-04-02 03:10:46 +02:00
|
|
|
s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
|
|
|
|
vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef HW_RECT_ACCEL
|
2014-10-06 11:58:51 +02:00
|
|
|
static inline int vmsvga_copy_rect(struct vmsvga_state_s *s,
|
2007-04-02 03:10:46 +02:00
|
|
|
int x0, int y0, int x1, int y1, int w, int h)
|
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->vga.con);
|
2009-05-03 21:25:16 +02:00
|
|
|
uint8_t *vram = s->vga.vram_ptr;
|
2013-03-05 15:24:14 +01:00
|
|
|
int bypl = surface_stride(surface);
|
|
|
|
int bypp = surface_bytes_per_pixel(surface);
|
2012-11-03 12:47:08 +01:00
|
|
|
int width = bypp * w;
|
2007-04-02 03:10:46 +02:00
|
|
|
int line = h;
|
|
|
|
uint8_t *ptr[2];
|
|
|
|
|
2014-10-06 11:58:51 +02:00
|
|
|
if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2011-08-22 19:12:10 +02:00
|
|
|
if (y1 > y0) {
|
2012-11-03 12:47:08 +01:00
|
|
|
ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
|
|
|
|
ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
|
2011-08-22 19:12:10 +02:00
|
|
|
for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
|
|
|
|
memmove(ptr[1], ptr[0], width);
|
|
|
|
}
|
|
|
|
} else {
|
2012-11-03 12:47:08 +01:00
|
|
|
ptr[0] = vram + bypp * x0 + bypl * y0;
|
|
|
|
ptr[1] = vram + bypp * x1 + bypl * y1;
|
2011-08-22 19:12:10 +02:00
|
|
|
for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
|
|
|
|
memmove(ptr[1], ptr[0], width);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
vmsvga_update_rect_delayed(s, x1, y1, w, h);
|
2014-10-06 11:58:51 +02:00
|
|
|
return 0;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef HW_FILL_ACCEL
|
2014-10-06 11:59:51 +02:00
|
|
|
static inline int vmsvga_fill_rect(struct vmsvga_state_s *s,
|
2007-04-02 03:10:46 +02:00
|
|
|
uint32_t c, int x, int y, int w, int h)
|
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->vga.con);
|
|
|
|
int bypl = surface_stride(surface);
|
|
|
|
int width = surface_bytes_per_pixel(surface) * w;
|
2007-04-02 03:10:46 +02:00
|
|
|
int line = h;
|
|
|
|
int column;
|
2012-11-03 12:47:08 +01:00
|
|
|
uint8_t *fst;
|
2007-04-02 03:10:46 +02:00
|
|
|
uint8_t *dst;
|
|
|
|
uint8_t *src;
|
|
|
|
uint8_t col[4];
|
|
|
|
|
2014-10-06 11:59:51 +02:00
|
|
|
if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2011-08-22 19:12:10 +02:00
|
|
|
col[0] = c;
|
|
|
|
col[1] = c >> 8;
|
|
|
|
col[2] = c >> 16;
|
|
|
|
col[3] = c >> 24;
|
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2011-08-22 19:12:10 +02:00
|
|
|
if (line--) {
|
|
|
|
dst = fst;
|
|
|
|
src = col;
|
|
|
|
for (column = width; column > 0; column--) {
|
|
|
|
*(dst++) = *(src++);
|
2013-03-05 15:24:14 +01:00
|
|
|
if (src - col == surface_bytes_per_pixel(surface)) {
|
2011-08-22 19:12:10 +02:00
|
|
|
src = col;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
}
|
2011-08-22 19:12:10 +02:00
|
|
|
dst = fst;
|
|
|
|
for (; line > 0; line--) {
|
|
|
|
dst += bypl;
|
|
|
|
memcpy(dst, fst, width);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
vmsvga_update_rect_delayed(s, x, y, w, h);
|
2014-10-06 11:59:51 +02:00
|
|
|
return 0;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
struct vmsvga_cursor_definition_s {
|
2015-09-29 09:58:05 +02:00
|
|
|
uint32_t width;
|
|
|
|
uint32_t height;
|
2007-04-02 03:10:46 +02:00
|
|
|
int id;
|
2015-09-29 09:58:05 +02:00
|
|
|
uint32_t bpp;
|
2007-04-02 03:10:46 +02:00
|
|
|
int hot_x;
|
|
|
|
int hot_y;
|
|
|
|
uint32_t mask[1024];
|
2009-12-17 23:08:11 +01:00
|
|
|
uint32_t image[4096];
|
2007-04-02 03:10:46 +02:00
|
|
|
};
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
|
|
|
|
#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
#ifdef HW_MOUSE_ACCEL
|
|
|
|
static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
|
|
|
|
struct vmsvga_cursor_definition_s *c)
|
|
|
|
{
|
2010-05-21 11:54:33 +02:00
|
|
|
QEMUCursor *qc;
|
|
|
|
int i, pixels;
|
|
|
|
|
|
|
|
qc = cursor_alloc(c->width, c->height);
|
|
|
|
qc->hot_x = c->hot_x;
|
|
|
|
qc->hot_y = c->hot_y;
|
|
|
|
switch (c->bpp) {
|
|
|
|
case 1:
|
2012-11-03 12:47:08 +01:00
|
|
|
cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
|
|
|
|
1, (void *)c->mask);
|
2010-05-21 11:54:33 +02:00
|
|
|
#ifdef DEBUG
|
|
|
|
cursor_print_ascii_art(qc, "vmware/mono");
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
/* fill alpha channel from mask, set color to zero */
|
2012-11-03 12:47:08 +01:00
|
|
|
cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
|
|
|
|
1, (void *)c->mask);
|
2010-05-21 11:54:33 +02:00
|
|
|
/* add in rgb values */
|
|
|
|
pixels = c->width * c->height;
|
|
|
|
for (i = 0; i < pixels; i++) {
|
|
|
|
qc->data[i] |= c->image[i] & 0xffffff;
|
|
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
|
|
cursor_print_ascii_art(qc, "vmware/32bit");
|
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
2012-11-03 12:47:08 +01:00
|
|
|
__func__, c->bpp);
|
2010-05-21 11:54:33 +02:00
|
|
|
cursor_put(qc);
|
|
|
|
qc = cursor_builtin_left_ptr();
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_cursor_define(s->vga.con, qc);
|
2010-05-21 11:54:33 +02:00
|
|
|
cursor_put(qc);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-09-10 02:23:31 +02:00
|
|
|
static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2010-09-10 02:23:31 +02:00
|
|
|
int num;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
|
|
|
if (!s->config || !s->enable) {
|
2010-09-10 02:23:31 +02:00
|
|
|
return 0;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2016-05-30 09:09:18 +02:00
|
|
|
|
2016-05-30 09:09:20 +02:00
|
|
|
s->fifo_min = le32_to_cpu(s->fifo[SVGA_FIFO_MIN]);
|
|
|
|
s->fifo_max = le32_to_cpu(s->fifo[SVGA_FIFO_MAX]);
|
|
|
|
s->fifo_next = le32_to_cpu(s->fifo[SVGA_FIFO_NEXT]);
|
|
|
|
s->fifo_stop = le32_to_cpu(s->fifo[SVGA_FIFO_STOP]);
|
|
|
|
|
2016-05-30 09:09:18 +02:00
|
|
|
/* Check range and alignment. */
|
2016-05-30 09:09:20 +02:00
|
|
|
if ((s->fifo_min | s->fifo_max | s->fifo_next | s->fifo_stop) & 3) {
|
2016-05-30 09:09:18 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2016-05-30 09:09:20 +02:00
|
|
|
if (s->fifo_min < sizeof(uint32_t) * 4) {
|
2016-05-30 09:09:18 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2016-05-30 09:09:20 +02:00
|
|
|
if (s->fifo_max > SVGA_FIFO_SIZE ||
|
|
|
|
s->fifo_min >= SVGA_FIFO_SIZE ||
|
|
|
|
s->fifo_stop >= SVGA_FIFO_SIZE ||
|
|
|
|
s->fifo_next >= SVGA_FIFO_SIZE) {
|
2016-05-30 09:09:18 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2016-05-30 09:09:20 +02:00
|
|
|
if (s->fifo_max < s->fifo_min + 10 * 1024) {
|
2016-05-30 09:09:18 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-30 09:09:20 +02:00
|
|
|
num = s->fifo_next - s->fifo_stop;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (num < 0) {
|
2016-05-30 09:09:20 +02:00
|
|
|
num += s->fifo_max - s->fifo_min;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
return num >> 2;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
2008-07-16 06:45:12 +02:00
|
|
|
static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2016-05-30 09:09:20 +02:00
|
|
|
uint32_t cmd = s->fifo[s->fifo_stop >> 2];
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2016-05-30 09:09:20 +02:00
|
|
|
s->fifo_stop += 4;
|
|
|
|
if (s->fifo_stop >= s->fifo_max) {
|
|
|
|
s->fifo_stop = s->fifo_min;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2016-05-30 09:09:20 +02:00
|
|
|
s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
|
2007-04-02 03:10:46 +02:00
|
|
|
return cmd;
|
|
|
|
}
|
|
|
|
|
2008-07-16 06:45:12 +02:00
|
|
|
static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
|
|
|
|
{
|
|
|
|
return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
|
|
|
}
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
static void vmsvga_fifo_run(struct vmsvga_state_s *s)
|
|
|
|
{
|
|
|
|
uint32_t cmd, colour;
|
2016-05-30 09:09:21 +02:00
|
|
|
int args, len, maxloop = 1024;
|
2007-04-02 03:10:46 +02:00
|
|
|
int x, y, dx, dy, width, height;
|
|
|
|
struct vmsvga_cursor_definition_s cursor;
|
2010-09-10 02:23:31 +02:00
|
|
|
uint32_t cmd_start;
|
|
|
|
|
|
|
|
len = vmsvga_fifo_length(s);
|
2016-05-30 09:09:21 +02:00
|
|
|
while (len > 0 && --maxloop > 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
/* May need to go back to the start of the command if incomplete */
|
2016-05-30 09:09:20 +02:00
|
|
|
cmd_start = s->fifo_stop;
|
2010-09-10 02:23:31 +02:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
switch (cmd = vmsvga_fifo_read(s)) {
|
|
|
|
case SVGA_CMD_UPDATE:
|
|
|
|
case SVGA_CMD_UPDATE_VERBOSE:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 5;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
x = vmsvga_fifo_read(s);
|
|
|
|
y = vmsvga_fifo_read(s);
|
|
|
|
width = vmsvga_fifo_read(s);
|
|
|
|
height = vmsvga_fifo_read(s);
|
|
|
|
vmsvga_update_rect_delayed(s, x, y, width, height);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_CMD_RECT_FILL:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 6;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
colour = vmsvga_fifo_read(s);
|
|
|
|
x = vmsvga_fifo_read(s);
|
|
|
|
y = vmsvga_fifo_read(s);
|
|
|
|
width = vmsvga_fifo_read(s);
|
|
|
|
height = vmsvga_fifo_read(s);
|
|
|
|
#ifdef HW_FILL_ACCEL
|
2014-10-06 11:59:51 +02:00
|
|
|
if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
2010-09-10 02:23:31 +02:00
|
|
|
args = 0;
|
2007-04-02 03:10:46 +02:00
|
|
|
goto badcmd;
|
|
|
|
|
|
|
|
case SVGA_CMD_RECT_COPY:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 7;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
x = vmsvga_fifo_read(s);
|
|
|
|
y = vmsvga_fifo_read(s);
|
|
|
|
dx = vmsvga_fifo_read(s);
|
|
|
|
dy = vmsvga_fifo_read(s);
|
|
|
|
width = vmsvga_fifo_read(s);
|
|
|
|
height = vmsvga_fifo_read(s);
|
|
|
|
#ifdef HW_RECT_ACCEL
|
2014-10-06 11:58:51 +02:00
|
|
|
if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
#endif
|
2010-09-10 02:23:31 +02:00
|
|
|
args = 0;
|
2007-04-02 03:10:46 +02:00
|
|
|
goto badcmd;
|
|
|
|
|
|
|
|
case SVGA_CMD_DEFINE_CURSOR:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 8;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
cursor.id = vmsvga_fifo_read(s);
|
|
|
|
cursor.hot_x = vmsvga_fifo_read(s);
|
|
|
|
cursor.hot_y = vmsvga_fifo_read(s);
|
|
|
|
cursor.width = x = vmsvga_fifo_read(s);
|
|
|
|
cursor.height = y = vmsvga_fifo_read(s);
|
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
cursor.bpp = vmsvga_fifo_read(s);
|
2010-01-06 05:43:34 +01:00
|
|
|
|
2010-09-10 02:23:31 +02:00
|
|
|
args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
|
2016-09-08 14:45:54 +02:00
|
|
|
if (cursor.width > 256
|
|
|
|
|| cursor.height > 256
|
|
|
|
|| cursor.bpp > 32
|
|
|
|
|| SVGA_BITMAP_SIZE(x, y)
|
|
|
|
> sizeof(cursor.mask) / sizeof(cursor.mask[0])
|
|
|
|
|| SVGA_PIXMAP_SIZE(x, y, cursor.bpp)
|
|
|
|
> sizeof(cursor.image) / sizeof(cursor.image[0])) {
|
2010-09-10 02:30:04 +02:00
|
|
|
goto badcmd;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
|
|
|
|
len -= args;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2010-01-06 05:43:34 +01:00
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
|
2008-07-16 06:45:12 +02:00
|
|
|
cursor.mask[args] = vmsvga_fifo_read_raw(s);
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
|
|
|
for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
|
2008-07-16 06:45:12 +02:00
|
|
|
cursor.image[args] = vmsvga_fifo_read_raw(s);
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
#ifdef HW_MOUSE_ACCEL
|
|
|
|
vmsvga_cursor_define(s, &cursor);
|
|
|
|
break;
|
|
|
|
#else
|
|
|
|
args = 0;
|
|
|
|
goto badcmd;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Other commands that we at least know the number of arguments
|
|
|
|
* for so we can avoid FIFO desync if driver uses them illegally.
|
|
|
|
*/
|
|
|
|
case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 6;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
x = vmsvga_fifo_read(s);
|
|
|
|
y = vmsvga_fifo_read(s);
|
|
|
|
args = x * y;
|
|
|
|
goto badcmd;
|
|
|
|
case SVGA_CMD_RECT_ROP_FILL:
|
|
|
|
args = 6;
|
|
|
|
goto badcmd;
|
|
|
|
case SVGA_CMD_RECT_ROP_COPY:
|
|
|
|
args = 7;
|
|
|
|
goto badcmd;
|
|
|
|
case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= 4;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
vmsvga_fifo_read(s);
|
|
|
|
args = 7 + (vmsvga_fifo_read(s) >> 2);
|
|
|
|
goto badcmd;
|
|
|
|
case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
|
|
|
args = 12;
|
|
|
|
goto badcmd;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Other commands that are not listed as depending on any
|
|
|
|
* CAPABILITIES bits, but are not described in the README either.
|
|
|
|
*/
|
|
|
|
case SVGA_CMD_SURFACE_FILL:
|
|
|
|
case SVGA_CMD_SURFACE_COPY:
|
|
|
|
case SVGA_CMD_FRONT_ROP_FILL:
|
|
|
|
case SVGA_CMD_FENCE:
|
|
|
|
case SVGA_CMD_INVALID_CMD:
|
|
|
|
break; /* Nop */
|
|
|
|
|
|
|
|
default:
|
2010-09-10 02:23:31 +02:00
|
|
|
args = 0;
|
2007-04-02 03:10:46 +02:00
|
|
|
badcmd:
|
2010-09-10 02:23:31 +02:00
|
|
|
len -= args;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (len < 0) {
|
2010-09-10 02:23:31 +02:00
|
|
|
goto rewind;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
|
|
|
while (args--) {
|
2007-04-02 03:10:46 +02:00
|
|
|
vmsvga_fifo_read(s);
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
2012-11-03 12:47:08 +01:00
|
|
|
__func__, cmd);
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
2010-09-10 02:23:31 +02:00
|
|
|
|
|
|
|
rewind:
|
2016-05-30 09:09:20 +02:00
|
|
|
s->fifo_stop = cmd_start;
|
|
|
|
s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
|
2010-09-10 02:23:31 +02:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
2010-09-10 02:23:31 +02:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
s->syncing = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
|
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
return s->index;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
|
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
s->index = index;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
|
|
|
|
{
|
|
|
|
uint32_t caps;
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->vga.con);
|
2013-03-25 11:44:21 +01:00
|
|
|
PixelFormat pf;
|
2013-03-25 09:53:35 +01:00
|
|
|
uint32_t ret;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
switch (s->index) {
|
|
|
|
case SVGA_REG_ID:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->svgaid;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_ENABLE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->enable;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_WIDTH:
|
2013-03-25 11:44:21 +01:00
|
|
|
ret = s->new_width ? s->new_width : surface_width(surface);
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_HEIGHT:
|
2013-03-25 11:44:21 +01:00
|
|
|
ret = s->new_height ? s->new_height : surface_height(surface);
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_MAX_WIDTH:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = SVGA_MAX_WIDTH;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_MAX_HEIGHT:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = SVGA_MAX_HEIGHT;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_DEPTH:
|
2013-03-25 11:44:21 +01:00
|
|
|
ret = (s->new_depth == 32) ? 24 : s->new_depth;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_BITS_PER_PIXEL:
|
2013-03-25 11:44:21 +01:00
|
|
|
case SVGA_REG_HOST_BITS_PER_PIXEL:
|
|
|
|
ret = s->new_depth;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_PSEUDOCOLOR:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = 0x0;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_RED_MASK:
|
2013-03-25 11:44:21 +01:00
|
|
|
pf = qemu_default_pixelformat(s->new_depth);
|
|
|
|
ret = pf.rmask;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
case SVGA_REG_GREEN_MASK:
|
2013-03-25 11:44:21 +01:00
|
|
|
pf = qemu_default_pixelformat(s->new_depth);
|
|
|
|
ret = pf.gmask;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
case SVGA_REG_BLUE_MASK:
|
2013-03-25 11:44:21 +01:00
|
|
|
pf = qemu_default_pixelformat(s->new_depth);
|
|
|
|
ret = pf.bmask;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_BYTES_PER_LINE:
|
2013-03-25 11:44:21 +01:00
|
|
|
if (s->new_width) {
|
|
|
|
ret = (s->new_depth * s->new_width) / 8;
|
|
|
|
} else {
|
|
|
|
ret = surface_stride(surface);
|
|
|
|
}
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2011-08-08 15:08:56 +02:00
|
|
|
case SVGA_REG_FB_START: {
|
|
|
|
struct pci_vmsvga_state_s *pci_vmsvga
|
|
|
|
= container_of(s, struct pci_vmsvga_state_s, chip);
|
2013-06-30 15:01:36 +02:00
|
|
|
ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2011-08-08 15:08:56 +02:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_FB_OFFSET:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = 0x0;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_VRAM_SIZE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_FB_SIZE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->vga.vram_size;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CAPABILITIES:
|
|
|
|
caps = SVGA_CAP_NONE;
|
|
|
|
#ifdef HW_RECT_ACCEL
|
|
|
|
caps |= SVGA_CAP_RECT_COPY;
|
|
|
|
#endif
|
|
|
|
#ifdef HW_FILL_ACCEL
|
|
|
|
caps |= SVGA_CAP_RECT_FILL;
|
|
|
|
#endif
|
|
|
|
#ifdef HW_MOUSE_ACCEL
|
2013-03-05 15:24:14 +01:00
|
|
|
if (dpy_cursor_define_supported(s->vga.con)) {
|
2007-04-02 03:10:46 +02:00
|
|
|
caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
|
|
|
|
SVGA_CAP_CURSOR_BYPASS;
|
2012-09-12 07:56:45 +02:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
#endif
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = caps;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2011-08-08 15:08:57 +02:00
|
|
|
case SVGA_REG_MEM_START: {
|
|
|
|
struct pci_vmsvga_state_s *pci_vmsvga
|
|
|
|
= container_of(s, struct pci_vmsvga_state_s, chip);
|
2013-06-30 15:01:36 +02:00
|
|
|
ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2011-08-08 15:08:57 +02:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_MEM_SIZE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->fifo_size;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CONFIG_DONE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->config;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_SYNC:
|
|
|
|
case SVGA_REG_BUSY:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->syncing;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_GUEST_ID:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->guest;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_ID:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->cursor.id;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_X:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->cursor.x;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_Y:
|
2014-06-09 07:19:17 +02:00
|
|
|
ret = s->cursor.y;
|
2013-03-25 09:53:35 +01:00
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_ON:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->cursor.on;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_SCRATCH_SIZE:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->scratch_size;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
case SVGA_REG_MEM_REGS:
|
|
|
|
case SVGA_REG_NUM_DISPLAYS:
|
|
|
|
case SVGA_REG_PITCHLOCK:
|
|
|
|
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = 0;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
default:
|
|
|
|
if (s->index >= SVGA_SCRATCH_BASE &&
|
2012-11-03 12:47:08 +01:00
|
|
|
s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
|
|
|
|
break;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
|
|
|
printf("%s: Bad register %02x\n", __func__, s->index);
|
2013-03-25 09:53:35 +01:00
|
|
|
ret = 0;
|
|
|
|
break;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
2013-03-25 09:53:35 +01:00
|
|
|
if (s->index >= SVGA_SCRATCH_BASE) {
|
|
|
|
trace_vmware_scratch_read(s->index, ret);
|
|
|
|
} else if (s->index >= SVGA_PALETTE_BASE) {
|
|
|
|
trace_vmware_palette_read(s->index, ret);
|
|
|
|
} else {
|
|
|
|
trace_vmware_value_read(s->index, ret);
|
|
|
|
}
|
|
|
|
return ret;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
|
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2012-11-03 12:47:08 +01:00
|
|
|
|
2013-03-25 09:53:35 +01:00
|
|
|
if (s->index >= SVGA_SCRATCH_BASE) {
|
|
|
|
trace_vmware_scratch_write(s->index, value);
|
|
|
|
} else if (s->index >= SVGA_PALETTE_BASE) {
|
|
|
|
trace_vmware_palette_write(s->index, value);
|
|
|
|
} else {
|
|
|
|
trace_vmware_value_write(s->index, value);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
switch (s->index) {
|
|
|
|
case SVGA_REG_ID:
|
2012-11-03 12:47:08 +01:00
|
|
|
if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
|
2007-04-02 03:10:46 +02:00
|
|
|
s->svgaid = value;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_ENABLE:
|
2012-11-03 12:47:08 +01:00
|
|
|
s->enable = !!value;
|
2007-04-02 03:10:46 +02:00
|
|
|
s->invalidated = 1;
|
2013-03-13 14:04:18 +01:00
|
|
|
s->vga.hw_ops->invalidate(&s->vga);
|
2012-11-03 12:47:08 +01:00
|
|
|
if (s->enable && s->config) {
|
2010-09-10 02:30:04 +02:00
|
|
|
vga_dirty_log_stop(&s->vga);
|
|
|
|
} else {
|
|
|
|
vga_dirty_log_start(&s->vga);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_WIDTH:
|
2012-11-03 12:47:08 +01:00
|
|
|
if (value <= SVGA_MAX_WIDTH) {
|
|
|
|
s->new_width = value;
|
|
|
|
s->invalidated = 1;
|
|
|
|
} else {
|
|
|
|
printf("%s: Bad width: %i\n", __func__, value);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_HEIGHT:
|
2012-11-03 12:47:08 +01:00
|
|
|
if (value <= SVGA_MAX_HEIGHT) {
|
|
|
|
s->new_height = value;
|
|
|
|
s->invalidated = 1;
|
|
|
|
} else {
|
|
|
|
printf("%s: Bad height: %i\n", __func__, value);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_BITS_PER_PIXEL:
|
2013-03-25 11:44:21 +01:00
|
|
|
if (value != 32) {
|
2012-11-03 12:47:08 +01:00
|
|
|
printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
|
2007-04-02 03:10:46 +02:00
|
|
|
s->config = 0;
|
2013-03-25 11:44:21 +01:00
|
|
|
s->invalidated = 1;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_CONFIG_DONE:
|
|
|
|
if (value) {
|
2009-12-17 23:08:06 +01:00
|
|
|
s->fifo = (uint32_t *) s->fifo_ptr;
|
2012-11-03 12:47:08 +01:00
|
|
|
vga_dirty_log_stop(&s->vga);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
2007-05-13 15:26:49 +02:00
|
|
|
s->config = !!value;
|
2007-04-02 03:10:46 +02:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_SYNC:
|
|
|
|
s->syncing = 1;
|
|
|
|
vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_GUEST_ID:
|
|
|
|
s->guest = value;
|
|
|
|
#ifdef VERBOSE
|
|
|
|
if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
2012-11-03 12:47:08 +01:00
|
|
|
ARRAY_SIZE(vmsvga_guest_id)) {
|
|
|
|
printf("%s: guest runs %s.\n", __func__,
|
|
|
|
vmsvga_guest_id[value - GUEST_OS_BASE]);
|
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_ID:
|
|
|
|
s->cursor.id = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_X:
|
|
|
|
s->cursor.x = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_Y:
|
|
|
|
s->cursor.y = value;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SVGA_REG_CURSOR_ON:
|
|
|
|
s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
|
|
|
|
s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
|
|
|
|
#ifdef HW_MOUSE_ACCEL
|
2012-09-12 07:56:45 +02:00
|
|
|
if (value <= SVGA_CURSOR_ON_SHOW) {
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
|
2012-09-12 07:56:45 +02:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
case SVGA_REG_DEPTH:
|
2007-04-02 03:10:46 +02:00
|
|
|
case SVGA_REG_MEM_REGS:
|
|
|
|
case SVGA_REG_NUM_DISPLAYS:
|
|
|
|
case SVGA_REG_PITCHLOCK:
|
|
|
|
case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
if (s->index >= SVGA_SCRATCH_BASE &&
|
|
|
|
s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
|
|
|
|
s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
|
|
|
|
break;
|
|
|
|
}
|
2012-11-03 12:47:08 +01:00
|
|
|
printf("%s: Bad register %02x\n", __func__, s->index);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
|
|
|
|
{
|
2012-11-03 12:47:08 +01:00
|
|
|
printf("%s: what are we supposed to return?\n", __func__);
|
2007-04-02 03:10:46 +02:00
|
|
|
return 0xcafe;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
|
|
|
|
{
|
2012-11-03 12:47:08 +01:00
|
|
|
printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
static inline void vmsvga_check_size(struct vmsvga_state_s *s)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2013-03-05 15:24:14 +01:00
|
|
|
DisplaySurface *surface = qemu_console_surface(s->vga.con);
|
|
|
|
|
|
|
|
if (s->new_width != surface_width(surface) ||
|
2013-03-25 11:44:21 +01:00
|
|
|
s->new_height != surface_height(surface) ||
|
|
|
|
s->new_depth != surface_bits_per_pixel(surface)) {
|
|
|
|
int stride = (s->new_depth * s->new_width) / 8;
|
2014-06-18 11:03:15 +02:00
|
|
|
pixman_format_code_t format =
|
|
|
|
qemu_default_pixman_format(s->new_depth, true);
|
2013-03-25 11:44:21 +01:00
|
|
|
trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
|
|
|
|
surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
|
2014-06-18 11:03:15 +02:00
|
|
|
format, stride,
|
|
|
|
s->vga.vram_ptr);
|
2013-03-25 11:44:21 +01:00
|
|
|
dpy_gfx_replace_surface(s->vga.con, surface);
|
2007-04-02 03:10:46 +02:00
|
|
|
s->invalidated = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vmsvga_update_display(void *opaque)
|
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2013-03-19 20:44:56 +01:00
|
|
|
DisplaySurface *surface;
|
2012-11-03 12:47:08 +01:00
|
|
|
bool dirty = false;
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
if (!s->enable) {
|
2013-03-13 14:04:18 +01:00
|
|
|
s->vga.hw_ops->gfx_update(&s->vga);
|
2007-04-02 03:10:46 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
vmsvga_check_size(s);
|
2013-03-19 20:44:56 +01:00
|
|
|
surface = qemu_console_surface(s->vga.con);
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
vmsvga_fifo_run(s);
|
|
|
|
vmsvga_update_rect_flush(s);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Is it more efficient to look at vram VGA-dirty bits or wait
|
|
|
|
* for the driver to issue SVGA_CMD_UPDATE?
|
|
|
|
*/
|
2015-03-23 10:50:57 +01:00
|
|
|
if (memory_region_is_logging(&s->vga.vram, DIRTY_MEMORY_VGA)) {
|
2012-11-03 12:47:08 +01:00
|
|
|
vga_sync_dirty_bitmap(&s->vga);
|
|
|
|
dirty = memory_region_get_dirty(&s->vga.vram, 0,
|
2013-03-05 15:24:14 +01:00
|
|
|
surface_stride(surface) * surface_height(surface),
|
2012-11-03 12:47:08 +01:00
|
|
|
DIRTY_MEMORY_VGA);
|
|
|
|
}
|
|
|
|
if (s->invalidated || dirty) {
|
2007-04-02 03:10:46 +02:00
|
|
|
s->invalidated = 0;
|
2013-03-05 15:24:14 +01:00
|
|
|
dpy_gfx_update(s->vga.con, 0, 0,
|
|
|
|
surface_width(surface), surface_height(surface));
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
|
|
|
if (dirty) {
|
|
|
|
memory_region_reset_dirty(&s->vga.vram, 0,
|
2013-03-05 15:24:14 +01:00
|
|
|
surface_stride(surface) * surface_height(surface),
|
2012-11-03 12:47:08 +01:00
|
|
|
DIRTY_MEMORY_VGA);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-22 19:12:08 +02:00
|
|
|
static void vmsvga_reset(DeviceState *dev)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2013-06-24 08:58:45 +02:00
|
|
|
struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
|
2011-08-22 19:12:08 +02:00
|
|
|
struct vmsvga_state_s *s = &pci->chip;
|
|
|
|
|
2007-04-02 03:10:46 +02:00
|
|
|
s->index = 0;
|
|
|
|
s->enable = 0;
|
|
|
|
s->config = 0;
|
|
|
|
s->svgaid = SVGA_ID;
|
|
|
|
s->cursor.on = 0;
|
|
|
|
s->redraw_fifo_first = 0;
|
|
|
|
s->redraw_fifo_last = 0;
|
|
|
|
s->syncing = 0;
|
2009-12-17 23:08:10 +01:00
|
|
|
|
|
|
|
vga_dirty_log_start(&s->vga);
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void vmsvga_invalidate_display(void *opaque)
|
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2007-04-02 03:10:46 +02:00
|
|
|
if (!s->enable) {
|
2013-03-13 14:04:18 +01:00
|
|
|
s->vga.hw_ops->invalidate(&s->vga);
|
2007-04-02 03:10:46 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->invalidated = 1;
|
|
|
|
}
|
|
|
|
|
2009-10-01 23:12:16 +02:00
|
|
|
static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
|
2008-02-10 17:33:14 +01:00
|
|
|
{
|
2009-10-14 17:49:08 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2008-02-10 17:33:14 +01:00
|
|
|
|
2013-03-13 14:04:18 +01:00
|
|
|
if (s->vga.hw_ops->text_update) {
|
|
|
|
s->vga.hw_ops->text_update(&s->vga, chardata);
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2008-02-10 17:33:14 +01:00
|
|
|
}
|
|
|
|
|
2009-10-14 19:30:22 +02:00
|
|
|
static int vmsvga_post_load(void *opaque, int version_id)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2009-10-14 19:30:22 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2007-04-02 03:10:46 +02:00
|
|
|
|
|
|
|
s->invalidated = 1;
|
2012-11-03 12:47:08 +01:00
|
|
|
if (s->config) {
|
2009-12-17 23:08:06 +01:00
|
|
|
s->fifo = (uint32_t *) s->fifo_ptr;
|
2012-11-03 12:47:08 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-04 21:44:44 +01:00
|
|
|
static const VMStateDescription vmstate_vmware_vga_internal = {
|
2009-10-14 19:30:22 +02:00
|
|
|
.name = "vmware_vga_internal",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.post_load = vmsvga_post_load,
|
2014-04-16 15:32:32 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2013-03-25 11:44:21 +01:00
|
|
|
VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s),
|
2009-10-14 19:30:22 +02:00
|
|
|
VMSTATE_INT32(enable, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(config, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(index, struct vmsvga_state_s),
|
|
|
|
VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
|
|
|
scratch_size, 0, vmstate_info_uint32, uint32_t),
|
|
|
|
VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
|
|
|
VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
|
|
|
VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
|
|
|
VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
2012-11-03 12:47:08 +01:00
|
|
|
VMSTATE_UNUSED(4), /* was fb_size */
|
2009-10-14 19:30:22 +02:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-12-04 21:44:44 +01:00
|
|
|
static const VMStateDescription vmstate_vmware_vga = {
|
2009-10-14 19:30:22 +02:00
|
|
|
.name = "vmware_vga",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
2014-04-16 15:32:32 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2013-06-30 15:01:36 +02:00
|
|
|
VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
|
2009-10-14 19:30:22 +02:00
|
|
|
VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
|
|
|
|
vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2013-03-13 14:04:18 +01:00
|
|
|
static const GraphicHwOps vmsvga_ops = {
|
|
|
|
.invalidate = vmsvga_invalidate_display,
|
|
|
|
.gfx_update = vmsvga_update_display,
|
|
|
|
.text_update = vmsvga_text_update,
|
|
|
|
};
|
|
|
|
|
2013-04-17 10:21:27 +02:00
|
|
|
static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
|
2011-08-16 17:27:39 +02:00
|
|
|
MemoryRegion *address_space, MemoryRegion *io)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
|
|
|
s->scratch_size = SVGA_SCRATCH_SIZE;
|
2011-08-21 05:09:37 +02:00
|
|
|
s->scratch = g_malloc(s->scratch_size * 4);
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2014-01-24 15:35:21 +01:00
|
|
|
s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s);
|
2009-08-23 19:00:58 +02:00
|
|
|
|
2009-12-17 23:08:06 +01:00
|
|
|
s->fifo_size = SVGA_FIFO_SIZE;
|
2014-09-09 07:27:55 +02:00
|
|
|
memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
|
|
|
&error_fatal);
|
2011-12-20 14:59:12 +01:00
|
|
|
vmstate_register_ram_global(&s->fifo_ram);
|
2011-08-08 15:08:57 +02:00
|
|
|
s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
|
2009-12-17 23:08:06 +01:00
|
|
|
|
2013-10-11 19:56:59 +02:00
|
|
|
vga_common_init(&s->vga, OBJECT(dev), true);
|
2013-06-07 03:21:13 +02:00
|
|
|
vga_init(&s->vga, OBJECT(dev), address_space, io, true);
|
2010-06-25 19:09:07 +02:00
|
|
|
vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
|
2013-03-25 11:44:21 +01:00
|
|
|
s->new_depth = 32;
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
|
|
|
|
2012-11-03 12:47:08 +01:00
|
|
|
static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
|
2008-01-14 02:52:52 +01:00
|
|
|
{
|
2011-08-08 15:08:57 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
|
|
|
|
|
|
|
switch (addr) {
|
|
|
|
case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
|
|
|
|
case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
|
|
|
|
case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
|
|
|
|
default: return -1u;
|
|
|
|
}
|
2008-01-14 02:52:52 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void vmsvga_io_write(void *opaque, hwaddr addr,
|
2011-08-08 15:08:57 +02:00
|
|
|
uint64_t data, unsigned size)
|
2008-03-06 21:28:49 +01:00
|
|
|
{
|
2011-08-08 15:08:57 +02:00
|
|
|
struct vmsvga_state_s *s = opaque;
|
2009-12-17 23:08:08 +01:00
|
|
|
|
2011-08-08 15:08:57 +02:00
|
|
|
switch (addr) {
|
|
|
|
case SVGA_IO_MUL * SVGA_INDEX_PORT:
|
2012-07-08 08:56:53 +02:00
|
|
|
vmsvga_index_write(s, addr, data);
|
|
|
|
break;
|
2011-08-08 15:08:57 +02:00
|
|
|
case SVGA_IO_MUL * SVGA_VALUE_PORT:
|
2012-07-08 08:56:53 +02:00
|
|
|
vmsvga_value_write(s, addr, data);
|
|
|
|
break;
|
2011-08-08 15:08:57 +02:00
|
|
|
case SVGA_IO_MUL * SVGA_BIOS_PORT:
|
2012-07-08 08:56:53 +02:00
|
|
|
vmsvga_bios_write(s, addr, data);
|
|
|
|
break;
|
2011-08-08 15:08:57 +02:00
|
|
|
}
|
2008-03-06 21:28:49 +01:00
|
|
|
}
|
|
|
|
|
2011-08-08 15:08:57 +02:00
|
|
|
static const MemoryRegionOps vmsvga_io_ops = {
|
|
|
|
.read = vmsvga_io_read,
|
|
|
|
.write = vmsvga_io_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
2013-06-22 08:07:02 +02:00
|
|
|
.unaligned = true,
|
|
|
|
},
|
|
|
|
.impl = {
|
|
|
|
.unaligned = true,
|
2011-08-08 15:08:57 +02:00
|
|
|
},
|
|
|
|
};
|
2009-12-17 23:08:06 +01:00
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
|
2007-04-02 03:10:46 +02:00
|
|
|
{
|
2013-06-24 08:58:45 +02:00
|
|
|
struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
|
2011-08-08 15:08:57 +02:00
|
|
|
|
2013-06-30 15:01:36 +02:00
|
|
|
dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
|
|
|
|
dev->config[PCI_LATENCY_TIMER] = 0x40;
|
|
|
|
dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&s->io_bar, NULL, &vmsvga_io_ops, &s->chip,
|
2011-08-08 15:08:57 +02:00
|
|
|
"vmsvga-io", 0x10);
|
2012-08-23 13:02:33 +02:00
|
|
|
memory_region_set_flush_coalesced(&s->io_bar);
|
2013-06-30 15:01:36 +02:00
|
|
|
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
2009-12-17 23:08:06 +01:00
|
|
|
|
2013-04-17 10:21:27 +02:00
|
|
|
vmsvga_init(DEVICE(dev), &s->chip,
|
|
|
|
pci_address_space(dev), pci_address_space_io(dev));
|
2007-04-02 03:10:46 +02:00
|
|
|
|
2013-06-30 15:01:36 +02:00
|
|
|
pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
2012-11-03 12:47:08 +01:00
|
|
|
&s->chip.vga.vram);
|
2013-06-30 15:01:36 +02:00
|
|
|
pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
2011-08-08 15:09:31 +02:00
|
|
|
&s->chip.fifo_ram);
|
2011-08-08 15:08:57 +02:00
|
|
|
|
2010-11-17 12:06:44 +01:00
|
|
|
if (!dev->rom_bar) {
|
|
|
|
/* compatibility with pc-0.13 and older */
|
2013-06-07 03:21:13 +02:00
|
|
|
vga_init_vbe(&s->chip.vga, OBJECT(dev), pci_address_space(dev));
|
2010-11-17 12:06:44 +01:00
|
|
|
}
|
2007-04-02 03:10:46 +02:00
|
|
|
}
|
2009-07-28 18:18:00 +02:00
|
|
|
|
2012-05-24 09:59:44 +02:00
|
|
|
static Property vga_vmware_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
|
2012-06-11 10:42:53 +02:00
|
|
|
chip.vga.vram_size_mb, 16),
|
2012-05-24 09:59:44 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2011-12-04 19:22:06 +01:00
|
|
|
static void vmsvga_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-04 19:22:06 +01:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2015-01-19 15:52:30 +01:00
|
|
|
k->realize = pci_vmsvga_realize;
|
2011-12-04 19:22:06 +01:00
|
|
|
k->romfile = "vgabios-vmware.bin";
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_VMWARE;
|
|
|
|
k->device_id = SVGA_PCI_DEVICE_ID;
|
|
|
|
k->class_id = PCI_CLASS_DISPLAY_VGA;
|
|
|
|
k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
|
|
|
|
k->subsystem_id = SVGA_PCI_DEVICE_ID;
|
2011-12-08 04:34:16 +01:00
|
|
|
dc->reset = vmsvga_reset;
|
|
|
|
dc->vmsd = &vmstate_vmware_vga;
|
2012-05-24 09:59:44 +02:00
|
|
|
dc->props = vga_vmware_properties;
|
2014-02-05 16:36:48 +01:00
|
|
|
dc->hotpluggable = false;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
|
2011-12-04 19:22:06 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo vmsvga_info = {
|
2013-06-24 08:58:45 +02:00
|
|
|
.name = TYPE_VMWARE_SVGA,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(struct pci_vmsvga_state_s),
|
|
|
|
.class_init = vmsvga_class_init,
|
2009-07-28 18:18:00 +02:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void vmsvga_register_types(void)
|
2009-07-28 18:18:00 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&vmsvga_info);
|
2009-07-28 18:18:00 +02:00
|
|
|
}
|
2012-02-09 15:20:55 +01:00
|
|
|
|
|
|
|
type_init(vmsvga_register_types)
|