2022-06-06 14:43:20 +02:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU loongson 3a5000 develop board emulation
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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2022-06-06 14:43:27 +02:00
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#include "hw/char/serial.h"
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2022-06-06 14:43:20 +02:00
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "sysemu/runstate.h"
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#include "sysemu/reset.h"
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#include "sysemu/rtc.h"
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#include "hw/loongarch/virt.h"
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#include "exec/address-spaces.h"
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2022-06-06 14:43:27 +02:00
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#include "hw/irq.h"
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#include "net/net.h"
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2022-06-06 14:43:29 +02:00
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#include "hw/loader.h"
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#include "elf.h"
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2022-06-06 14:43:25 +02:00
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#include "hw/intc/loongarch_ipi.h"
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#include "hw/intc/loongarch_extioi.h"
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#include "hw/intc/loongarch_pch_pic.h"
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#include "hw/intc/loongarch_pch_msi.h"
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#include "hw/pci-host/ls7a.h"
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2022-06-06 14:43:27 +02:00
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#include "hw/pci-host/gpex.h"
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#include "hw/misc/unimp.h"
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2022-07-12 10:32:01 +02:00
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#include "hw/loongarch/fw_cfg.h"
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2022-06-06 14:43:20 +02:00
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#include "target/loongarch/cpu.h"
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2022-07-12 10:32:04 +02:00
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#include "hw/firmware/smbios.h"
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2022-07-12 10:32:05 +02:00
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#include "hw/acpi/aml-build.h"
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#include "qapi/qapi-visit-common.h"
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#include "hw/acpi/generic_event_device.h"
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#include "hw/mem/nvdimm.h"
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2022-07-12 10:32:06 +02:00
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#include "sysemu/device_tree.h"
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#include <libfdt.h>
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static void create_fdt(LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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ms->fdt = create_device_tree(&lams->fdt_size);
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if (!ms->fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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/* Header */
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qemu_fdt_setprop_string(ms->fdt, "/", "compatible",
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"linux,dummy-loongson3");
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qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2);
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}
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static void fdt_add_cpu_nodes(const LoongArchMachineState *lams)
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{
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int num;
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const MachineState *ms = MACHINE(lams);
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int smp_cpus = ms->smp.cpus;
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qemu_fdt_add_subnode(ms->fdt, "/cpus");
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qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
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/* cpu nodes */
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for (num = smp_cpus - 1; num >= 0; num--) {
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char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
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LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num));
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
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cpu->dtb_compatible);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
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qemu_fdt_alloc_phandle(ms->fdt));
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g_free(nodename);
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}
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/*cpu map */
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qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
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for (num = smp_cpus - 1; num >= 0; num--) {
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char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num);
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char *map_path;
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if (ms->smp.threads > 1) {
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map_path = g_strdup_printf(
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"/cpus/cpu-map/socket%d/core%d/thread%d",
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num / (ms->smp.cores * ms->smp.threads),
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(num / ms->smp.threads) % ms->smp.cores,
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num % ms->smp.threads);
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} else {
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map_path = g_strdup_printf(
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"/cpus/cpu-map/socket%d/core%d",
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num / ms->smp.cores,
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num % ms->smp.cores);
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}
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qemu_fdt_add_path(ms->fdt, map_path);
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qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
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g_free(map_path);
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g_free(cpu_path);
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}
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}
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static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
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{
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char *nodename;
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hwaddr base = VIRT_FWCFG_BASE;
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const MachineState *ms = MACHINE(lams);
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nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename,
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"compatible", "qemu,fw-cfg-mmio");
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
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2, base, 2, 0x8);
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qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
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g_free(nodename);
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}
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static void fdt_add_pcie_node(const LoongArchMachineState *lams)
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{
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char *nodename;
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2022-07-29 09:30:18 +02:00
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hwaddr base_mmio = VIRT_PCI_MEM_BASE;
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hwaddr size_mmio = VIRT_PCI_MEM_SIZE;
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hwaddr base_pio = VIRT_PCI_IO_BASE;
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hwaddr size_pio = VIRT_PCI_IO_SIZE;
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hwaddr base_pcie = VIRT_PCI_CFG_BASE;
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hwaddr size_pcie = VIRT_PCI_CFG_SIZE;
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2022-07-12 10:32:06 +02:00
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hwaddr base = base_pcie;
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const MachineState *ms = MACHINE(lams);
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nodename = g_strdup_printf("/pcie@%" PRIx64, base);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename,
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"compatible", "pci-host-ecam-generic");
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qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
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2022-07-29 09:30:18 +02:00
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PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1));
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2022-07-12 10:32:06 +02:00
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qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
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2, base_pcie, 2, size_pcie);
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
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2022-07-29 09:30:18 +02:00
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1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET,
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2022-07-12 10:32:06 +02:00
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2, base_pio, 2, size_pio,
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1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
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2, base_mmio, 2, size_mmio);
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g_free(nodename);
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qemu_fdt_dumpdtb(ms->fdt, lams->fdt_size);
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}
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2022-06-06 14:43:20 +02:00
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2022-06-06 14:43:30 +02:00
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#define PM_BASE 0x10080000
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#define PM_SIZE 0x100
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#define PM_CTRL 0x10
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2022-07-12 10:32:04 +02:00
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static void virt_build_smbios(LoongArchMachineState *lams)
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{
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MachineState *ms = MACHINE(lams);
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MachineClass *mc = MACHINE_GET_CLASS(lams);
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uint8_t *smbios_tables, *smbios_anchor;
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size_t smbios_tables_len, smbios_anchor_len;
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const char *product = "QEMU Virtual Machine";
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if (!lams->fw_cfg) {
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return;
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}
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smbios_set_defaults("QEMU", product, mc->name, false,
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true, SMBIOS_ENTRY_POINT_TYPE_64);
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smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len,
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&smbios_anchor, &smbios_anchor_len, &error_fatal);
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if (smbios_anchor) {
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fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables",
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smbios_tables, smbios_tables_len);
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fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor",
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smbios_anchor, smbios_anchor_len);
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}
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}
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static void virt_machine_done(Notifier *notifier, void *data)
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{
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LoongArchMachineState *lams = container_of(notifier,
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LoongArchMachineState, machine_done);
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virt_build_smbios(lams);
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2022-07-12 10:32:05 +02:00
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loongarch_acpi_setup(lams);
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2022-07-12 10:32:04 +02:00
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}
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2022-07-12 10:32:01 +02:00
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struct memmap_entry {
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uint64_t address;
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uint64_t length;
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uint32_t type;
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uint32_t reserved;
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};
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static struct memmap_entry *memmap_table;
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static unsigned memmap_entries;
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static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type)
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{
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/* Ensure there are no duplicate entries. */
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for (unsigned i = 0; i < memmap_entries; i++) {
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assert(memmap_table[i].address != address);
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}
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memmap_table = g_renew(struct memmap_entry, memmap_table,
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memmap_entries + 1);
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memmap_table[memmap_entries].address = cpu_to_le64(address);
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memmap_table[memmap_entries].length = cpu_to_le64(length);
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memmap_table[memmap_entries].type = cpu_to_le32(type);
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memmap_table[memmap_entries].reserved = 0;
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memmap_entries++;
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}
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2022-06-06 14:43:30 +02:00
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/*
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* This is a placeholder for missing ACPI,
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* and will eventually be replaced.
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*/
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static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size)
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{
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return 0;
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}
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static void loongarch_virt_pm_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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if (addr != PM_CTRL) {
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return;
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}
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switch (val) {
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case 0x00:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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return;
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case 0xff:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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return;
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default:
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return;
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}
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}
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static const MemoryRegionOps loongarch_virt_pm_ops = {
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.read = loongarch_virt_pm_read,
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.write = loongarch_virt_pm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1
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}
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};
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2022-06-06 14:43:29 +02:00
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static struct _loaderparams {
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uint64_t ram_size;
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const char *kernel_filename;
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2022-07-12 10:32:03 +02:00
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const char *kernel_cmdline;
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const char *initrd_filename;
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2022-06-06 14:43:29 +02:00
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} loaderparams;
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static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr)
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{
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return addr & 0x1fffffffll;
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}
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static int64_t load_kernel_info(void)
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{
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uint64_t kernel_entry, kernel_low, kernel_high;
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ssize_t kernel_size;
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kernel_size = load_elf(loaderparams.kernel_filename, NULL,
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cpu_loongarch_virt_to_phys, NULL,
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&kernel_entry, &kernel_low,
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&kernel_high, NULL, 0,
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EM_LOONGARCH, 1, 0);
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if (kernel_size < 0) {
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error_report("could not load kernel '%s': %s",
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loaderparams.kernel_filename,
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load_elf_strerror(kernel_size));
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exit(1);
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}
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return kernel_entry;
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}
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2022-07-12 10:32:05 +02:00
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static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams)
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{
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DeviceState *dev;
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MachineState *ms = MACHINE(lams);
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uint32_t event = ACPI_GED_PWR_DOWN_EVT;
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if (ms->ram_slots) {
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event |= ACPI_GED_MEM_HOTPLUG_EVT;
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}
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dev = qdev_new(TYPE_ACPI_GED);
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qdev_prop_set_uint32(dev, "ged-event", event);
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/* ged event */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR);
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/* memory hotplug */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR);
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/* ged regs used for reset and power down */
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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2022-07-29 09:30:18 +02:00
|
|
|
qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET));
|
2022-07-12 10:32:05 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
|
|
return dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams)
|
2022-06-06 14:43:27 +02:00
|
|
|
{
|
|
|
|
DeviceState *gpex_dev;
|
|
|
|
SysBusDevice *d;
|
|
|
|
PCIBus *pci_bus;
|
|
|
|
MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg;
|
2022-06-06 14:43:30 +02:00
|
|
|
MemoryRegion *mmio_alias, *mmio_reg, *pm_mem;
|
2022-06-06 14:43:27 +02:00
|
|
|
int i;
|
|
|
|
|
|
|
|
gpex_dev = qdev_new(TYPE_GPEX_HOST);
|
|
|
|
d = SYS_BUS_DEVICE(gpex_dev);
|
|
|
|
sysbus_realize_and_unref(d, &error_fatal);
|
|
|
|
pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
|
|
|
|
|
|
|
|
/* Map only part size_ecam bytes of ECAM space */
|
|
|
|
ecam_alias = g_new0(MemoryRegion, 1);
|
|
|
|
ecam_reg = sysbus_mmio_get_region(d, 0);
|
|
|
|
memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
|
2022-07-29 09:30:18 +02:00
|
|
|
ecam_reg, 0, VIRT_PCI_CFG_SIZE);
|
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE,
|
2022-06-06 14:43:27 +02:00
|
|
|
ecam_alias);
|
|
|
|
|
|
|
|
/* Map PCI mem space */
|
|
|
|
mmio_alias = g_new0(MemoryRegion, 1);
|
|
|
|
mmio_reg = sysbus_mmio_get_region(d, 1);
|
|
|
|
memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
|
2022-07-29 09:30:18 +02:00
|
|
|
mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE);
|
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE,
|
2022-06-06 14:43:27 +02:00
|
|
|
mmio_alias);
|
|
|
|
|
|
|
|
/* Map PCI IO port space. */
|
|
|
|
pio_alias = g_new0(MemoryRegion, 1);
|
|
|
|
pio_reg = sysbus_mmio_get_region(d, 2);
|
|
|
|
memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
|
2022-07-29 09:30:18 +02:00
|
|
|
VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE);
|
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE,
|
2022-06-06 14:43:27 +02:00
|
|
|
pio_alias);
|
|
|
|
|
|
|
|
for (i = 0; i < GPEX_NUM_IRQS; i++) {
|
|
|
|
sysbus_connect_irq(d, i,
|
|
|
|
qdev_get_gpio_in(pch_pic, 16 + i));
|
|
|
|
gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
|
|
|
|
}
|
|
|
|
|
2022-07-29 09:30:18 +02:00
|
|
|
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
|
2022-06-06 14:43:27 +02:00
|
|
|
qdev_get_gpio_in(pch_pic,
|
2022-07-29 09:30:18 +02:00
|
|
|
VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
|
2022-06-06 14:43:27 +02:00
|
|
|
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
|
|
|
|
|
|
|
|
/* Network init */
|
|
|
|
for (i = 0; i < nb_nics; i++) {
|
|
|
|
NICInfo *nd = &nd_table[i];
|
|
|
|
|
|
|
|
if (!nd->model) {
|
|
|
|
nd->model = g_strdup("virtio");
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* VGA setup */
|
|
|
|
pci_vga_init(pci_bus);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* There are some invalid guest memory access.
|
|
|
|
* Create some unimplemented devices to emulate this.
|
|
|
|
*/
|
|
|
|
create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
|
2022-07-29 09:30:18 +02:00
|
|
|
sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
|
2022-06-06 14:43:28 +02:00
|
|
|
qdev_get_gpio_in(pch_pic,
|
2022-07-29 09:30:18 +02:00
|
|
|
VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
|
2022-06-06 14:43:30 +02:00
|
|
|
|
|
|
|
pm_mem = g_new(MemoryRegion, 1);
|
|
|
|
memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
|
|
|
|
NULL, "loongarch_virt_pm", PM_SIZE);
|
|
|
|
memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem);
|
2022-07-12 10:32:05 +02:00
|
|
|
/* acpi ged */
|
|
|
|
lams->acpi_ged = create_acpi_ged(pch_pic, lams);
|
2022-06-06 14:43:27 +02:00
|
|
|
}
|
|
|
|
|
2022-06-06 14:43:25 +02:00
|
|
|
static void loongarch_irq_init(LoongArchMachineState *lams)
|
|
|
|
{
|
|
|
|
MachineState *ms = MACHINE(lams);
|
|
|
|
DeviceState *pch_pic, *pch_msi, *cpudev;
|
|
|
|
DeviceState *ipi, *extioi;
|
|
|
|
SysBusDevice *d;
|
|
|
|
LoongArchCPU *lacpu;
|
|
|
|
CPULoongArchState *env;
|
|
|
|
CPUState *cpu_state;
|
|
|
|
int cpu, pin, i;
|
|
|
|
|
|
|
|
ipi = qdev_new(TYPE_LOONGARCH_IPI);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
|
|
|
|
|
|
|
|
extioi = qdev_new(TYPE_LOONGARCH_EXTIOI);
|
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The connection of interrupts:
|
|
|
|
* +-----+ +---------+ +-------+
|
|
|
|
* | IPI |--> | CPUINTC | <-- | Timer |
|
|
|
|
* +-----+ +---------+ +-------+
|
|
|
|
* ^
|
|
|
|
* |
|
|
|
|
* +---------+
|
|
|
|
* | EIOINTC |
|
|
|
|
* +---------+
|
|
|
|
* ^ ^
|
|
|
|
* | |
|
|
|
|
* +---------+ +---------+
|
|
|
|
* | PCH-PIC | | PCH-MSI |
|
|
|
|
* +---------+ +---------+
|
|
|
|
* ^ ^ ^
|
|
|
|
* | | |
|
|
|
|
* +--------+ +---------+ +---------+
|
|
|
|
* | UARTs | | Devices | | Devices |
|
|
|
|
* +--------+ +---------+ +---------+
|
|
|
|
*/
|
|
|
|
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
|
|
|
|
cpu_state = qemu_get_cpu(cpu);
|
|
|
|
cpudev = DEVICE(cpu_state);
|
|
|
|
lacpu = LOONGARCH_CPU(cpu_state);
|
|
|
|
env = &(lacpu->env);
|
|
|
|
|
|
|
|
/* connect ipi irq to cpu irq */
|
|
|
|
qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI));
|
|
|
|
/* IPI iocsr memory region */
|
|
|
|
memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX,
|
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
|
2022-07-05 08:49:00 +02:00
|
|
|
cpu * 2));
|
|
|
|
memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR,
|
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
|
|
|
|
cpu * 2 + 1));
|
2022-06-06 14:43:25 +02:00
|
|
|
/* extioi iocsr memory region */
|
|
|
|
memory_region_add_subregion(&env->system_iocsr, APIC_BASE,
|
|
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
|
|
|
|
cpu));
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* connect ext irq to the cpu irq
|
|
|
|
* cpu_pin[9:2] <= intc_pin[7:0]
|
|
|
|
*/
|
|
|
|
for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
|
|
|
|
cpudev = DEVICE(qemu_get_cpu(cpu));
|
|
|
|
for (pin = 0; pin < LS3A_INTC_IP; pin++) {
|
|
|
|
qdev_connect_gpio_out(extioi, (cpu * 8 + pin),
|
|
|
|
qdev_get_gpio_in(cpudev, pin + 2));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
|
|
|
|
d = SYS_BUS_DEVICE(pch_pic);
|
|
|
|
sysbus_realize_and_unref(d, &error_fatal);
|
2022-07-29 09:30:18 +02:00
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
|
2022-06-06 14:43:25 +02:00
|
|
|
sysbus_mmio_get_region(d, 0));
|
|
|
|
memory_region_add_subregion(get_system_memory(),
|
2022-07-29 09:30:18 +02:00
|
|
|
VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
|
2022-06-06 14:43:25 +02:00
|
|
|
sysbus_mmio_get_region(d, 1));
|
|
|
|
memory_region_add_subregion(get_system_memory(),
|
2022-07-29 09:30:18 +02:00
|
|
|
VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
|
2022-06-06 14:43:25 +02:00
|
|
|
sysbus_mmio_get_region(d, 2));
|
|
|
|
|
|
|
|
/* Connect 64 pch_pic irqs to extioi */
|
|
|
|
for (int i = 0; i < PCH_PIC_IRQ_NUM; i++) {
|
|
|
|
qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i));
|
|
|
|
}
|
|
|
|
|
|
|
|
pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI);
|
2022-07-01 05:07:40 +02:00
|
|
|
qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
|
2022-06-06 14:43:25 +02:00
|
|
|
d = SYS_BUS_DEVICE(pch_msi);
|
|
|
|
sysbus_realize_and_unref(d, &error_fatal);
|
2022-07-29 09:30:18 +02:00
|
|
|
sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
|
2022-06-06 14:43:25 +02:00
|
|
|
for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
|
|
|
|
/* Connect 192 pch_msi irqs to extioi */
|
|
|
|
qdev_connect_gpio_out(DEVICE(d), i,
|
|
|
|
qdev_get_gpio_in(extioi, i + PCH_MSI_IRQ_START));
|
|
|
|
}
|
2022-06-06 14:43:27 +02:00
|
|
|
|
2022-07-12 10:32:05 +02:00
|
|
|
loongarch_devices_init(pch_pic, lams);
|
2022-06-06 14:43:25 +02:00
|
|
|
}
|
|
|
|
|
2022-07-12 10:32:02 +02:00
|
|
|
static void loongarch_firmware_init(LoongArchMachineState *lams)
|
|
|
|
{
|
|
|
|
char *filename = MACHINE(lams)->firmware;
|
|
|
|
char *bios_name = NULL;
|
|
|
|
int bios_size;
|
|
|
|
|
|
|
|
lams->bios_loaded = false;
|
|
|
|
if (filename) {
|
|
|
|
bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename);
|
|
|
|
if (!bios_name) {
|
|
|
|
error_report("Could not find ROM image '%s'", filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE);
|
|
|
|
if (bios_size < 0) {
|
|
|
|
error_report("Could not load ROM image '%s'", bios_name);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
g_free(bios_name);
|
|
|
|
|
|
|
|
memory_region_init_ram(&lams->bios, NULL, "loongarch.bios",
|
|
|
|
VIRT_BIOS_SIZE, &error_fatal);
|
|
|
|
memory_region_set_readonly(&lams->bios, true);
|
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios);
|
|
|
|
lams->bios_loaded = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2022-06-06 14:43:29 +02:00
|
|
|
static void reset_load_elf(void *opaque)
|
|
|
|
{
|
|
|
|
LoongArchCPU *cpu = opaque;
|
|
|
|
CPULoongArchState *env = &cpu->env;
|
|
|
|
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
if (env->load_elf) {
|
|
|
|
cpu_set_pc(CPU(cpu), env->elf_address);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-07-12 10:32:03 +02:00
|
|
|
/* Load an image file into an fw_cfg entry identified by key. */
|
|
|
|
static void load_image_to_fw_cfg(FWCfgState *fw_cfg, uint16_t size_key,
|
|
|
|
uint16_t data_key, const char *image_name,
|
|
|
|
bool try_decompress)
|
|
|
|
{
|
|
|
|
size_t size = -1;
|
|
|
|
uint8_t *data;
|
|
|
|
|
|
|
|
if (image_name == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (try_decompress) {
|
|
|
|
size = load_image_gzipped_buffer(image_name,
|
|
|
|
LOAD_IMAGE_MAX_GUNZIP_BYTES, &data);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (size == (size_t)-1) {
|
|
|
|
gchar *contents;
|
|
|
|
gsize length;
|
|
|
|
|
|
|
|
if (!g_file_get_contents(image_name, &contents, &length, NULL)) {
|
|
|
|
error_report("failed to load \"%s\"", image_name);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
size = length;
|
|
|
|
data = (uint8_t *)contents;
|
|
|
|
}
|
|
|
|
|
|
|
|
fw_cfg_add_i32(fw_cfg, size_key, size);
|
|
|
|
fw_cfg_add_bytes(fw_cfg, data_key, data, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Expose the kernel, the command line, and the initrd in fw_cfg.
|
|
|
|
* We don't process them here at all, it's all left to the
|
|
|
|
* firmware.
|
|
|
|
*/
|
|
|
|
load_image_to_fw_cfg(fw_cfg,
|
|
|
|
FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
|
|
|
|
loaderparams.kernel_filename,
|
|
|
|
false);
|
|
|
|
|
|
|
|
if (loaderparams.initrd_filename) {
|
|
|
|
load_image_to_fw_cfg(fw_cfg,
|
|
|
|
FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
|
|
|
|
loaderparams.initrd_filename, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (loaderparams.kernel_cmdline) {
|
|
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
|
|
|
strlen(loaderparams.kernel_cmdline) + 1);
|
|
|
|
fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
|
|
|
|
loaderparams.kernel_cmdline);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_firmware_boot(LoongArchMachineState *lams)
|
|
|
|
{
|
|
|
|
fw_cfg_add_kernel_info(lams->fw_cfg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_direct_kernel_boot(LoongArchMachineState *lams)
|
|
|
|
{
|
|
|
|
MachineState *machine = MACHINE(lams);
|
|
|
|
int64_t kernel_addr = 0;
|
|
|
|
LoongArchCPU *lacpu;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
kernel_addr = load_kernel_info();
|
|
|
|
if (!machine->firmware) {
|
|
|
|
for (i = 0; i < machine->smp.cpus; i++) {
|
|
|
|
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
|
|
|
|
lacpu->env.load_elf = true;
|
|
|
|
lacpu->env.elf_address = kernel_addr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-06 14:43:20 +02:00
|
|
|
static void loongarch_init(MachineState *machine)
|
|
|
|
{
|
2022-07-12 10:32:03 +02:00
|
|
|
LoongArchCPU *lacpu;
|
2022-06-06 14:43:20 +02:00
|
|
|
const char *cpu_model = machine->cpu_type;
|
|
|
|
ram_addr_t offset = 0;
|
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
|
|
uint64_t highram_size = 0;
|
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
LoongArchMachineState *lams = LOONGARCH_MACHINE(machine);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (!cpu_model) {
|
|
|
|
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!strstr(cpu_model, "la464")) {
|
|
|
|
error_report("LoongArch/TCG needs cpu type la464");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ram_size < 1 * GiB) {
|
|
|
|
error_report("ram_size must be greater than 1G.");
|
|
|
|
exit(1);
|
|
|
|
}
|
2022-07-12 10:32:06 +02:00
|
|
|
create_fdt(lams);
|
2022-06-06 14:43:20 +02:00
|
|
|
/* Init CPUs */
|
|
|
|
for (i = 0; i < machine->smp.cpus; i++) {
|
|
|
|
cpu_create(machine->cpu_type);
|
|
|
|
}
|
2022-07-12 10:32:06 +02:00
|
|
|
fdt_add_cpu_nodes(lams);
|
2022-06-06 14:43:20 +02:00
|
|
|
/* Add memory region */
|
|
|
|
memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram",
|
|
|
|
machine->ram, 0, 256 * MiB);
|
|
|
|
memory_region_add_subregion(address_space_mem, offset, &lams->lowmem);
|
|
|
|
offset += 256 * MiB;
|
2022-07-12 10:32:01 +02:00
|
|
|
memmap_add_entry(0, 256 * MiB, 1);
|
2022-06-06 14:43:20 +02:00
|
|
|
highram_size = ram_size - 256 * MiB;
|
|
|
|
memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem",
|
|
|
|
machine->ram, offset, highram_size);
|
|
|
|
memory_region_add_subregion(address_space_mem, 0x90000000, &lams->highmem);
|
2022-07-12 10:32:01 +02:00
|
|
|
memmap_add_entry(0x90000000, highram_size, 1);
|
2022-06-06 14:43:20 +02:00
|
|
|
/* Add isa io region */
|
|
|
|
memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
|
2022-07-29 09:30:18 +02:00
|
|
|
get_system_io(), 0, VIRT_ISA_IO_SIZE);
|
|
|
|
memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE,
|
2022-06-06 14:43:20 +02:00
|
|
|
&lams->isa_io);
|
2022-07-12 10:32:02 +02:00
|
|
|
/* load the BIOS image. */
|
|
|
|
loongarch_firmware_init(lams);
|
|
|
|
|
2022-07-12 10:32:01 +02:00
|
|
|
/* fw_cfg init */
|
|
|
|
lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine);
|
|
|
|
rom_set_fw(lams->fw_cfg);
|
|
|
|
if (lams->fw_cfg != NULL) {
|
|
|
|
fw_cfg_add_file(lams->fw_cfg, "etc/memmap",
|
|
|
|
memmap_table,
|
|
|
|
sizeof(struct memmap_entry) * (memmap_entries));
|
|
|
|
}
|
2022-07-12 10:32:06 +02:00
|
|
|
fdt_add_fw_cfg_node(lams);
|
2022-07-12 10:32:03 +02:00
|
|
|
loaderparams.ram_size = ram_size;
|
|
|
|
loaderparams.kernel_filename = machine->kernel_filename;
|
|
|
|
loaderparams.kernel_cmdline = machine->kernel_cmdline;
|
|
|
|
loaderparams.initrd_filename = machine->initrd_filename;
|
|
|
|
/* load the kernel. */
|
|
|
|
if (loaderparams.kernel_filename) {
|
|
|
|
if (lams->bios_loaded) {
|
|
|
|
loongarch_firmware_boot(lams);
|
|
|
|
} else {
|
|
|
|
loongarch_direct_kernel_boot(lams);
|
2022-06-06 14:43:29 +02:00
|
|
|
}
|
|
|
|
}
|
2022-07-12 10:32:03 +02:00
|
|
|
/* register reset function */
|
|
|
|
for (i = 0; i < machine->smp.cpus; i++) {
|
|
|
|
lacpu = LOONGARCH_CPU(qemu_get_cpu(i));
|
|
|
|
qemu_register_reset(reset_load_elf, lacpu);
|
|
|
|
}
|
2022-06-06 14:43:25 +02:00
|
|
|
/* Initialize the IO interrupt subsystem */
|
|
|
|
loongarch_irq_init(lams);
|
2022-07-12 10:32:04 +02:00
|
|
|
lams->machine_done.notify = virt_machine_done;
|
|
|
|
qemu_add_machine_init_done_notifier(&lams->machine_done);
|
2022-07-12 10:32:06 +02:00
|
|
|
fdt_add_pcie_node(lams);
|
|
|
|
|
|
|
|
/* load fdt */
|
|
|
|
MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
|
2022-07-29 09:30:18 +02:00
|
|
|
memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
|
|
|
|
memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
|
|
|
|
rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
|
2022-06-06 14:43:20 +02:00
|
|
|
}
|
|
|
|
|
2022-07-12 10:32:05 +02:00
|
|
|
bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
|
|
|
|
{
|
|
|
|
if (lams->acpi == ON_OFF_AUTO_OFF) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
|
|
|
|
OnOffAuto acpi = lams->acpi;
|
|
|
|
|
|
|
|
visit_type_OnOffAuto(v, name, &acpi, errp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name,
|
|
|
|
void *opaque, Error **errp)
|
|
|
|
{
|
|
|
|
LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
|
|
|
|
|
|
|
|
visit_type_OnOffAuto(v, name, &lams->acpi, errp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void loongarch_machine_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
LoongArchMachineState *lams = LOONGARCH_MACHINE(obj);
|
|
|
|
|
|
|
|
lams->acpi = ON_OFF_AUTO_AUTO;
|
|
|
|
lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
|
|
|
|
lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
|
|
|
|
}
|
|
|
|
|
2022-06-06 14:43:20 +02:00
|
|
|
static void loongarch_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
|
|
|
|
|
|
mc->desc = "Loongson-3A5000 LS7A1000 machine";
|
|
|
|
mc->init = loongarch_init;
|
|
|
|
mc->default_ram_size = 1 * GiB;
|
|
|
|
mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464");
|
|
|
|
mc->default_ram_id = "loongarch.ram";
|
|
|
|
mc->max_cpus = LOONGARCH_MAX_VCPUS;
|
|
|
|
mc->is_default = 1;
|
|
|
|
mc->default_kernel_irqchip_split = false;
|
|
|
|
mc->block_default_type = IF_VIRTIO;
|
|
|
|
mc->default_boot_order = "c";
|
|
|
|
mc->no_cdrom = 1;
|
2022-07-12 10:32:05 +02:00
|
|
|
|
|
|
|
object_class_property_add(oc, "acpi", "OnOffAuto",
|
|
|
|
loongarch_get_acpi, loongarch_set_acpi,
|
|
|
|
NULL, NULL);
|
|
|
|
object_class_property_set_description(oc, "acpi",
|
|
|
|
"Enable ACPI");
|
2022-06-06 14:43:20 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo loongarch_machine_types[] = {
|
|
|
|
{
|
|
|
|
.name = TYPE_LOONGARCH_MACHINE,
|
|
|
|
.parent = TYPE_MACHINE,
|
|
|
|
.instance_size = sizeof(LoongArchMachineState),
|
|
|
|
.class_init = loongarch_class_init,
|
2022-07-12 10:32:05 +02:00
|
|
|
.instance_init = loongarch_machine_initfn,
|
2022-06-06 14:43:20 +02:00
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
DEFINE_TYPES(loongarch_machine_types)
|