2013-10-15 22:03:04 +02:00
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/*
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* QEMU CG3 Frame buffer
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*
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* Copyright (c) 2012 Bob Breuer
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* Copyright (c) 2013 Mark Cave-Ayland
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2016-01-26 19:17:13 +01:00
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#include "qemu/osdep.h"
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2019-05-23 16:35:08 +02:00
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#include "qemu-common.h"
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include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
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2013-10-15 22:03:04 +02:00
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#include "qemu/error-report.h"
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#include "ui/console.h"
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#include "hw/sysbus.h"
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2019-08-12 07:23:45 +02:00
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#include "migration/vmstate.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2013-10-15 22:03:04 +02:00
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#include "hw/loader.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2015-12-15 13:16:16 +01:00
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#include "qemu/log.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2020-05-26 08:22:40 +02:00
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#include "trace.h"
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2013-10-15 22:03:04 +02:00
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/* Change to 1 to enable debugging */
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#define DEBUG_CG3 0
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#define CG3_ROM_FILE "QEMU,cgthree.bin"
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#define FCODE_MAX_ROM_SIZE 0x10000
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#define CG3_REG_SIZE 0x20
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#define CG3_REG_BT458_ADDR 0x0
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#define CG3_REG_BT458_COLMAP 0x4
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#define CG3_REG_FBC_CTRL 0x10
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#define CG3_REG_FBC_STATUS 0x11
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#define CG3_REG_FBC_CURSTART 0x12
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#define CG3_REG_FBC_CUREND 0x13
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#define CG3_REG_FBC_VCTRL 0x14
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/* Control register flags */
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#define CG3_CR_ENABLE_INTS 0x80
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/* Status register flags */
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#define CG3_SR_PENDING_INT 0x80
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#define CG3_SR_1152_900_76_B 0x60
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#define CG3_SR_ID_COLOR 0x01
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#define CG3_VRAM_SIZE 0x100000
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#define CG3_VRAM_OFFSET 0x800000
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#define TYPE_CG3 "cgthree"
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#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
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typedef struct CG3State {
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SysBusDevice parent_obj;
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QemuConsole *con;
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qemu_irq irq;
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hwaddr prom_addr;
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MemoryRegion vram_mem;
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MemoryRegion rom;
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MemoryRegion reg;
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uint32_t vram_size;
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int full_update;
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uint8_t regs[16];
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uint8_t r[256], g[256], b[256];
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uint16_t width, height, depth;
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uint8_t dac_index, dac_state;
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} CG3State;
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static void cg3_update_display(void *opaque)
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{
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CG3State *s = opaque;
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DisplaySurface *surface = qemu_console_surface(s->con);
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const uint8_t *pix;
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uint32_t *data;
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uint32_t dval;
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int x, y, y_start;
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unsigned int width, height;
|
2017-05-10 22:52:30 +02:00
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ram_addr_t page;
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DirtyBitmapSnapshot *snap = NULL;
|
2013-10-15 22:03:04 +02:00
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if (surface_bits_per_pixel(surface) != 32) {
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return;
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}
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width = s->width;
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height = s->height;
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y_start = -1;
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pix = memory_region_get_ram_ptr(&s->vram_mem);
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data = (uint32_t *)surface_data(surface);
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2017-05-10 22:52:30 +02:00
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if (!s->full_update) {
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snap = memory_region_snapshot_and_clear_dirty(&s->vram_mem, 0x0,
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memory_region_size(&s->vram_mem),
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DIRTY_MEMORY_VGA);
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}
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2013-10-15 22:03:04 +02:00
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for (y = 0; y < height; y++) {
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2017-05-10 22:52:30 +02:00
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int update;
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2013-10-15 22:03:04 +02:00
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2017-05-01 09:33:47 +02:00
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page = (ram_addr_t)y * width;
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2017-05-10 22:52:30 +02:00
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if (s->full_update) {
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update = 1;
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} else {
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update = memory_region_snapshot_get_dirty(&s->vram_mem, snap, page,
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width);
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}
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2013-10-15 22:03:04 +02:00
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if (update) {
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if (y_start < 0) {
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y_start = y;
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}
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for (x = 0; x < width; x++) {
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dval = *pix++;
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dval = (s->r[dval] << 16) | (s->g[dval] << 8) | s->b[dval];
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*data++ = dval;
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}
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} else {
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if (y_start >= 0) {
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2017-05-10 22:52:30 +02:00
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dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
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2013-10-15 22:03:04 +02:00
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y_start = -1;
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}
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pix += width;
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data += width;
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}
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}
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s->full_update = 0;
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if (y_start >= 0) {
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2017-05-10 22:52:30 +02:00
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dpy_gfx_update(s->con, 0, y_start, width, y - y_start);
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2013-10-15 22:03:04 +02:00
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}
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/* vsync interrupt? */
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if (s->regs[0] & CG3_CR_ENABLE_INTS) {
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s->regs[1] |= CG3_SR_PENDING_INT;
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qemu_irq_raise(s->irq);
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}
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2017-05-10 22:52:30 +02:00
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g_free(snap);
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2013-10-15 22:03:04 +02:00
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}
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static void cg3_invalidate_display(void *opaque)
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{
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CG3State *s = opaque;
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memory_region_set_dirty(&s->vram_mem, 0, CG3_VRAM_SIZE);
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}
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static uint64_t cg3_reg_read(void *opaque, hwaddr addr, unsigned size)
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{
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CG3State *s = opaque;
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int val;
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switch (addr) {
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case CG3_REG_BT458_ADDR:
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case CG3_REG_BT458_COLMAP:
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val = 0;
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break;
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case CG3_REG_FBC_CTRL:
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val = s->regs[0];
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break;
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case CG3_REG_FBC_STATUS:
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/* monitor ID 6, board type = 1 (color) */
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val = s->regs[1] | CG3_SR_1152_900_76_B | CG3_SR_ID_COLOR;
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break;
|
2014-05-24 12:51:50 +02:00
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case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
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2013-10-15 22:03:04 +02:00
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val = s->regs[addr - 0x10];
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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|
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"cg3: Unimplemented register read "
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|
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"reg 0x%" HWADDR_PRIx " size 0x%x\n",
|
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|
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addr, size);
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val = 0;
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break;
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}
|
2020-05-26 08:22:40 +02:00
|
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trace_cg3_read(addr, val, size);
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2013-10-15 22:03:04 +02:00
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return val;
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}
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static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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|
|
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{
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CG3State *s = opaque;
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uint8_t regval;
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int i;
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|
2020-05-26 08:22:40 +02:00
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trace_cg3_write(addr, val, size);
|
2013-10-15 22:03:04 +02:00
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switch (addr) {
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|
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case CG3_REG_BT458_ADDR:
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s->dac_index = val;
|
|
|
|
s->dac_state = 0;
|
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|
break;
|
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|
|
case CG3_REG_BT458_COLMAP:
|
|
|
|
/* This register can be written to as either a long word or a byte */
|
|
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if (size == 1) {
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|
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val <<= 24;
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}
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for (i = 0; i < size; i++) {
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regval = val >> 24;
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switch (s->dac_state) {
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|
|
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case 0:
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|
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s->r[s->dac_index] = regval;
|
|
|
|
s->dac_state++;
|
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break;
|
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case 1:
|
|
|
|
s->g[s->dac_index] = regval;
|
|
|
|
s->dac_state++;
|
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|
break;
|
|
|
|
case 2:
|
|
|
|
s->b[s->dac_index] = regval;
|
|
|
|
/* Index autoincrement */
|
|
|
|
s->dac_index = (s->dac_index + 1) & 0xff;
|
2018-08-01 17:14:09 +02:00
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|
|
/* fall through */
|
2013-10-15 22:03:04 +02:00
|
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default:
|
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|
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s->dac_state = 0;
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break;
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|
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}
|
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val <<= 8;
|
|
|
|
}
|
|
|
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s->full_update = 1;
|
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break;
|
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|
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case CG3_REG_FBC_CTRL:
|
|
|
|
s->regs[0] = val;
|
|
|
|
break;
|
|
|
|
case CG3_REG_FBC_STATUS:
|
|
|
|
if (s->regs[1] & CG3_SR_PENDING_INT) {
|
|
|
|
/* clear interrupt */
|
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|
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s->regs[1] &= ~CG3_SR_PENDING_INT;
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|
|
qemu_irq_lower(s->irq);
|
|
|
|
}
|
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|
break;
|
2014-05-24 12:51:50 +02:00
|
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|
case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE - 1:
|
2013-10-15 22:03:04 +02:00
|
|
|
s->regs[addr - 0x10] = val;
|
|
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break;
|
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|
default:
|
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"cg3: Unimplemented register write "
|
|
|
|
"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
|
|
|
|
addr, size, val);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps cg3_reg_ops = {
|
|
|
|
.read = cg3_reg_read,
|
|
|
|
.write = cg3_reg_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const GraphicHwOps cg3_ops = {
|
|
|
|
.invalidate = cg3_invalidate_display,
|
|
|
|
.gfx_update = cg3_update_display,
|
|
|
|
};
|
|
|
|
|
2014-05-24 12:42:36 +02:00
|
|
|
static void cg3_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
CG3State *s = CG3(obj);
|
|
|
|
|
2020-02-24 19:50:29 +01:00
|
|
|
memory_region_init_rom_nomigrate(&s->rom, obj, "cg3.prom",
|
|
|
|
FCODE_MAX_ROM_SIZE, &error_fatal);
|
2014-05-24 12:42:36 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->rom);
|
|
|
|
|
2015-10-01 10:59:51 +02:00
|
|
|
memory_region_init_io(&s->reg, obj, &cg3_reg_ops, s, "cg3.reg",
|
2014-05-24 12:42:36 +02:00
|
|
|
CG3_REG_SIZE);
|
|
|
|
sysbus_init_mmio(sbd, &s->reg);
|
|
|
|
}
|
|
|
|
|
2013-10-15 22:03:04 +02:00
|
|
|
static void cg3_realizefn(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
CG3State *s = CG3(dev);
|
|
|
|
int ret;
|
|
|
|
char *fcode_filename;
|
|
|
|
|
|
|
|
/* FCode ROM */
|
|
|
|
vmstate_register_ram_global(&s->rom);
|
|
|
|
fcode_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, CG3_ROM_FILE);
|
|
|
|
if (fcode_filename) {
|
2017-04-05 10:02:46 +02:00
|
|
|
ret = load_image_mr(fcode_filename, &s->rom);
|
2015-05-28 13:13:42 +02:00
|
|
|
g_free(fcode_filename);
|
2013-10-15 22:03:04 +02:00
|
|
|
if (ret < 0 || ret > FCODE_MAX_ROM_SIZE) {
|
2018-10-17 10:26:28 +02:00
|
|
|
warn_report("cg3: could not load prom '%s'", CG3_ROM_FILE);
|
2013-10-15 22:03:04 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size,
|
Fix bad error handling after memory_region_init_ram()
Symptom:
$ qemu-system-x86_64 -m 10000000
Unexpected error in ram_block_add() at /work/armbru/qemu/exec.c:1456:
upstream-qemu: cannot set up guest memory 'pc.ram': Cannot allocate memory
Aborted (core dumped)
Root cause: commit ef701d7 screwed up handling of out-of-memory
conditions. Before the commit, we report the error and exit(1), in
one place, ram_block_add(). The commit lifts the error handling up
the call chain some, to three places. Fine. Except it uses
&error_abort in these places, changing the behavior from exit(1) to
abort(), and thus undoing the work of commit 3922825 "exec: Don't
abort when we can't allocate guest memory".
The three places are:
* memory_region_init_ram()
Commit 4994653 (right after commit ef701d7) lifted the error
handling further, through memory_region_init_ram(), multiplying the
incorrect use of &error_abort. Later on, imitation of existing
(bad) code may have created more.
* memory_region_init_ram_ptr()
The &error_abort is still there.
* memory_region_init_rom_device()
Doesn't need fixing, because commit 33e0eb5 (soon after commit
ef701d7) lifted the error handling further, and in the process
changed it from &error_abort to passing it up the call chain.
Correct, because the callers are realize() methods.
Fix the error handling after memory_region_init_ram() with a
Coccinelle semantic patch:
@r@
expression mr, owner, name, size, err;
position p;
@@
memory_region_init_ram(mr, owner, name, size,
(
- &error_abort
+ &error_fatal
|
err@p
)
);
@script:python@
p << r.p;
@@
print "%s:%s:%s" % (p[0].file, p[0].line, p[0].column)
When the last argument is &error_abort, it gets replaced by
&error_fatal. This is the fix.
If the last argument is anything else, its position is reported. This
lets us check the fix is complete. Four positions get reported:
* ram_backend_memory_alloc()
Error is passed up the call chain, ultimately through
user_creatable_complete(). As far as I can tell, it's callers all
handle the error sanely.
* fsl_imx25_realize(), fsl_imx31_realize(), dp8393x_realize()
DeviceClass.realize() methods, errors handled sanely further up the
call chain.
We're good. Test case again behaves:
$ qemu-system-x86_64 -m 10000000
qemu-system-x86_64: cannot set up guest memory 'pc.ram': Cannot allocate memory
[Exit 1 ]
The next commits will repair the rest of commit ef701d7's damage.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <1441983105-26376-3-git-send-email-armbru@redhat.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
2015-09-11 16:51:43 +02:00
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&error_fatal);
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2015-03-23 10:47:45 +01:00
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memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA);
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2013-10-15 22:03:04 +02:00
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sysbus_init_mmio(sbd, &s->vram_mem);
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sysbus_init_irq(sbd, &s->irq);
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2020-05-12 09:00:20 +02:00
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s->con = graphic_console_init(dev, 0, &cg3_ops, s);
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2013-10-15 22:03:04 +02:00
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qemu_console_resize(s->con, s->width, s->height);
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}
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static int vmstate_cg3_post_load(void *opaque, int version_id)
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{
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CG3State *s = opaque;
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cg3_invalidate_display(s);
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return 0;
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}
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static const VMStateDescription vmstate_cg3 = {
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.name = "cg3",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = vmstate_cg3_post_load,
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2014-04-16 16:01:33 +02:00
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.fields = (VMStateField[]) {
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2013-10-15 22:03:04 +02:00
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VMSTATE_UINT16(height, CG3State),
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VMSTATE_UINT16(width, CG3State),
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VMSTATE_UINT16(depth, CG3State),
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VMSTATE_BUFFER(r, CG3State),
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VMSTATE_BUFFER(g, CG3State),
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VMSTATE_BUFFER(b, CG3State),
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VMSTATE_UINT8(dac_index, CG3State),
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VMSTATE_UINT8(dac_state, CG3State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void cg3_reset(DeviceState *d)
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{
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CG3State *s = CG3(d);
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/* Initialize palette */
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memset(s->r, 0, 256);
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memset(s->g, 0, 256);
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memset(s->b, 0, 256);
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s->dac_state = 0;
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s->full_update = 1;
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qemu_irq_lower(s->irq);
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}
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static Property cg3_properties[] = {
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DEFINE_PROP_UINT32("vram-size", CG3State, vram_size, -1),
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DEFINE_PROP_UINT16("width", CG3State, width, -1),
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DEFINE_PROP_UINT16("height", CG3State, height, -1),
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DEFINE_PROP_UINT16("depth", CG3State, depth, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cg3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = cg3_realizefn;
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dc->reset = cg3_reset;
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dc->vmsd = &vmstate_cg3;
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2020-01-10 16:30:32 +01:00
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device_class_set_props(dc, cg3_properties);
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2013-10-15 22:03:04 +02:00
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}
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static const TypeInfo cg3_info = {
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.name = TYPE_CG3,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(CG3State),
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2014-05-24 12:42:36 +02:00
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.instance_init = cg3_initfn,
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2013-10-15 22:03:04 +02:00
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.class_init = cg3_class_init,
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};
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static void cg3_register_types(void)
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{
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type_register_static(&cg3_info);
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}
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type_init(cg3_register_types)
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