2012-04-29 20:20:34 +02:00
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/*
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* x86 misc helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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2014-04-08 07:31:41 +02:00
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#include "exec/helper-proto.h"
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2014-03-28 19:42:10 +01:00
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#include "exec/cpu_ldst.h"
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2015-04-08 14:45:53 +02:00
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#include "exec/address-spaces.h"
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2012-04-29 22:35:48 +02:00
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2015-04-08 14:45:53 +02:00
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void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
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#else
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address_space_stb(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2015-04-08 14:45:53 +02:00
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target_ulong helper_inb(CPUX86State *env, uint32_t port)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "inb: port=0x%04x\n", port);
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return 0;
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#else
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return address_space_ldub(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2015-04-08 14:45:53 +02:00
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void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
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#else
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address_space_stw(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2015-04-08 14:45:53 +02:00
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target_ulong helper_inw(CPUX86State *env, uint32_t port)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "inw: port=0x%04x\n", port);
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return 0;
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#else
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return address_space_lduw(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2015-04-08 14:45:53 +02:00
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void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "outw: port=0x%04x, data=%08x\n", port, data);
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#else
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address_space_stl(&address_space_io, port, data,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2015-04-08 14:45:53 +02:00
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target_ulong helper_inl(CPUX86State *env, uint32_t port)
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2012-04-29 20:20:34 +02:00
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{
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2015-04-08 14:45:53 +02:00
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#ifdef CONFIG_USER_ONLY
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fprintf(stderr, "inl: port=0x%04x\n", port);
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return 0;
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#else
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return address_space_ldl(&address_space_io, port,
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cpu_get_mem_attrs(env), NULL);
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#endif
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_into(CPUX86State *env, int next_eip_addend)
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2012-04-29 20:20:34 +02:00
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{
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int eflags;
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2012-04-29 14:45:34 +02:00
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eflags = cpu_cc_compute_all(env, CC_OP);
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2012-04-29 20:20:34 +02:00
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if (eflags & CC_O) {
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raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
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}
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}
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2012-04-29 20:42:47 +02:00
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void helper_single_step(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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#ifndef CONFIG_USER_ONLY
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2013-01-15 06:39:56 +01:00
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check_hw_breakpoints(env, true);
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2012-04-29 20:20:34 +02:00
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env->dr[6] |= DR6_BS;
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#endif
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raise_exception(env, EXCP01_DB);
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}
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2012-04-29 20:42:47 +02:00
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void helper_cpuid(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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uint32_t eax, ebx, ecx, edx;
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cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0);
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2013-05-28 10:21:10 +02:00
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cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
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&eax, &ebx, &ecx, &edx);
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2013-05-28 10:20:59 +02:00
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env->regs[R_EAX] = eax;
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2013-05-28 10:21:00 +02:00
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env->regs[R_EBX] = ebx;
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2013-05-28 10:21:01 +02:00
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env->regs[R_ECX] = ecx;
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2013-05-28 10:21:02 +02:00
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env->regs[R_EDX] = edx;
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2012-04-29 20:20:34 +02:00
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}
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#if defined(CONFIG_USER_ONLY)
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2012-04-29 20:42:47 +02:00
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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2012-04-29 20:20:34 +02:00
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{
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return 0;
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}
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2012-04-29 20:42:47 +02:00
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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2012-04-29 20:20:34 +02:00
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{
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}
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2012-04-29 20:42:47 +02:00
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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2012-04-29 20:20:34 +02:00
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{
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}
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#else
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2012-04-29 20:42:47 +02:00
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target_ulong helper_read_crN(CPUX86State *env, int reg)
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2012-04-29 20:20:34 +02:00
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{
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target_ulong val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0);
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switch (reg) {
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default:
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val = env->cr[reg];
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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2013-12-23 10:04:02 +01:00
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val = cpu_get_apic_tpr(x86_env_get_cpu(env)->apic_state);
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2012-04-29 20:20:34 +02:00
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} else {
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val = env->v_tpr;
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}
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break;
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}
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return val;
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}
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2012-04-29 20:42:47 +02:00
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void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
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2012-04-29 20:20:34 +02:00
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{
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cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0);
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switch (reg) {
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case 0:
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cpu_x86_update_cr0(env, t0);
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break;
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case 3:
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cpu_x86_update_cr3(env, t0);
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break;
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case 4:
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cpu_x86_update_cr4(env, t0);
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break;
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case 8:
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if (!(env->hflags2 & HF2_VINTR_MASK)) {
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2013-12-23 10:04:02 +01:00
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cpu_set_apic_tpr(x86_env_get_cpu(env)->apic_state, t0);
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2012-04-29 20:20:34 +02:00
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}
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env->v_tpr = t0 & 0x0f;
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break;
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default:
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env->cr[reg] = t0;
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break;
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}
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}
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2012-04-29 20:42:47 +02:00
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void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0)
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2012-04-29 20:20:34 +02:00
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{
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int i;
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if (reg < 4) {
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hw_breakpoint_remove(env, reg);
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env->dr[reg] = t0;
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hw_breakpoint_insert(env, reg);
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} else if (reg == 7) {
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2013-01-15 06:39:55 +01:00
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for (i = 0; i < DR7_MAX_BP; i++) {
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2012-04-29 20:20:34 +02:00
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hw_breakpoint_remove(env, i);
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}
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env->dr[7] = t0;
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2013-01-15 06:39:55 +01:00
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for (i = 0; i < DR7_MAX_BP; i++) {
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2012-04-29 20:20:34 +02:00
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hw_breakpoint_insert(env, i);
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}
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} else {
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env->dr[reg] = t0;
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}
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}
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#endif
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2012-04-29 20:42:47 +02:00
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void helper_lmsw(CPUX86State *env, target_ulong t0)
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2012-04-29 20:20:34 +02:00
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{
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/* only 4 lower bits of CR0 are modified. PE cannot be set to zero
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if already set to one. */
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t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
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2012-04-29 20:42:47 +02:00
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helper_write_crN(env, 0, t0);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_invlpg(CPUX86State *env, target_ulong addr)
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2012-04-29 20:20:34 +02:00
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{
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2013-09-04 01:29:02 +02:00
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X86CPU *cpu = x86_env_get_cpu(env);
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2012-04-29 20:20:34 +02:00
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cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
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2013-09-04 01:29:02 +02:00
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tlb_flush_page(CPU(cpu), addr);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_rdtsc(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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uint64_t val;
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if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
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2015-07-10 11:57:41 +02:00
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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2012-04-29 20:20:34 +02:00
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}
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0);
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val = cpu_get_tsc(env) + env->tsc_offset;
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2013-05-28 10:20:59 +02:00
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env->regs[R_EAX] = (uint32_t)(val);
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2013-05-28 10:21:02 +02:00
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env->regs[R_EDX] = (uint32_t)(val >> 32);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_rdtscp(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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2012-04-29 20:42:47 +02:00
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helper_rdtsc(env);
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2013-05-28 10:21:01 +02:00
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env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_rdpmc(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
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2015-07-10 11:57:41 +02:00
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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2012-04-29 20:20:34 +02:00
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}
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cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0);
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/* currently unimplemented */
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qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
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raise_exception_err(env, EXCP06_ILLOP, 0);
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}
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#if defined(CONFIG_USER_ONLY)
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2012-04-29 20:42:47 +02:00
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void helper_wrmsr(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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}
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2012-04-29 20:42:47 +02:00
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void helper_rdmsr(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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}
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#else
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2012-04-29 20:42:47 +02:00
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void helper_wrmsr(CPUX86State *env)
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2012-04-29 20:20:34 +02:00
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{
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uint64_t val;
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cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1);
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2013-05-28 10:21:10 +02:00
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val = ((uint32_t)env->regs[R_EAX]) |
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((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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2012-04-29 20:20:34 +02:00
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2013-05-28 10:21:01 +02:00
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switch ((uint32_t)env->regs[R_ECX]) {
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2012-04-29 20:20:34 +02:00
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case MSR_IA32_SYSENTER_CS:
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env->sysenter_cs = val & 0xffff;
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break;
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case MSR_IA32_SYSENTER_ESP:
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env->sysenter_esp = val;
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break;
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case MSR_IA32_SYSENTER_EIP:
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env->sysenter_eip = val;
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break;
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case MSR_IA32_APICBASE:
|
2013-12-23 10:04:02 +01:00
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cpu_set_apic_base(x86_env_get_cpu(env)->apic_state, val);
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2012-04-29 20:20:34 +02:00
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break;
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case MSR_EFER:
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{
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uint64_t update_mask;
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update_mask = 0;
|
2013-04-22 21:00:15 +02:00
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
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2012-04-29 20:20:34 +02:00
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update_mask |= MSR_EFER_SCE;
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}
|
2013-04-22 21:00:15 +02:00
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if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
|
2012-04-29 20:20:34 +02:00
|
|
|
update_mask |= MSR_EFER_LME;
|
|
|
|
}
|
2013-04-22 21:00:15 +02:00
|
|
|
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
|
2012-04-29 20:20:34 +02:00
|
|
|
update_mask |= MSR_EFER_FFXSR;
|
|
|
|
}
|
2013-04-22 21:00:15 +02:00
|
|
|
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
|
2012-04-29 20:20:34 +02:00
|
|
|
update_mask |= MSR_EFER_NXE;
|
|
|
|
}
|
2013-04-22 21:00:15 +02:00
|
|
|
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
|
2012-04-29 20:20:34 +02:00
|
|
|
update_mask |= MSR_EFER_SVME;
|
|
|
|
}
|
2013-04-22 21:00:15 +02:00
|
|
|
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
|
2012-04-29 20:20:34 +02:00
|
|
|
update_mask |= MSR_EFER_FFXSR;
|
|
|
|
}
|
|
|
|
cpu_load_efer(env, (env->efer & ~update_mask) |
|
|
|
|
(val & update_mask));
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSR_STAR:
|
|
|
|
env->star = val;
|
|
|
|
break;
|
|
|
|
case MSR_PAT:
|
|
|
|
env->pat = val;
|
|
|
|
break;
|
|
|
|
case MSR_VM_HSAVE_PA:
|
|
|
|
env->vm_hsave = val;
|
|
|
|
break;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
case MSR_LSTAR:
|
|
|
|
env->lstar = val;
|
|
|
|
break;
|
|
|
|
case MSR_CSTAR:
|
|
|
|
env->cstar = val;
|
|
|
|
break;
|
|
|
|
case MSR_FMASK:
|
|
|
|
env->fmask = val;
|
|
|
|
break;
|
|
|
|
case MSR_FSBASE:
|
|
|
|
env->segs[R_FS].base = val;
|
|
|
|
break;
|
|
|
|
case MSR_GSBASE:
|
|
|
|
env->segs[R_GS].base = val;
|
|
|
|
break;
|
|
|
|
case MSR_KERNELGSBASE:
|
|
|
|
env->kernelgsbase = val;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
case MSR_MTRRphysBase(0):
|
|
|
|
case MSR_MTRRphysBase(1):
|
|
|
|
case MSR_MTRRphysBase(2):
|
|
|
|
case MSR_MTRRphysBase(3):
|
|
|
|
case MSR_MTRRphysBase(4):
|
|
|
|
case MSR_MTRRphysBase(5):
|
|
|
|
case MSR_MTRRphysBase(6):
|
|
|
|
case MSR_MTRRphysBase(7):
|
2013-05-28 10:21:10 +02:00
|
|
|
env->mtrr_var[((uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRphysBase(0)) / 2].base = val;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRphysMask(0):
|
|
|
|
case MSR_MTRRphysMask(1):
|
|
|
|
case MSR_MTRRphysMask(2):
|
|
|
|
case MSR_MTRRphysMask(3):
|
|
|
|
case MSR_MTRRphysMask(4):
|
|
|
|
case MSR_MTRRphysMask(5):
|
|
|
|
case MSR_MTRRphysMask(6):
|
|
|
|
case MSR_MTRRphysMask(7):
|
2013-05-28 10:21:10 +02:00
|
|
|
env->mtrr_var[((uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRphysMask(0)) / 2].mask = val;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRfix64K_00000:
|
2013-05-28 10:21:10 +02:00
|
|
|
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRfix64K_00000] = val;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRfix16K_80000:
|
|
|
|
case MSR_MTRRfix16K_A0000:
|
2013-05-28 10:21:10 +02:00
|
|
|
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRfix16K_80000 + 1] = val;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRfix4K_C0000:
|
|
|
|
case MSR_MTRRfix4K_C8000:
|
|
|
|
case MSR_MTRRfix4K_D0000:
|
|
|
|
case MSR_MTRRfix4K_D8000:
|
|
|
|
case MSR_MTRRfix4K_E0000:
|
|
|
|
case MSR_MTRRfix4K_E8000:
|
|
|
|
case MSR_MTRRfix4K_F0000:
|
|
|
|
case MSR_MTRRfix4K_F8000:
|
2013-05-28 10:21:10 +02:00
|
|
|
env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRfix4K_C0000 + 3] = val;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRdefType:
|
|
|
|
env->mtrr_deftype = val;
|
|
|
|
break;
|
|
|
|
case MSR_MCG_STATUS:
|
|
|
|
env->mcg_status = val;
|
|
|
|
break;
|
|
|
|
case MSR_MCG_CTL:
|
|
|
|
if ((env->mcg_cap & MCG_CTL_P)
|
|
|
|
&& (val == 0 || val == ~(uint64_t)0)) {
|
|
|
|
env->mcg_ctl = val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSR_TSC_AUX:
|
|
|
|
env->tsc_aux = val;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_MISC_ENABLE:
|
|
|
|
env->msr_ia32_misc_enable = val;
|
|
|
|
break;
|
|
|
|
default:
|
2013-05-28 10:21:01 +02:00
|
|
|
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
|
2013-05-28 10:21:10 +02:00
|
|
|
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
|
|
|
|
(4 * env->mcg_cap & 0xff)) {
|
2013-05-28 10:21:01 +02:00
|
|
|
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
|
2012-04-29 20:20:34 +02:00
|
|
|
if ((offset & 0x3) != 0
|
|
|
|
|| (val == 0 || val == ~(uint64_t)0)) {
|
|
|
|
env->mce_banks[offset] = val;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* XXX: exception? */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-04-29 20:42:47 +02:00
|
|
|
void helper_rdmsr(CPUX86State *env)
|
2012-04-29 20:20:34 +02:00
|
|
|
{
|
|
|
|
uint64_t val;
|
|
|
|
|
|
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0);
|
|
|
|
|
2013-05-28 10:21:01 +02:00
|
|
|
switch ((uint32_t)env->regs[R_ECX]) {
|
2012-04-29 20:20:34 +02:00
|
|
|
case MSR_IA32_SYSENTER_CS:
|
|
|
|
val = env->sysenter_cs;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_SYSENTER_ESP:
|
|
|
|
val = env->sysenter_esp;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_SYSENTER_EIP:
|
|
|
|
val = env->sysenter_eip;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_APICBASE:
|
2013-12-23 10:04:02 +01:00
|
|
|
val = cpu_get_apic_base(x86_env_get_cpu(env)->apic_state);
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_EFER:
|
|
|
|
val = env->efer;
|
|
|
|
break;
|
|
|
|
case MSR_STAR:
|
|
|
|
val = env->star;
|
|
|
|
break;
|
|
|
|
case MSR_PAT:
|
|
|
|
val = env->pat;
|
|
|
|
break;
|
|
|
|
case MSR_VM_HSAVE_PA:
|
|
|
|
val = env->vm_hsave;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_PERF_STATUS:
|
|
|
|
/* tsc_increment_by_tick */
|
|
|
|
val = 1000ULL;
|
|
|
|
/* CPU multiplier */
|
|
|
|
val |= (((uint64_t)4ULL) << 40);
|
|
|
|
break;
|
|
|
|
#ifdef TARGET_X86_64
|
|
|
|
case MSR_LSTAR:
|
|
|
|
val = env->lstar;
|
|
|
|
break;
|
|
|
|
case MSR_CSTAR:
|
|
|
|
val = env->cstar;
|
|
|
|
break;
|
|
|
|
case MSR_FMASK:
|
|
|
|
val = env->fmask;
|
|
|
|
break;
|
|
|
|
case MSR_FSBASE:
|
|
|
|
val = env->segs[R_FS].base;
|
|
|
|
break;
|
|
|
|
case MSR_GSBASE:
|
|
|
|
val = env->segs[R_GS].base;
|
|
|
|
break;
|
|
|
|
case MSR_KERNELGSBASE:
|
|
|
|
val = env->kernelgsbase;
|
|
|
|
break;
|
|
|
|
case MSR_TSC_AUX:
|
|
|
|
val = env->tsc_aux;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
case MSR_MTRRphysBase(0):
|
|
|
|
case MSR_MTRRphysBase(1):
|
|
|
|
case MSR_MTRRphysBase(2):
|
|
|
|
case MSR_MTRRphysBase(3):
|
|
|
|
case MSR_MTRRphysBase(4):
|
|
|
|
case MSR_MTRRphysBase(5):
|
|
|
|
case MSR_MTRRphysBase(6):
|
|
|
|
case MSR_MTRRphysBase(7):
|
2013-05-28 10:21:10 +02:00
|
|
|
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRphysBase(0)) / 2].base;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRphysMask(0):
|
|
|
|
case MSR_MTRRphysMask(1):
|
|
|
|
case MSR_MTRRphysMask(2):
|
|
|
|
case MSR_MTRRphysMask(3):
|
|
|
|
case MSR_MTRRphysMask(4):
|
|
|
|
case MSR_MTRRphysMask(5):
|
|
|
|
case MSR_MTRRphysMask(6):
|
|
|
|
case MSR_MTRRphysMask(7):
|
2013-05-28 10:21:10 +02:00
|
|
|
val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRphysMask(0)) / 2].mask;
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRfix64K_00000:
|
|
|
|
val = env->mtrr_fixed[0];
|
|
|
|
break;
|
|
|
|
case MSR_MTRRfix16K_80000:
|
|
|
|
case MSR_MTRRfix16K_A0000:
|
2013-05-28 10:21:10 +02:00
|
|
|
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRfix16K_80000 + 1];
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRfix4K_C0000:
|
|
|
|
case MSR_MTRRfix4K_C8000:
|
|
|
|
case MSR_MTRRfix4K_D0000:
|
|
|
|
case MSR_MTRRfix4K_D8000:
|
|
|
|
case MSR_MTRRfix4K_E0000:
|
|
|
|
case MSR_MTRRfix4K_E8000:
|
|
|
|
case MSR_MTRRfix4K_F0000:
|
|
|
|
case MSR_MTRRfix4K_F8000:
|
2013-05-28 10:21:10 +02:00
|
|
|
val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
|
|
|
|
MSR_MTRRfix4K_C0000 + 3];
|
2012-04-29 20:20:34 +02:00
|
|
|
break;
|
|
|
|
case MSR_MTRRdefType:
|
|
|
|
val = env->mtrr_deftype;
|
|
|
|
break;
|
|
|
|
case MSR_MTRRcap:
|
2013-04-22 21:00:15 +02:00
|
|
|
if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
|
2012-04-29 20:20:34 +02:00
|
|
|
val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
|
|
|
|
MSR_MTRRcap_WC_SUPPORTED;
|
|
|
|
} else {
|
|
|
|
/* XXX: exception? */
|
|
|
|
val = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSR_MCG_CAP:
|
|
|
|
val = env->mcg_cap;
|
|
|
|
break;
|
|
|
|
case MSR_MCG_CTL:
|
|
|
|
if (env->mcg_cap & MCG_CTL_P) {
|
|
|
|
val = env->mcg_ctl;
|
|
|
|
} else {
|
|
|
|
val = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case MSR_MCG_STATUS:
|
|
|
|
val = env->mcg_status;
|
|
|
|
break;
|
|
|
|
case MSR_IA32_MISC_ENABLE:
|
|
|
|
val = env->msr_ia32_misc_enable;
|
|
|
|
break;
|
|
|
|
default:
|
2013-05-28 10:21:01 +02:00
|
|
|
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
|
2013-05-28 10:21:10 +02:00
|
|
|
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
|
|
|
|
(4 * env->mcg_cap & 0xff)) {
|
2013-05-28 10:21:01 +02:00
|
|
|
uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
|
2012-04-29 20:20:34 +02:00
|
|
|
val = env->mce_banks[offset];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
/* XXX: exception? */
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
}
|
2013-05-28 10:20:59 +02:00
|
|
|
env->regs[R_EAX] = (uint32_t)(val);
|
2013-05-28 10:21:02 +02:00
|
|
|
env->regs[R_EDX] = (uint32_t)(val >> 32);
|
2012-04-29 20:20:34 +02:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify
or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
tick, but the timers are only the trigger for a pre-existing problem.
Before the offending patch, setting a timer did a timer_settime system call.
After, setting the timer exits the event loop (which uses poll) and
reenters it with a new deadline. This does not cause any slowdown; the
difference is between one system call (timer_settime and a signal
delivery (SIGALRM) before the patch, and two system calls afterwards
(write to a pipe or eventfd + calling poll again when re-entering the
event loop).
Unfortunately, the exit/enter causes the main loop to grab the iothread
lock, which in turns kicks the VCPU thread out of execution. This
causes TCG to execute the next VCPU in its round-robin scheduling of
VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause"
instruction in its idle loop which only burns cycles without any
progress. As soon as the timer tick expires, the first VCPU runs
the interrupt handler but very soon it sets it again---and QEMU
then goes back doing nothing in the second VCPU.
The fix is to make the pause instruction do "cpu_loop_exit".
Cc: Richard Henderson <rth@twiddle.net>
Reported-by: Luigi Rizzo <rizzo@iet.unipi.it>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-20 12:54:02 +01:00
|
|
|
static void do_pause(X86CPU *cpu)
|
|
|
|
{
|
2013-08-26 08:31:06 +02:00
|
|
|
CPUState *cs = CPU(cpu);
|
target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify
or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
tick, but the timers are only the trigger for a pre-existing problem.
Before the offending patch, setting a timer did a timer_settime system call.
After, setting the timer exits the event loop (which uses poll) and
reenters it with a new deadline. This does not cause any slowdown; the
difference is between one system call (timer_settime and a signal
delivery (SIGALRM) before the patch, and two system calls afterwards
(write to a pipe or eventfd + calling poll again when re-entering the
event loop).
Unfortunately, the exit/enter causes the main loop to grab the iothread
lock, which in turns kicks the VCPU thread out of execution. This
causes TCG to execute the next VCPU in its round-robin scheduling of
VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause"
instruction in its idle loop which only burns cycles without any
progress. As soon as the timer tick expires, the first VCPU runs
the interrupt handler but very soon it sets it again---and QEMU
then goes back doing nothing in the second VCPU.
The fix is to make the pause instruction do "cpu_loop_exit".
Cc: Richard Henderson <rth@twiddle.net>
Reported-by: Luigi Rizzo <rizzo@iet.unipi.it>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-20 12:54:02 +01:00
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/* Just let another CPU run. */
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2013-08-26 08:31:06 +02:00
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cs->exception_index = EXCP_INTERRUPT;
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2013-08-27 17:52:12 +02:00
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cpu_loop_exit(cs);
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target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify
or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
tick, but the timers are only the trigger for a pre-existing problem.
Before the offending patch, setting a timer did a timer_settime system call.
After, setting the timer exits the event loop (which uses poll) and
reenters it with a new deadline. This does not cause any slowdown; the
difference is between one system call (timer_settime and a signal
delivery (SIGALRM) before the patch, and two system calls afterwards
(write to a pipe or eventfd + calling poll again when re-entering the
event loop).
Unfortunately, the exit/enter causes the main loop to grab the iothread
lock, which in turns kicks the VCPU thread out of execution. This
causes TCG to execute the next VCPU in its round-robin scheduling of
VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause"
instruction in its idle loop which only burns cycles without any
progress. As soon as the timer tick expires, the first VCPU runs
the interrupt handler but very soon it sets it again---and QEMU
then goes back doing nothing in the second VCPU.
The fix is to make the pause instruction do "cpu_loop_exit".
Cc: Richard Henderson <rth@twiddle.net>
Reported-by: Luigi Rizzo <rizzo@iet.unipi.it>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-20 12:54:02 +01:00
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}
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2013-01-17 18:51:17 +01:00
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static void do_hlt(X86CPU *cpu)
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2012-04-29 20:20:34 +02:00
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{
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2013-01-17 18:51:17 +01:00
|
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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2012-04-29 20:20:34 +02:00
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env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
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2013-01-17 18:51:17 +01:00
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cs->halted = 1;
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2013-08-26 08:31:06 +02:00
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cs->exception_index = EXCP_HLT;
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2013-08-27 17:52:12 +02:00
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cpu_loop_exit(cs);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_hlt(CPUX86State *env, int next_eip_addend)
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2012-04-29 20:20:34 +02:00
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{
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2013-01-17 18:51:17 +01:00
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X86CPU *cpu = x86_env_get_cpu(env);
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2012-04-29 20:20:34 +02:00
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cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0);
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2013-05-28 10:21:07 +02:00
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env->eip += next_eip_addend;
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2012-04-29 20:20:34 +02:00
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2013-01-17 18:51:17 +01:00
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do_hlt(cpu);
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2012-04-29 20:20:34 +02:00
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}
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2012-04-29 20:42:47 +02:00
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void helper_monitor(CPUX86State *env, target_ulong ptr)
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2012-04-29 20:20:34 +02:00
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{
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2013-05-28 10:21:01 +02:00
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if ((uint32_t)env->regs[R_ECX] != 0) {
|
2015-07-10 11:57:41 +02:00
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
|
2012-04-29 20:20:34 +02:00
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}
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/* XXX: store address? */
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cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0);
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}
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2012-04-29 20:42:47 +02:00
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void helper_mwait(CPUX86State *env, int next_eip_addend)
|
2012-04-29 20:20:34 +02:00
|
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{
|
2013-01-17 18:51:17 +01:00
|
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CPUState *cs;
|
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X86CPU *cpu;
|
2012-12-17 06:18:02 +01:00
|
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|
2013-05-28 10:21:01 +02:00
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if ((uint32_t)env->regs[R_ECX] != 0) {
|
2015-07-10 11:57:41 +02:00
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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2012-04-29 20:20:34 +02:00
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}
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cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0);
|
2013-05-28 10:21:07 +02:00
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env->eip += next_eip_addend;
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2012-04-29 20:20:34 +02:00
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2013-01-17 18:51:17 +01:00
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cpu = x86_env_get_cpu(env);
|
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cs = CPU(cpu);
|
2012-04-29 20:20:34 +02:00
|
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/* XXX: not complete but not completely erroneous */
|
2013-06-24 23:50:24 +02:00
|
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if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
|
target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify
or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
tick, but the timers are only the trigger for a pre-existing problem.
Before the offending patch, setting a timer did a timer_settime system call.
After, setting the timer exits the event loop (which uses poll) and
reenters it with a new deadline. This does not cause any slowdown; the
difference is between one system call (timer_settime and a signal
delivery (SIGALRM) before the patch, and two system calls afterwards
(write to a pipe or eventfd + calling poll again when re-entering the
event loop).
Unfortunately, the exit/enter causes the main loop to grab the iothread
lock, which in turns kicks the VCPU thread out of execution. This
causes TCG to execute the next VCPU in its round-robin scheduling of
VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause"
instruction in its idle loop which only burns cycles without any
progress. As soon as the timer tick expires, the first VCPU runs
the interrupt handler but very soon it sets it again---and QEMU
then goes back doing nothing in the second VCPU.
The fix is to make the pause instruction do "cpu_loop_exit".
Cc: Richard Henderson <rth@twiddle.net>
Reported-by: Luigi Rizzo <rizzo@iet.unipi.it>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-20 12:54:02 +01:00
|
|
|
do_pause(cpu);
|
2012-04-29 20:20:34 +02:00
|
|
|
} else {
|
2013-01-17 18:51:17 +01:00
|
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do_hlt(cpu);
|
2012-04-29 20:20:34 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notify
or aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)
tick, but the timers are only the trigger for a pre-existing problem.
Before the offending patch, setting a timer did a timer_settime system call.
After, setting the timer exits the event loop (which uses poll) and
reenters it with a new deadline. This does not cause any slowdown; the
difference is between one system call (timer_settime and a signal
delivery (SIGALRM) before the patch, and two system calls afterwards
(write to a pipe or eventfd + calling poll again when re-entering the
event loop).
Unfortunately, the exit/enter causes the main loop to grab the iothread
lock, which in turns kicks the VCPU thread out of execution. This
causes TCG to execute the next VCPU in its round-robin scheduling of
VCPUS. When the second VCPU is mostly unused, FreeBSD runs a "pause"
instruction in its idle loop which only burns cycles without any
progress. As soon as the timer tick expires, the first VCPU runs
the interrupt handler but very soon it sets it again---and QEMU
then goes back doing nothing in the second VCPU.
The fix is to make the pause instruction do "cpu_loop_exit".
Cc: Richard Henderson <rth@twiddle.net>
Reported-by: Luigi Rizzo <rizzo@iet.unipi.it>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1384948442-24217-1-git-send-email-pbonzini@redhat.com
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
2013-11-20 12:54:02 +01:00
|
|
|
void helper_pause(CPUX86State *env, int next_eip_addend)
|
|
|
|
{
|
|
|
|
X86CPU *cpu = x86_env_get_cpu(env);
|
|
|
|
|
|
|
|
cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0);
|
|
|
|
env->eip += next_eip_addend;
|
|
|
|
|
|
|
|
do_pause(cpu);
|
|
|
|
}
|
|
|
|
|
2012-04-29 20:42:47 +02:00
|
|
|
void helper_debug(CPUX86State *env)
|
2012-04-29 20:20:34 +02:00
|
|
|
{
|
2013-08-26 08:31:06 +02:00
|
|
|
CPUState *cs = CPU(x86_env_get_cpu(env));
|
|
|
|
|
|
|
|
cs->exception_index = EXCP_DEBUG;
|
2013-08-27 17:52:12 +02:00
|
|
|
cpu_loop_exit(cs);
|
2012-04-29 20:20:34 +02:00
|
|
|
}
|