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qemu-e2k/target/mips/tcg/tx79.decode

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target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
# Toshiba C790's instruction set
#
# Copyright (C) 2021 Philippe Mathieu-Daudé
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
# Toshiba Appendix B C790-Specific Instruction Set Details
###########################################################################
# Named attribute sets. These are used to make nice(er) names
# when creating helpers common to those for the individual
# instruction patterns.
target/mips: Rename 'rtype' as 'r' We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-27 21:13:49 +02:00
&r rs rt rd sa
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
target/mips: Rename 'rtype' as 'r' We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-27 21:13:49 +02:00
&i base rt offset
target/mips/tx79: Introduce LQ opcode (Load Quadword) Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:58:18 +01:00
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
target/mips: Rename 'rtype' as 'r' We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-27 21:13:49 +02:00
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r sa=0
@rt_rd ...... ..... rt:5 rd:5 ..... ...... &r sa=0 rs=0
@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
target/mips: Fix TX79 LQ/SQ opcodes The base register address offset is *signed*. Cc: qemu-stable@nongnu.org Fixes: aaaa82a9f9 ("target/mips/tx79: Introduce LQ opcode (Load Quadword)") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914090447.12557-1-philmd@linaro.org>
2023-09-14 11:02:41 +02:00
@ldst ...... base:5 rt:5 offset:s16 &i
target/mips/tx79: Introduce LQ opcode (Load Quadword) Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:58:18 +01:00
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
2021-02-14 17:20:19 +01:00
MTHI1 011100 ..... 0000000000 00000 010001 @rs
target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-9-f4bug@amsat.org>
2021-02-14 17:57:24 +01:00
MFLO1 011100 0000000000 ..... 00000 010010 @rd
target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-10-f4bug@amsat.org>
2021-02-14 17:20:19 +01:00
MTLO1 011100 ..... 0000000000 00000 010011 @rs
target/mips/tx79: Move PCPYH opcode to decodetree Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-02-13 11:57:56 +01:00
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-02-13 14:40:18 +01:00
# MMI0
PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd
target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-15-f4bug@amsat.org>
2021-02-13 14:22:32 +01:00
PCGTW 011100 ..... ..... ..... 00010 001000 @rs_rt_rd
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-02-13 14:40:18 +01:00
PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd
target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-15-f4bug@amsat.org>
2021-02-13 14:22:32 +01:00
PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-02-13 14:40:18 +01:00
PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd
target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-15-f4bug@amsat.org>
2021-02-13 14:22:32 +01:00
PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd
target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) Introduce the 'Parallel Extend Lower' opcodes: - PEXTLB (Parallel Extend Upper from Byte) - PEXTLH (Parallel Extend Upper from Halfword) - PEXTLW (Parallel Extend Upper from Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-13-f4bug@amsat.org>
2021-02-13 14:42:30 +01:00
PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd
target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-22-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:45:09 +01:00
PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd
target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower) Introduce the 'Parallel Extend Lower' opcodes: - PEXTLB (Parallel Extend Upper from Byte) - PEXTLH (Parallel Extend Upper from Halfword) - PEXTLW (Parallel Extend Upper from Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-13-f4bug@amsat.org>
2021-02-13 14:42:30 +01:00
PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd
PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd
target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <820210309145653.743937-11-f4bug@amsat.org>
2021-02-13 14:40:18 +01:00
target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Introduce the PEXTUW opcode (Parallel Extend Upper from Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-12-f4bug@amsat.org>
2021-02-13 20:42:14 +01:00
# MMI1
target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Introduce the 'Parallel Compare for Equal' opcodes: - PCEQB (Parallel Compare for Equal Byte) - PCEQH (Parallel Compare for Equal Halfword) - PCEQW (Parallel Compare for Equal Word) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-14-f4bug@amsat.org>
2021-02-13 14:43:52 +01:00
PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd
PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd
PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd
target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Introduce the PEXTUW opcode (Parallel Extend Upper from Word). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210309145653.743937-12-f4bug@amsat.org>
2021-02-13 20:42:14 +01:00
PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-02-13 12:04:43 +01:00
# MMI2
PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-16-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 12:24:44 +01:00
PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd
PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd
target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Introduce the PROT3W opcode (Parallel Rotate 3 Words). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-25-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:46:56 +01:00
PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-02-13 12:04:43 +01:00
target/mips/tx79: Move PCPYH opcode to decodetree Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-02-13 11:57:56 +01:00
# MMI3
target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
2021-02-13 12:04:43 +01:00
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-16-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 12:24:44 +01:00
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
target/mips/tx79: Move PCPYH opcode to decodetree Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-12-f4bug@amsat.org>
2021-02-13 11:57:56 +01:00
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
target/mips/tx79: Introduce LQ opcode (Load Quadword) Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-26-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:58:18 +01:00
# SPECIAL
LQ 011110 ..... ..... ................ @ldst
target/mips/tx79: Introduce SQ opcode (Store Quadword) Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210214175912.732946-27-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-02-13 14:47:47 +01:00
SQ 011111 ..... ..... ................ @ldst
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